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nb/amd/mct_ddr3: Consolidate calls to MCT minimum clock setting fetch

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Change-Id: I4497b0be6ed6c90dbb31e89013feed8ff5ff9071
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13885
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Timothy Pearson
2016-03-03 03:05:17 -06:00
committed by Martin Roth
parent 6116f369e9
commit ed85f614b0
1 changed files with 5 additions and 2 deletions
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7
src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
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@@ -1146,6 +1146,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
uint8_t lane; uint8_t lane;
uint8_t nibble; uint8_t nibble;
uint8_t mem_clk; uint8_t mem_clk;
uint16_t min_mem_clk;
uint16_t initial_seed; uint16_t initial_seed;
uint8_t train_both_nibbles; uint8_t train_both_nibbles;
uint16_t current_total_delay[MAX_BYTE_LANES]; uint16_t current_total_delay[MAX_BYTE_LANES];
@@ -1163,6 +1164,8 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
print_debug_dqs("\nTrainRcvEn: Node", pDCTstat->Node_ID, 0); print_debug_dqs("\nTrainRcvEn: Node", pDCTstat->Node_ID, 0);
print_debug_dqs("TrainRcvEn: Pass", Pass, 0); print_debug_dqs("TrainRcvEn: Pass", Pass, 0);
min_mem_clk = mctGet_NVbits(NV_MIN_MEMCLK);
train_both_nibbles = 0; train_both_nibbles = 0;
if (pDCTstat->Dimmx4Present) if (pDCTstat->Dimmx4Present)
if (is_fam15h()) if (is_fam15h())
@@ -1274,7 +1277,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
/* Adjust seed for the minimum platform supported frequency */ /* Adjust seed for the minimum platform supported frequency */
initial_seed = (uint16_t) (((((uint64_t) initial_seed) * initial_seed = (uint16_t) (((((uint64_t) initial_seed) *
fam15h_freq_tab[mem_clk] * 100) / (mctGet_NVbits(NV_MIN_MEMCLK) * 100))); fam15h_freq_tab[mem_clk] * 100) / (min_mem_clk * 100)));
for (lane = 0; lane < MAX_BYTE_LANES; lane++) { for (lane = 0; lane < MAX_BYTE_LANES; lane++) {
uint16_t wl_pass1_delay; uint16_t wl_pass1_delay;
@@ -1304,7 +1307,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
for (lane = 0; lane < MAX_BYTE_LANES; lane++) { for (lane = 0; lane < MAX_BYTE_LANES; lane++) {
seed_prescaling = current_total_delay[lane] - register_delay - 0x20; seed_prescaling = current_total_delay[lane] - register_delay - 0x20;
seed[lane] = (uint16_t) (register_delay + ((((uint64_t) seed_prescaling) * fam15h_freq_tab[mem_clk] * 100) / (mctGet_NVbits(NV_MIN_MEMCLK) * 100))); seed[lane] = (uint16_t) (register_delay + ((((uint64_t) seed_prescaling) * fam15h_freq_tab[mem_clk] * 100) / (min_mem_clk * 100)));
} }
} }