mb, soc/intel: Reorganize CNVi device entries in devicetree

This change reorganizes the CNVi device entries in mainboard
devicetree/overridetree and SoC chipset tree to make it consistent
with how other SoC internal PCI devices are represented i.e. without a
chip driver around the SoC controller itself.

Before:
chip drivers/wifi/generic
	register "wake" = "..."
	device pci xx.y on end
end

After:
device pci xx.y on
	chip drivers/wifi/generic
		register "wake" = "..."
		device generic 0 on end
	end
end

Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb

@@ -86,10 +86,12 @@ chip soc/intel/cannonlake
 			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# Type-A port 3
 		end
 		device pci 14.1 off end # USB xDCI (OTG)
-		chip drivers/wifi/generic # CNVi wifi
-			register "wake" = "GPE0_PME_B0"
-			device pci 14.3 on end
-		end
+		device pci 14.3 on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end  # CNVi wifi
 		device pci 14.5 off end # SDCard
 		device pci 15.0 on	# I2C #0
 			chip drivers/i2c/hid