sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mainboard/asus/p3b-f: Reintroduce as variant of p2b

Browse Source 
Fold this last ASUS 440BX board into the P2B family, while bringing in
some changes:

- Devicetree becomes overridetree.
- Remove non-existent IR device and disable ACPI device on Super I/O to
  match OEM firmware.
- Add SB GPO settings from OEM firmware to devicetree. This disables
  the SPD enabling magic this board needs. By moving the enabling part
  to bootblock the hacky enable_spd hook can be eliminated.
- Initialize the serial port in bootblock, like the other boards.

Boot tested on hardware.

Change-Id: I65f2cb9d1bd4c82550de43889e3502526a46bd18
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41047
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Keith Hui 2020-04-19 00:55:48 -04:00 committed by Patrick Georgi
parent 75476ec303
commit edd38465a5
10 changed files with 21 additions and 106 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/mainboard/asus/p2b/Kconfig
View File

@ -4,7 +4,7 @@
## ##
## SPDX-License-Identifier: GPL-2.0-only ## SPDX-License-Identifier: GPL-2.0-only
if BOARD_ASUS_P2B || BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_DS || BOARD_ASUS_P2B_F || BOARD_ASUS_P2B_LS if BOARD_ASUS_P2B || BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_DS || BOARD_ASUS_P2B_F || BOARD_ASUS_P2B_LS || BOARD_ASUS_P3B_F
config BASE_ASUS_P2B_D config BASE_ASUS_P2B_D
def_bool n def_bool n
@ -21,7 +21,7 @@ config BOARD_SPECIFIC_OPTIONS
select SUPERIO_WINBOND_W83977TF select SUPERIO_WINBOND_W83977TF
select HAVE_PIRQ_TABLE select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256 select BOARD_ROMSIZE_KB_256
select SDRAMPWR_4DIMM if BOARD_ASUS_P2B_LS select SDRAMPWR_4DIMM if BOARD_ASUS_P2B_LS || BOARD_ASUS_P3B_F
select HAVE_ACPI_TABLES if BOARD_ASUS_P2B || BOARD_ASUS_P2B_LS select HAVE_ACPI_TABLES if BOARD_ASUS_P2B || BOARD_ASUS_P2B_LS
select BASE_ASUS_P2B_D if BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_DS select BASE_ASUS_P2B_D if BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_DS
@ -40,6 +40,7 @@ config MAINBOARD_PART_NUMBER
default "P2B-DS" if BOARD_ASUS_P2B_DS default "P2B-DS" if BOARD_ASUS_P2B_DS
default "P2B-F" if BOARD_ASUS_P2B_F default "P2B-F" if BOARD_ASUS_P2B_F
default "P2B-LS" if BOARD_ASUS_P2B_LS default "P2B-LS" if BOARD_ASUS_P2B_LS
default "P3B-F" if BOARD_ASUS_P3B_F
config VARIANT_DIR config VARIANT_DIR
string string
@ -48,6 +49,7 @@ config VARIANT_DIR
default "p2b-ds" if BOARD_ASUS_P2B_DS default "p2b-ds" if BOARD_ASUS_P2B_DS
default "p2b-f" if BOARD_ASUS_P2B_F default "p2b-f" if BOARD_ASUS_P2B_F
default "p2b-ls" if BOARD_ASUS_P2B_LS default "p2b-ls" if BOARD_ASUS_P2B_LS
default "p3b-f" if BOARD_ASUS_P3B_F
config OVERRIDE_DEVICETREE config OVERRIDE_DEVICETREE
string string
@ -55,7 +57,7 @@ config OVERRIDE_DEVICETREE
config IRQ_SLOT_COUNT config IRQ_SLOT_COUNT
int int
default 8 if BOARD_ASUS_P2B_LS default 8 if BOARD_ASUS_P2B_LS || BOARD_ASUS_P3B_F
default 7 if BOARD_ASUS_P2B_F || BOARD_ASUS_P2B_DS default 7 if BOARD_ASUS_P2B_F || BOARD_ASUS_P2B_DS
default 6 default 6

3
src/mainboard/asus/p2b/Kconfig.name
View File

@ -12,3 +12,6 @@ config BOARD_ASUS_P2B_F
config BOARD_ASUS_P2B_LS config BOARD_ASUS_P2B_LS
bool "P2B-LS" bool "P2B-LS"
config BOARD_ASUS_P3B_F
bool "P3B-F"

1
src/mainboard/asus/p2b/Makefile.inc
View File

@ -1,4 +1,5 @@
bootblock-y += bootblock.c bootblock-y += bootblock.c
romstage-$(CONFIG_BOARD_ASUS_P3B_F) += variants/$(VARIANT_DIR)/romstage.c
ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += variants/$(VARIANT_DIR)/irq_tables.c ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += variants/$(VARIANT_DIR)/irq_tables.c
ramstage-$(CONFIG_GENERATE_MP_TABLE) += variants/$(VARIANT_DIR)/mptable.c ramstage-$(CONFIG_GENERATE_MP_TABLE) += variants/$(VARIANT_DIR)/mptable.c

0
src/mainboard/asus/p3b-f/board_info.txt → src/mainboard/asus/p2b/variants/p3b-f/board_info.txt
View File

0
src/mainboard/asus/p3b-f/irq_tables.c → src/mainboard/asus/p2b/variants/p3b-f/irq_tables.c
View File

12
src/mainboard/asus/p2b/variants/p3b-f/overridetree.cb Normal file
View File

@ -0,0 +1,12 @@
chip northbridge/intel/i440bx # Northbridge
device domain 0 on # PCI domain
chip southbridge/intel/i82371eb # Southbridge
register "gpo" = "0x67ffbfff" # GPIO: This value sets GPIOs 27,28 to expose HWM
device pci 4.0 on # ISA bridge
chip superio/winbond/w83977tf # Super I/O
device pnp 3f0.a off end # ACPI
end
end
end
end
end

11
src/mainboard/asus/p3b-f/romstage.c → src/mainboard/asus/p2b/variants/p3b-f/romstage.c
View File

@ -4,12 +4,6 @@
#include <arch/io.h> #include <arch/io.h>
#include <southbridge/intel/i82371eb/i82371eb.h> #include <southbridge/intel/i82371eb/i82371eb.h>
#include <northbridge/intel/i440bx/raminit.h> #include <northbridge/intel/i440bx/raminit.h>
#include <superio/winbond/common/winbond.h>
/* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
#include <superio/winbond/w83977tf/w83977tf.h>
/* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
/* /*
* ASUS P3B-F specific SPD enable magic. * ASUS P3B-F specific SPD enable magic.
@ -41,8 +35,3 @@ void disable_spd(void)
{ {
outb(0x67, PM_IO_BASE + 0x37); outb(0x67, PM_IO_BASE + 0x37);
} }
void mainboard_enable_serial(void)
{
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}

31
src/mainboard/asus/p3b-f/Kconfig
View File

@ -1,31 +0,0 @@
##
## This file is part of the coreboot project.
##
##
## SPDX-License-Identifier: GPL-2.0-only
if BOARD_ASUS_P3B_F
config BOARD_SPECIFIC_OPTIONS
def_bool y
select CPU_INTEL_SLOT_1
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83977TF
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256
select SDRAMPWR_4DIMM
config MAINBOARD_DIR
string
default "asus/p3b-f"
config MAINBOARD_PART_NUMBER
string
default "P3B-F"
config IRQ_SLOT_COUNT
int
default 8
endif # BOARD_ASUS_P3B_F

2
src/mainboard/asus/p3b-f/Kconfig.name
View File

@ -1,2 +0,0 @@
config BOARD_ASUS_P3B_F
bool "P3B-F"

59
src/mainboard/asus/p3b-f/devicetree.cb
View File

@ -1,59 +0,0 @@
chip northbridge/intel/i440bx # Northbridge
device cpu_cluster 0 on # APIC cluster
chip cpu/intel/slot_1 # CPU
device lapic 0 on end # APIC
end
end
device domain 0 on # PCI domain
device pci 0.0 on end # Host bridge
device pci 1.0 on end # PCI/AGP bridge
chip southbridge/intel/i82371eb # Southbridge
device pci 4.0 on # ISA bridge
chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!)
device pnp 3f0.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 3f0.1 on # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 3f0.2 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 3f0.3 on # COM2 / IR
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 3f0.5 on # PS/2 keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1 # PS/2 keyboard interrupt
irq 0x72 = 12 # PS/2 mouse interrupt
end
device pnp 3f0.6 on # Consumer IR
end
device pnp 3f0.7 on # GPIO 1
end
device pnp 3f0.8 on # GPIO 2
end
device pnp 3f0.a on # ACPI
end
end
end
device pci 4.1 on end # IDE
device pci 4.2 on end # USB
device pci 4.3 on end # ACPI
register "ide0_enable" = "1"
register "ide1_enable" = "1"
register "ide_legacy_enable" = "1"
# Enable UDMA/33 for higher speed if your IDE device(s) support it.
register "ide0_drive0_udma33_enable" = "0"
register "ide0_drive1_udma33_enable" = "0"
register "ide1_drive0_udma33_enable" = "0"
register "ide1_drive1_udma33_enable" = "0"
end
end
end