From edd97f35bd91e1ae3c2f6d59487f4ff3850d8633 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Thu, 21 Jan 2021 09:01:11 -0700 Subject: [PATCH] Correct darp7 PL2 Change-Id: I51f047b62a8a2eadcaf89a4c6e6041d5bb9d1331 --- src/mainboard/system76/darp7/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/system76/darp7/devicetree.cb b/src/mainboard/system76/darp7/devicetree.cb index dbafa2d436..82195918a5 100644 --- a/src/mainboard/system76/darp7/devicetree.cb +++ b/src/mainboard/system76/darp7/devicetree.cb @@ -25,13 +25,13 @@ chip soc/intel/tigerlake // /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw .tdp_pl1_override = 28, // /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw - .tdp_pl2_override = 51, + .tdp_pl2_override = 40, }" register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ // /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw .tdp_pl1_override = 28, // /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw - .tdp_pl2_override = 51, + .tdp_pl2_override = 40, }" # Finalize (soc/intel/tigerlake/finalize.c)