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soc/amd/*/psp: move MSR_CU_CBBCFG to common and rename to MSR_PSP_ADDR

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TEST=Checked that the MSR is the same for Stoneyridge, Picasso and
Cezanne.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id15715ed1c17f4fc475985dcb1c31a83713ee65c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Felix Held
2021-01-29 22:31:40 +01:00
parent 5ddcfe5ec1
commit ee04881360
4 changed files with 6 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/amd/common/block/include/amdblocks/psp.h
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@@ -3,6 +3,8 @@
#ifndef AMD_BLOCK_PSP_H #ifndef AMD_BLOCK_PSP_H
#define AMD_BLOCK_PSP_H #define AMD_BLOCK_PSP_H
#define MSR_PSP_ADDR 0xc00110a2
/* Get the mailbox base address - specific to family of device. */ /* Get the mailbox base address - specific to family of device. */
void *soc_get_mbox_address(void); void *soc_get_mbox_address(void);

5
src/soc/amd/picasso/psp.c
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@@ -8,15 +8,14 @@
#include <amdblocks/smi.h> #include <amdblocks/smi.h>
#define PSP_MAILBOX_OFFSET 0x10570 #define PSP_MAILBOX_OFFSET 0x10570
#define MSR_CU_CBBCFG 0xc00110a2
void *soc_get_mbox_address(void) void *soc_get_mbox_address(void)
{ {
uintptr_t psp_mmio; uintptr_t psp_mmio;
psp_mmio = rdmsr(MSR_CU_CBBCFG).lo; psp_mmio = rdmsr(MSR_PSP_ADDR).lo;
if (psp_mmio == 0xffffffff) { if (psp_mmio == 0xffffffff) {
printk(BIOS_WARNING, "PSP: MSR_CU_CBBCFG uninitialized\n"); printk(BIOS_WARNING, "PSP: MSR_PSP_ADDR uninitialized\n");
return 0; return 0;
} }

2
src/soc/amd/stoneyridge/include/soc/southbridge.h
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@@ -205,8 +205,6 @@ void soc_enable_psp_early(void);
#define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */ #define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */
#define PSP_MAILBOX_BAR_EN BIT(4) #define PSP_MAILBOX_BAR_EN BIT(4)
#define MSR_CU_CBBCFG 0xc00110a2 /* PSP Pvt Blk Base Addr */
typedef struct aoac_devs { typedef struct aoac_devs {
unsigned int :5; unsigned int :5;
unsigned int ic0e:1; /* 5: I2C0 */ unsigned int ic0e:1; /* 5: I2C0 */

4
src/soc/amd/stoneyridge/psp.c
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@@ -44,9 +44,9 @@ void *soc_get_mbox_address(void)
/* Determine if Bar3Hide has been set, and if hidden get the base from /* Determine if Bar3Hide has been set, and if hidden get the base from
* the MSR instead. */ * the MSR instead. */
if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) { if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) {
psp_mmio = rdmsr(MSR_CU_CBBCFG).lo; psp_mmio = rdmsr(MSR_PSP_ADDR).lo;
if (psp_mmio == 0xffffffff) { if (psp_mmio == 0xffffffff) {
printk(BIOS_WARNING, "PSP: BAR hidden, MSR val uninitialized\n"); printk(BIOS_WARNING, "PSP: BAR hidden, MSR_PSP_ADDR uninitialized\n");
return 0; return 0;
} }
} else { } else {