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mainboard/ocp/monolake: Hide IIO root ports before memory init

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It turned on some SKUs FSP hangs in Notify stage if IIO root ports are
disabled after MemoryInit. To address that hide IIO root ports earlier
in romstage.

TEST=the patch was ran on affected HW and success was reported

Change-Id: I6a2a405f729df14f46bcf34a24e66e8ba9415f9d
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Andrey Petrov
2019-10-11 11:31:08 -07:00
committed by Patrick Georgi
parent 89f5967647
commit ee0b7ad683
5 changed files with 52 additions and 24 deletions
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7
Documentation/soc/intel/fsp/index.md
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@@ -21,6 +21,12 @@ those are fixed. If possible a workaround is described here as well.
* Workaround: Don't disable this PCI device
* Issue on public tracker: [Issue 13]
* FSP Notify(EnumInitPhaseAfterPciEnumeration) hangs if 00:02.03/00:02.03 are hidden
* Release MR2
* Seems to get stuck on some SKUs only if hidden after MemoryInit
* Workaround: Hide before MemoryInit
* Issue on public tracker: [Issue 35]
### KabylakeFsp
* MfgId and ModulePartNum in the DIMM_INFO struct are empty
* Release 3.7.1
@@ -59,4 +65,5 @@ those are fixed. If possible a workaround is described here as well.
[Issue 13]: https://github.com/IntelFsp/FSP/issues/13
[Issue 15]: https://github.com/IntelFsp/FSP/issues/15
[Issue 22]: https://github.com/IntelFsp/FSP/issues/22
[Issue 35]: https://github.com/IntelFsp/FSP/issues/35