From ee224859e19ede334fc370f46e70a7108ffc11dd Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Wed, 31 Mar 2021 09:47:04 -0600 Subject: [PATCH] mb/system76/whl-u: Fix USB-C/TBT Partially revert 37c69a0123f to restore USB-C and likely TBT functionality on galp3-c. Fixes: 37c69a0123f ("Update whl-u to match cml-u") Change-Id: I6fc189b3185d51cd8e67ae2d1eedef65a6049a12 --- src/mainboard/system76/whl-u/gpio.h | 4 +- src/mainboard/system76/whl-u/ramstage.c | 123 ------------------------ 2 files changed, 2 insertions(+), 125 deletions(-) diff --git a/src/mainboard/system76/whl-u/gpio.h b/src/mainboard/system76/whl-u/gpio.h index 68b5d73b40..9003dae636 100644 --- a/src/mainboard/system76/whl-u/gpio.h +++ b/src/mainboard/system76/whl-u/gpio.h @@ -219,7 +219,7 @@ static const struct pad_config gpio_table[] = { // TBCIO_PLUG_EVENT _PAD_CFG_STRUCT(GPP_C9, 0x82880100, 0x3000), // TBT_FRC_PWR - PAD_CFG_TERM_GPO(GPP_C10, 0, NONE, PLTRST), + PAD_CFG_TERM_GPO(GPP_C10, 1, NONE, PLTRST), // NC PAD_CFG_NC(GPP_C11), @@ -524,7 +524,7 @@ static const struct pad_config gpio_table[] = { // GPPC_H21 PAD_CFG_NC(GPP_H21), // TBT_RTD3_PWR_EN_R - PAD_NC(GPP_H22, NONE), + PAD_CFG_TERM_GPO(GPP_H22, 1, NONE, PLTRST), // NC, WIGIG_PEWAKE PAD_CFG_NC(GPP_H23), }; diff --git a/src/mainboard/system76/whl-u/ramstage.c b/src/mainboard/system76/whl-u/ramstage.c index 72b680724a..fcc5b8f2b1 100644 --- a/src/mainboard/system76/whl-u/ramstage.c +++ b/src/mainboard/system76/whl-u/ramstage.c @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include -#include -#include #include #include #include @@ -66,128 +63,8 @@ static void mainboard_init(struct device *dev) { } } -static bool mainboard_pcie_hotplug(int port_number) { - printk(BIOS_DEBUG, "system76: pcie_hotplug(%d)\n", port_number); - /* RP01 */ - return port_number == 0; -} - -static void pcie_hotplug_generator(int port_number) -{ - int port; - int have_hotplug = 0; - - for (port = 0; port < port_number; port++) { - if (mainboard_pcie_hotplug(port)) { - have_hotplug = 1; - } - } - - if (!have_hotplug) { - return; - } - - for (port = 0; port < port_number; port++) { - if (mainboard_pcie_hotplug(port)) { - char scope_name[] = "\\_SB.PCI0.RP0x"; - scope_name[sizeof("\\_SB.PCI0.RP0x") - 2] = '1' + port; - acpigen_write_scope(scope_name); - - /* - Device (SLOT) - { - Name (_ADR, 0x00) - Method (_RMV, 0, NotSerialized) - { - Return (0x01) - } - } - */ - - acpigen_write_device("SLOT"); - - acpigen_write_name_byte("_ADR", 0x00); - - acpigen_write_method("_RMV", 0); - /* ReturnOp */ - acpigen_emit_byte (0xa4); - /* One */ - acpigen_emit_byte (0x01); - acpigen_pop_len(); - acpigen_pop_len(); - acpigen_pop_len(); - } - } - - /* Method (_L01, 0, NotSerialized) - { - If (\_SB.PCI0.RP04.HPCS) - { - Sleep (100) - Store (0x01, \_SB.PCI0.RP04.HPCS) - If (\_SB.PCI0.RP04.PDC) - { - Store (0x01, \_SB.PCI0.RP04.PDC) - Notify (\_SB.PCI0.RP04, 0x00) - } - } - } - - */ - acpigen_write_scope("\\_GPE"); - acpigen_write_method("_L01", 0); - for (port = 0; port < port_number; port++) { - if (mainboard_pcie_hotplug(port)) { - char reg_name[] = "\\_SB.PCI0.RP0x.HPCS"; - reg_name[sizeof("\\_SB.PCI0.RP0x") - 2] = '1' + port; - acpigen_emit_byte(0xa0); /* IfOp. */ - acpigen_write_len_f(); - acpigen_emit_namestring(reg_name); - - /* Sleep (100) */ - acpigen_emit_byte(0x5b); /* SleepOp. */ - acpigen_emit_byte(0x22); - acpigen_write_byte(100); - - /* Store (0x01, \_SB.PCI0.RP04.HPCS) */ - acpigen_emit_byte(0x70); - acpigen_emit_byte(0x01); - acpigen_emit_namestring(reg_name); - - memcpy(reg_name + sizeof("\\_SB.PCI0.RP0x.") - 1, "PDC", 4); - - /* If (\_SB.PCI0.RP04.PDC) */ - acpigen_emit_byte(0xa0); /* IfOp. */ - acpigen_write_len_f(); - acpigen_emit_namestring(reg_name); - - /* Store (0x01, \_SB.PCI0.RP04.PDC) */ - acpigen_emit_byte(0x70); - acpigen_emit_byte(0x01); - acpigen_emit_namestring(reg_name); - - reg_name[sizeof("\\_SB.PCI0.RP0x") - 1] = '\0'; - - /* Notify(\_SB.PCI0.RP04, 0x00) */ - acpigen_emit_byte(0x86); - acpigen_emit_namestring(reg_name); - acpigen_emit_byte(0x00); - acpigen_pop_len(); - acpigen_pop_len(); - } - } - acpigen_pop_len(); - acpigen_pop_len(); -} - -static void fill_ssdt(const struct device *device) { - printk(BIOS_INFO, "system76: fill_ssdt\n"); - pcie_hotplug_generator(CONFIG_MAX_ROOT_PORTS); -} - static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_fill_ssdt = fill_ssdt; // Configure pad for DisplayPort uint32_t config = 0x44000200;