arch/x86: Unify bootblock MMX register usage

Have same usage of registers with romcc bootblock
and C_ENVIRONMENT_BOOTBLOCK.

Change-Id: Ibfa80e40f0b736a904abf4245fc23efc0cdc458d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/arch/x86/timestamp.inc

@@ -13,8 +13,8 @@
 
 /*
  * Store the initial timestamp for booting in mmx registers. This works
- * because the bootblock isn't being compiled with MMX support so mm0 and
- * mm1 will be preserved into romstage.
+ * because the bootblock isn't being compiled with MMX support so mm1 and
+ * mm2 will be preserved into romstage.
  */
 	.code32
 
@@ -22,12 +22,13 @@
 stash_timestamp:
 
 	/* Save the BIST value */
-	movl	%eax, %ebp
+	movl	%eax, %ebx
 
 	finit
 	rdtsc
-	movd	%eax, %mm0
-	movd	%edx, %mm1
+	movd	%ebx, %mm0
+	movd	%eax, %mm1
+	movd	%edx, %mm2
 
 	/* Restore the BIST value to %eax */
-	movl	%ebp, %eax
+	movl	%ebx, %eax

src/drivers/intel/fsp1_1/cache_as_ram.inc

@@ -29,11 +29,20 @@
 #define LHLT_DELAY	0x50000		/* I/O delay between post codes on failure */
 
 	/*
-	 * eax:  BIST value
-	 * mm0:  low 32-bits of TSC value
-	 * mm1:  high 32-bits of TSC value
+	 * Per FSP1.1 specs, following registers are preserved:
+	 * EBX, EDI, ESI, EBP, MM0, MM1
+	 *
+	 * Shift values to release MM2.
+	 * mm0 -> edi:  BIST value
+	 * mm1 -> mm0:  low 32-bits of TSC value
+	 * mm2 -> mm1:  high 32-bits of TSC value
 	 */
-	movl	%eax, %edi
+	movd	%mm0, %edi
+	movd	%mm1, %eax
+	movd	%eax, %mm0
+	movd	%mm2, %eax
+	movd	%eax, %mm1
+
 cache_as_ram:
 	post_code(0x20)
 

src/soc/intel/baytrail/romstage/cache_as_ram.inc

@@ -36,9 +36,6 @@
 #define NoEvictMod_MSR 0x2e0
 #define BBL_CR_CTL3_MSR 0x11e
 
-	/* Save the BIST result. */
-	movl	%eax, %ebp
-
 cache_as_ram:
 	post_code(0x20)
 
@@ -183,14 +180,13 @@ addrsize_set_high:
 	movl	%eax, %esp
 
 	/* Push the initial TSC value from boot block. The low 32 bits are
-	 * in mm0, and the high 32 bits are in mm1. */
+	 * in mm1, and the high 32 bits are in mm2. */
+	movd	%mm2, %eax
+	pushl	%eax
 	movd	%mm1, %eax
 	pushl	%eax
-	movd	%mm0, %eax
-	pushl	%eax
 	/* Restore the BIST result. */
-	movl	%ebp, %eax
-	movl	%esp, %ebp
+	movd	%mm0, %eax
 	pushl	%eax
 
 before_romstage: