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arch/x86: Unify bootblock MMX register usage

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Have same usage of registers with romcc bootblock
and C_ENVIRONMENT_BOOTBLOCK.

Change-Id: Ibfa80e40f0b736a904abf4245fc23efc0cdc458d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki
2018-12-28 16:06:45 +02:00
parent 6267f5dd11
commit ee2e936f40
3 changed files with 24 additions and 18 deletions
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17
src/drivers/intel/fsp1_1/cache_as_ram.inc
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@ -29,11 +29,20 @@
#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */
/*
* eax: BIST value
* mm0: low 32-bits of TSC value
* mm1: high 32-bits of TSC value
* Per FSP1.1 specs, following registers are preserved:
* EBX, EDI, ESI, EBP, MM0, MM1
*
* Shift values to release MM2.
* mm0 -> edi: BIST value
* mm1 -> mm0: low 32-bits of TSC value
* mm2 -> mm1: high 32-bits of TSC value
*/
movl %eax, %edi
movd %mm0, %edi
movd %mm1, %eax
movd %eax, %mm0
movd %mm2, %eax
movd %eax, %mm1
cache_as_ram:
post_code(0x20)