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Revert "intel/lynxpoint,broadwell: Fix eDP display in Windows, SeaBios & Tiano"

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We've been able to narrow down the problem to a single register/
single bit, so revert this commit and address the problem in a
follow-on commit.

This reverts commit 0f2025da0fd4dce6b951b4c4b97c9370ca7d66db.

Change-Id: I780f9ea2976dd223aaa3e060aef6e1af8012c346
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18384
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Matt DeVillier 2017-02-16 11:45:19 -06:00 committed by Martin Roth
parent efd9dee646
commit ee6a612eb2
4 changed files with 0 additions and 22 deletions
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9
src/soc/intel/broadwell/Kconfig
View File

@ -208,13 +208,4 @@ config CHIPSET_BOOTBLOCK_INCLUDE
string string
default "soc/intel/broadwell/bootblock/timestamp.inc" default "soc/intel/broadwell/bootblock/timestamp.inc"
config BROADWELL_POWER_OPTIMIZER
bool "Enable Power Optimizer"
default y if CHROMEOS
help
Enable the power optimizer for the High Speed I/O
Power Control (HSIOPC). This can break graphics
under Windows, but can improve battery life under
'mostly idle' conditions.
endif endif

2
src/soc/intel/broadwell/lpc.c
View File

@ -260,7 +260,6 @@ static const struct reg_script pch_pm_init_script[] = {
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33b4, 0x00007001), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33b4, 0x00007001),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3350, 0x022ddfff), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3350, 0x022ddfff),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3354, 0x00000001), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3354, 0x00000001),
#if IS_ENABLED(CONFIG_BROADWELL_POWER_OPTIMIZER)
/* Power Optimizer */ /* Power Optimizer */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x08000000), REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x08000000),
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x08000080), REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x08000080),
@ -272,7 +271,6 @@ static const struct reg_script pch_pm_init_script[] = {
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a84, 0x00001005), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a84, 0x00001005),
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x2fff2fb1), REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x2fff2fb1),
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x00008000), REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x00008000),
#endif
REG_SCRIPT_END REG_SCRIPT_END
}; };

9
src/southbridge/intel/lynxpoint/Kconfig
View File

@ -97,13 +97,4 @@ config LOCK_MANAGEMENT_ENGINE
bool bool
default n default n
config LYNXPOINT_POWER_OPTIMIZER
bool "Enable Power Optimizer"
default y if CHROMEOS
help
Enable the power optimizer for the High Speed I/O
Power Control (HSIOPC). This can break graphics
under Windows, but can improve battery life under
'mostly idle' conditions.
endif endif

2
src/southbridge/intel/lynxpoint/lpc.c
View File

@ -346,7 +346,6 @@ const struct rcba_config_instruction lpt_lp_pm_rcba[] = {
RCBA_RMW_REG_32(0x33b4, 0, 0x00007001), RCBA_RMW_REG_32(0x33b4, 0, 0x00007001),
RCBA_RMW_REG_32(0x3350, 0, 0x022ddfff), RCBA_RMW_REG_32(0x3350, 0, 0x022ddfff),
RCBA_RMW_REG_32(0x3354, 0, 0x00000001), RCBA_RMW_REG_32(0x3354, 0, 0x00000001),
#if IS_ENABLED(CONFIG_LYNXPOINT_POWER_OPTIMIZER)
RCBA_RMW_REG_32(0x33d4, ~0, 0x08000000), /* Power Optimizer */ RCBA_RMW_REG_32(0x33d4, ~0, 0x08000000), /* Power Optimizer */
RCBA_RMW_REG_32(0x33c8, ~0, 0x08000080), /* Power Optimizer */ RCBA_RMW_REG_32(0x33c8, ~0, 0x08000080), /* Power Optimizer */
RCBA_RMW_REG_32(0x2b10, 0, 0x0000883c), /* Power Optimizer */ RCBA_RMW_REG_32(0x2b10, 0, 0x0000883c), /* Power Optimizer */
@ -354,7 +353,6 @@ const struct rcba_config_instruction lpt_lp_pm_rcba[] = {
RCBA_RMW_REG_32(0x2b24, 0, 0x40000005), /* Power Optimizer */ RCBA_RMW_REG_32(0x2b24, 0, 0x40000005), /* Power Optimizer */
RCBA_RMW_REG_32(0x2b20, 0, 0x0005db01), /* Power Optimizer */ RCBA_RMW_REG_32(0x2b20, 0, 0x0005db01), /* Power Optimizer */
RCBA_RMW_REG_32(0x3a80, 0, 0x05145005), RCBA_RMW_REG_32(0x3a80, 0, 0x05145005),
#endif
RCBA_END_CONFIG RCBA_END_CONFIG
}; };