cpu/x86: Link page tables in stage if possible

When switching back and forth between 32 to 64 bit mode, for example to
call a 32-bits FSP or to call the payload, new page tables in the
respective stage will be linked.

The advantages of this approach are:
- No need to determine a good place for page tables in CBFS that does
  not overlap.
- Works with non memory mapped flash (however all coreboot targets
  currently do support this)
- If later stages can use their own page tables which fits better with
  the vboot RO/RW flow

A disadvantage is that it increases the stage size. This could be
improved upon by using 1G pages and generating the pages at runtime.

Note: qemu cannot have the page tables in the RO boot medium and needs
to relocate them at runtime. This is why keeping the existing code with
page tables in CBFS is done for now.

TEST: Booted to payload on google/vilbox and qemu/q35

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80337
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/arch/x86/Kconfig

@@ -83,9 +83,13 @@ config USE_EXP_X86_64_SUPPORT
 	  is an experimental option: do not enable unless one wants to test it
 	  and has the means to recover a system when coreboot fails to boot.
 
+config PAGE_TABLES_IN_CBFS
+	bool
+	default n
+
 config ARCH_X86_64_PGTBL_LOC
 	hex "x86_64 page table location in CBFS"
-	depends on ARCH_BOOTBLOCK_X86_64
+	depends on ARCH_BOOTBLOCK_X86_64 && PAGE_TABLES_IN_CBFS
 	default 0xfffe9000
 	help
 	  The position where to place pagetables. Needs to be known at