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Unbreak boards where chipset can select between FSB and serial APIC bus

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Commit d4d5e4d3e10da06a83d57a147bd58a733381de18 contains #ifdef instead
of #if, making the FSB/serial bus selection for APIC always select serial
bus. The bug is harmless on most chipsets because the bit is often RO,
but it breaks at least on VIA K8T890.

Change-Id: I89c4855922199eca7f921c3e4eb500656544c8e5
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/921
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
This commit is contained in:
Rudolf Marek 2012-04-22 23:52:23 +02:00 committed by Peter Stuge
parent 770c44d20f
commit eeb8a06b03
1 changed files with 2 additions and 2 deletions
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4
src/arch/x86/lib/ioapic.c
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@ -89,7 +89,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
ioapic_interrupts = 24; ioapic_interrupts = 24;
printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts);
#ifdef CONFIG_IOAPIC_INTERRUPTS_ON_FSB #if CONFIG_IOAPIC_INTERRUPTS_ON_FSB
/* /*
* For the Pentium 4 and above APICs deliver their interrupts * For the Pentium 4 and above APICs deliver their interrupts
* on the front side bus, enable that. * on the front side bus, enable that.
@ -98,7 +98,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
io_apic_write(ioapic_base, 0x03, io_apic_write(ioapic_base, 0x03,
io_apic_read(ioapic_base, 0x03) | (1 << 0)); io_apic_read(ioapic_base, 0x03) | (1 << 0));
#endif #endif
#ifdef CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS #if CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n");
io_apic_write(ioapic_base, 0x03, 0); io_apic_write(ioapic_base, 0x03, 0);
#endif #endif