soc/intel/apollolake: utilize postcar phase/stage

The current Apollolake flow has its code executing out of
cache-as-ram for the pre-DRAM stages. This is different from
past platforms where they were just executing-in-place against
the memory-mapped SPI flash boot media. The implication is
that when cache-as-ram needs to be torn down one needs to be
executing out of DRAM since the act of cache-as-ram going
away means the code disappears out from under the processor.
Therefore load and use the postcar infrastructure to bootstrap
this process for tearing down cache-as-ram and subsequently
loading ramstage.

Change-Id: I856f4b992dd2609b95375767bfa4fe64a267d89e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14141
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/soc/intel/apollolake/Makefile.inc

@@ -37,6 +37,11 @@ ramstage-y += mmap_boot.c
 ramstage-y += uart.c
 ramstage-y += northbridge.c
 
+postcar-y += exit_car.S
+postcar-y += memmap.c
+postcar-y += mmap_boot.c
+postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
+
 CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
 
 endif