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nb/x4x/raminit: Fix programming dram timings

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The results were obtained by comparing the MCHBAR registers of vendor bios
with coreboot at the same dram timings.

This fixes 2 issues:
* 1333MHz fsb CPUs were limited to 667MHz ddr2 speeds, because with
  800MHz raminit failed;
* 1067MHz fsb CPUs did not boot when second dimm slot was populated.

TESTED on ga-g41m-es2l on 800, 1067 and 1333MHz CPUs with
DDR2 667 and 800MHz dimms.

Change-Id: I70f554f97b44947c2c78713b4d73a47c06d7ba60
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18022
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Arthur Heymans
2017-01-03 00:49:45 +01:00
committed by Martin Roth
parent acbb70b810
commit eee4f6b224
2 changed files with 11 additions and 9 deletions
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4
src/northbridge/intel/x4x/raminit.c
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@@ -228,9 +228,7 @@ static void sdram_detect_ram_speed(struct sysinfo *s)
// Max RAM speed
if (s->spd_type == DDR2) {
// FIXME: Limit memory speed to 667MHz if FSB is 1333MHz
maxfreq = (s->max_fsb == FSB_CLOCK_1333MHz)
? MEM_CLOCK_667MHz : MEM_CLOCK_800MHz;
maxfreq = MEM_CLOCK_800MHz;
// Choose common CAS latency from {6,5}, 4 does not work
commoncas = 0x60;