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Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-34

Browse Source 
Creator:  Yinghai Lu <yhlu@tyan.com>

AMD D0/E0 Opteron new mem mapping support, AMD E Opteron mem hole support,AMD K8 Four Ranks DIMM support


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
arch import user (historical)
2005-07-06 17:15:30 +00:00
parent 014c3e185f
commit ef03afa405
105 changed files with 4396 additions and 1603 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/cpu/amd/dualcore/Config.lb Normal file
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@ -0,0 +1,5 @@
uses CONFIG_LOGICAL_CPUS
if CONFIG_LOGICAL_CPUS
object amd_sibling.o
end

244
src/cpu/amd/dualcore/amd_sibling.c Normal file
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@ -0,0 +1,244 @@
/* 2004.12 yhlu add dual core support */
#include <console/console.h>
#include <cpu/cpu.h>
#include <cpu/x86/lapic.h>
#include <cpu/amd/dualcore.h>
#include <device/device.h>
#include <device/pci.h>
#include <pc80/mc146818rtc.h>
#include <smp/spinlock.h>
#include <cpu/x86/mtrr.h>
#include "../model_fxx/model_fxx_msr.h"
#include "../../../northbridge/amd/amdk8/cpu_rev.c"
static int first_time = 1;
static int disable_siblings = !CONFIG_LOGICAL_CPUS;
int is_e0_later_in_bsp(int nodeid)
{
uint32_t val;
uint32_t val_old;
int e0_later;
if(nodeid==0) { // we don't need to do that for node 0 in core0/node0
return !is_cpu_pre_e0();
}
// d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0
device_t dev;
dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid,2));
if(!dev) return 0;
val_old = pci_read_config32(dev, 0x80);
val = val_old;
val |= (1<<3);
pci_write_config32(dev, 0x80, val);
val = pci_read_config32(dev, 0x80);
e0_later = !!(val & (1<<3));
if(e0_later) { // pre_e0 bit 3 always be 0 and can not be changed
pci_write_config32(dev, 0x80, val_old); // restore it
}
return e0_later;
}
unsigned int read_nb_cfg_54(void)
{
msr_t msr;
msr = rdmsr(NB_CFG_MSR);
return ( ( msr.hi >> (54-32)) & 1);
}
struct node_core_id get_node_core_id(unsigned int nb_cfg_54) {
struct node_core_id id;
// get the apicid via cpuid(1) ebx[27:24]
if(nb_cfg_54) {
// when NB_CFG[54] is set, nodid = ebx[27:25], coreid = ebx[24]
id.coreid = (cpuid_ebx(1) >> 24) & 0xf;
id.nodeid = (id.coreid>>1);
id.coreid &= 1;
} else { // single core should be here too
// when NB_CFG[54] is clear, nodeid = ebx[26:24], coreid = ebx[27]
id.nodeid = (cpuid_ebx(1) >> 24) & 0xf;
id.coreid = (id.nodeid>>3);
id.nodeid &= 7;
}
return id;
}
static int get_max_siblings(int nodes)
{
device_t dev;
int nodeid;
int siblings=0;
//get max siblings from all the nodes
for(nodeid=0; nodeid<nodes; nodeid++){
int j;
dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 3));
j = (pci_read_config32(dev, 0xe8) >> 12) & 3;
if(siblings < j) {
siblings = j;
}
}
return siblings;
}
static void enable_apic_ext_id(int nodes)
{
device_t dev;
int nodeid;
//enable APIC_EXIT_ID all the nodes
for(nodeid=0; nodeid<nodes; nodeid++){
uint32_t val;
dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0));
val = pci_read_config32(dev, 0x68);
val |= (1<<17)|(1<<18);
pci_write_config32(dev, 0x68, val);
}
}
unsigned get_apicid_base(unsigned ioapic_num)
{
device_t dev;
int nodes;
unsigned apicid_base;
int siblings;
unsigned nb_cfg_54;
int bsp_apic_id = lapicid(); // bsp apicid
int disable_siblings = !CONFIG_LOGICAL_CPUS;
get_option(&disable_siblings, "dual_core");
//get the nodes number
dev = dev_find_slot(0, PCI_DEVFN(0x18,0));
nodes = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1;
siblings = get_max_siblings(nodes);
if(bsp_apic_id > 0) { // io apic could start from 0
return 0;
} else if(pci_read_config32(dev, 0x68) & ( (1<<17) | (1<<18)) ) { // enabled ext id but bsp = 0
if(!disable_siblings) { return siblings + 1; }
else { return 1; }
}
nb_cfg_54 = read_nb_cfg_54();
#if 0
//it is for all e0 single core and nc_cfg_54 low is set, but in the auto.c stage we do not set that bit for it.
if(nb_cfg_54 && (!disable_siblings) && (siblings == 0)) {
//we need to check if e0 single core is there
int i;
for(i=0; i<nodes; i++) {
if(is_e0_later_in_bsp(i)) {
siblings = 1;
break;
}
}
}
#endif
//contruct apicid_base
if((!disable_siblings) && (siblings>0) ) {
/* for 8 way dual core, we will used up apicid 16:16, actualy 16 is not allowed by current kernel
and the kernel will try to get one that is small than 16 to make io apic work.
I don't know when the kernel can support 256 apic id. (APIC_EXT_ID is enabled) */
//4:10 for two way 8:12 for four way 16:16 for eight way
//Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes for better consistency?
apicid_base = nb_cfg_54 ? (siblings+1) * nodes : 8 * siblings + nodes;
}
else {
apicid_base = nodes;
}
if((apicid_base+ioapic_num-1)>0xf) {
// We need to enable APIC EXT ID
printk_info("if the IO APIC device doesn't support 256 apic id, \r\n you need to set ENABLE_APIC_EXT_ID in auto.c so you can spare 16 id for ioapic\r\n");
enable_apic_ext_id(nodes);
}
return apicid_base;
}
#if 0
void amd_sibling_init(device_t cpu)
{
unsigned i, siblings;
struct cpuid_result result;
unsigned nb_cfg_54;
struct node_core_id id;
/* On the bootstrap processor see if I want sibling cpus enabled */
if (first_time) {
first_time = 0;
get_option(&disable_siblings, "dual_core");
}
result = cpuid(0x80000008);
/* See how many sibling cpus we have */
/* Is dualcore supported */
siblings = (result.ecx & 0xff);
if ( siblings < 1) {
return;
}
#if 1
printk_debug("CPU: %u %d siblings\n",
cpu->path.u.apic.apic_id,
siblings);
#endif
nb_cfg_54 = read_nb_cfg_54();
#if 1
id = get_node_core_id(nb_cfg_54); // pre e0 nb_cfg_54 can not be set
/* See if I am a sibling cpu */
//if ((cpu->path.u.apic.apic_id>>(nb_cfg_54?0:3)) & siblings ) { // siblings = 1, 3, 7, 15,....
//if ( ( (cpu->path.u.apic.apic_id>>(nb_cfg_54?0:3)) % (siblings+1) ) != 0 ) {
if(id.coreid != 0) {
if (disable_siblings) {
cpu->enabled = 0;
}
return;
}
#endif
/* I am the primary cpu start up my siblings */
for(i = 1; i <= siblings; i++) {
struct device_path cpu_path;
device_t new;
/* Build the cpu device path */
cpu_path.type = DEVICE_PATH_APIC;
cpu_path.u.apic.apic_id = cpu->path.u.apic.apic_id + i * (nb_cfg_54?1:8);
/* See if I can find the cpu */
new = find_dev_path(cpu->bus, &cpu_path);
/* Allocate the new cpu device structure */
if(!new) {
new = alloc_dev(cpu->bus, &cpu_path);
new->enabled = 1;
new->initialized = 0;
}
#if 1
printk_debug("CPU: %u has sibling %u\n",
cpu->path.u.apic.apic_id,
new->path.u.apic.apic_id);
#endif
/* Start the new cpu */
if(new->enabled && !new->initialized)
start_cpu(new);
}
}
#endif

99
src/cpu/amd/dualcore/dualcore.c Normal file
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@ -0,0 +1,99 @@
/* 2004.12 yhlu add dual core support */
#ifndef SET_NB_CFG_54
#define SET_NB_CFG_54 1
#endif
#include "cpu/amd/dualcore/dualcore_id.c"
static inline unsigned get_core_num_in_bsp(unsigned nodeid)
{
return ((pci_read_config32(PCI_DEV(0, 0x18+nodeid, 3), 0xe8)>>12) & 3);
}
static inline
#if SET_NB_CFG_54 == 1
uint8_t
#else
void
#endif
set_apicid_cpuid_lo(void) {
#if SET_NB_CFG_54
//for pre_e0, even we set nb_cfg_54, but it will still be 0
//for e0 later you should use get_node_id(read_nb_cfg_54()) even for single core cpu
//get siblings via cpuid(0x80000008) ecx[7:0]
#if CONFIG_MAX_PHYSICAL_CPUS != 8
if( get_core_num_in_bsp(0) == 0) {
/*first node only has one core, pre_e0
all e0 single core installed don't need enable lo too,
So if mixing e0 single core and dual core,
don't put single core in first socket */
return 0;
}
#endif
if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { // disable dual_core
return 0;
}
// set the NB_CFG[54]=1; why the OS will be happy with that ???
msr_t msr;
msr = rdmsr(NB_CFG_MSR);
msr.hi |= (1<<(54-32)); // InitApicIdCpuIdLo
wrmsr(NB_CFG_MSR, msr);
return 1;
#endif
}
static inline void real_start_other_core(unsigned nodeid)
{
uint32_t dword;
// set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4 accesses and error logging to core0
dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44);
dword |= 1<<27; // NbMcaToMstCpuEn bit
pci_write_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44, dword);
// set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1
dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 0), 0x68);
dword |= 1<<5;
pci_write_config32(PCI_DEV(0, 0x18+nodeid, 0), 0x68, dword);
}
//it is running on core0 of every node
static inline void start_other_core(unsigned nodeid) {
if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { // disable dual_core
return;
}
if( get_core_num() >0) { // defined in dualcore_id.c
real_start_other_core(nodeid);
}
}
static inline unsigned get_nodes(void)
{
return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1;
}
//it is running on core0 of node0
static inline void start_other_cores(void) {
unsigned nodes;
unsigned nodeid;
if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { // disable dual_core
return;
}
nodes = get_nodes();
for(nodeid=0; nodeid<nodes; nodeid++) {
if( get_core_num_in_bsp(nodeid) > 0) {
real_start_other_core(nodeid);
}
}
}

45
src/cpu/amd/dualcore/dualcore_id.c Normal file
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@ -0,0 +1,45 @@
/* 2004.12 yhlu add dual core support */
#include <arch/cpu.h>
#include "cpu/amd/model_fxx/model_fxx_msr.h"
static inline unsigned int read_nb_cfg_54(void)
{
msr_t msr;
msr = rdmsr(NB_CFG_MSR);
return ( ( msr.hi >> (54-32)) & 1);
}
struct node_core_id {
unsigned nodeid;
unsigned coreid;
};
static inline struct node_core_id get_node_core_id(unsigned nb_cfg_54) {
struct node_core_id id;
// get the apicid via cpuid(1) ebx[27:24]
if( nb_cfg_54) {
// when NB_CFG[54] is set, nodid = ebx[27:25], coreid = ebx[24]
id.coreid = (cpuid_ebx(1) >> 24) & 0xf;
id.nodeid = (id.coreid>>1);
id.coreid &= 1;
}
else
{
// when NB_CFG[54] is clear, nodeid = ebx[26:24], coreid = ebx[27]
id.nodeid = (cpuid_ebx(1) >> 24) & 0xf;
id.coreid = (id.nodeid>>3);
id.nodeid &= 7;
}
return id;
}
static inline unsigned get_core_num(void)
{
return (cpuid_ecx(0x80000008) & 0xff);
}
static inline struct node_core_id get_node_core_id_x(void) {
return get_node_core_id( read_nb_cfg_54() );
}

1
src/cpu/amd/model_fxx/Config.lb
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@ -10,5 +10,6 @@ dir /cpu/x86/lapic
dir /cpu/x86/cache
dir /cpu/x86/pae
dir /cpu/amd/mtrr
dir /cpu/amd/dualcore
driver model_fxx_init.o
object apic_timer.o

143
src/cpu/amd/model_fxx/model_fxx_init.c
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@ -1,4 +1,9 @@
/* Needed so the AMD K8 runs correctly. */
/* this should be done by Eric
* 2004.11 yhlu add d0 e0 support
* 2004.12 yhlu add dual core support
* 2005.02 yhlu add e0 memory hole support
*/
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
@ -16,6 +21,11 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/mem.h>
#if CONFIG_LOGICAL_CPUS==1
#include <cpu/amd/dualcore.h>
#endif
#include "model_fxx_msr.h"
#define MCI_STATUS 0x401
@ -139,16 +149,18 @@ static void set_init_ecc_mtrrs(void)
enable_cache();
}
static void init_ecc_memory(unsigned node_id)
{
unsigned long startk, begink, endk;
#if K8_E0_MEM_HOLE_SIZEK != 0
unsigned long hole_startk = 0, hole_endk = 0;
#endif
unsigned long basek;
struct mtrr_state mtrr_state;
device_t f1_dev, f2_dev, f3_dev;
int enable_scrubbing;
uint32_t dcl;
f1_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 1));
if (!f1_dev) {
die("Cannot find cpu function 1\n");
@ -186,6 +198,19 @@ static void init_ecc_memory(unsigned node_id)
startk = (pci_read_config32(f1_dev, 0x40 + (node_id*8)) & 0xffff0000) >> 2;
endk = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000;
#if K8_E0_MEM_HOLE_SIZEK != 0
if (!is_cpu_pre_e0()) {
uint32_t val;
val = pci_read_config32(f1_dev, 0xf0);
if((val & 1)==1) {
hole_startk = ((val & (0xff<<24)) >> 10);
hole_endk = ((val & (0xff<<8))<<(16-10)) - startk;
hole_endk += hole_startk;
}
}
#endif
/* Don't start too early */
begink = startk;
if (begink < CONFIG_LB_MEM_TOPK) {
@ -206,6 +231,9 @@ static void init_ecc_memory(unsigned node_id)
unsigned long size;
void *addr;
#if K8_E0_MEM_HOLE_SIZEK != 0
if ((basek >= hole_startk) && (basek < hole_endk)) continue;
#endif
/* Report every 64M */
if ((basek % (64*1024)) == 0) {
/* Restore the normal state */
@ -220,6 +248,7 @@ static void init_ecc_memory(unsigned node_id)
set_init_ecc_mtrrs();
disable_lapic();
}
limitk = (basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1);
if (limitk > endk) {
limitk = endk;
@ -280,7 +309,8 @@ static inline void k8_errata(void)
msr = rdmsr(NB_CFG_MSR);
msr.lo |= 1 << 3;
if (!is_cpu_pre_c0()) {
if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
/* D0 later don't need it */
/* Erratum 86 Disable data masking on C0 and
* later processor revs.
* FIXME this is only needed if ECC is enabled.
@ -289,31 +319,57 @@ static inline void k8_errata(void)
}
wrmsr(NB_CFG_MSR, msr);
}
/* Erratum 97 ... */
if (!is_cpu_pre_c0()) {
// AMD_D0_SUPPORT
if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
/* D0 later don't need it */
/* Erratum 97 ... */
msr = rdmsr_amd(DC_CFG_MSR);
msr.lo |= 1 << 3;
wrmsr_amd(DC_CFG_MSR, msr);
}
/* Erratum 94 ... */
msr = rdmsr_amd(IC_CFG_MSR);
msr.lo |= 1 << 11;
wrmsr_amd(IC_CFG_MSR, msr);
}
//AMD_D0_SUPPORT
if(is_cpu_pre_d0()) {
/*D0 later don't need it */
/* Erratum 94 ... */
msr = rdmsr_amd(IC_CFG_MSR);
msr.lo |= 1 << 11;
wrmsr_amd(IC_CFG_MSR, msr);
}
/* Erratum 91 prefetch miss is handled in the kernel */
//AMD_D0_SUPPORT
if(is_cpu_d0()) {
/* Erratum 110 ...*/
msr = rdmsr_amd(CPU_ID_HYPER_EXT_FEATURES);
msr.hi |=1;
wrmsr_amd(CPU_ID_HYPER_EXT_FEATURES, msr);
}
//AMD_E0_SUPPORT
if(!is_cpu_pre_e0()) {
/* Erratum 110 ...*/
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
msr.hi |=1;
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
}
void model_fxx_init(device_t dev)
{
unsigned long mmio_basek, tomk;
unsigned long i;
msr_t msr;
#if CONFIG_LOGICAL_CPUS==1
struct node_core_id id;
unsigned siblings;
id.coreid=0;
#else
unsigned nodeid;
#endif
/* Turn on caching if we haven't already */
x86_enable_cache();
x86_enable_cache();
amd_setup_mtrrs();
x86_mtrr_check();
@ -330,14 +386,45 @@ void model_fxx_init(device_t dev)
enable_cache();
#if CONFIG_LOGICAL_CPUS==1
//AMD_DUAL_CORE_SUPPORT
siblings = cpuid_ecx(0x80000008) & 0xff;
// id = get_node_core_id((!is_cpu_pre_e0())? read_nb_cfg_54():0);
id = get_node_core_id(read_nb_cfg_54()); // pre e0 nb_cfg_54 can not be set
if(siblings>0) {
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
msr.lo |= 1 << 28;
wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
msr = rdmsr_amd(LOGICAL_CPUS_NUM_MSR);
msr.lo = (siblings+1)<<16;
wrmsr_amd(LOGICAL_CPUS_NUM_MSR, msr);
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
msr.hi |= 1<<(33-32);
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
/* Is this a bad location? In particular can another node prefecth
* data from this node before we have initialized it?
*/
nodeid = lapicid() & 0xf;
if(id.coreid == 0) init_ecc_memory(id.nodeid); // only do it for core0
#else
/* For now there is a 1-1 mapping between node_id and cpu_id */
nodeid = lapicid() & 0x7;
init_ecc_memory(nodeid);
#endif
/* Enable the local cpu apics */
setup_lapic();
#if CONFIG_LOGICAL_CPUS==1
//AMD_DUAL_CORE_SUPPORT
/* Start up my cpu siblings */
// if(id.coreid==0) amd_sibling_init(dev); // Don't need core1 is already be put in the CPU BUS in bus_cpu_scan
#endif
}
static struct device_operations cpu_dev_ops = {
@ -357,7 +444,31 @@ static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0xff0 },
{ X86_VENDOR_AMD, 0xf82 }, /* CH7-CG */
{ X86_VENDOR_AMD, 0xfb2 },
//AMD_D0_SUPPORT
{ X86_VENDOR_AMD, 0x10f50 }, /* SH7-D0 */
{ X86_VENDOR_AMD, 0x10f40 },
{ X86_VENDOR_AMD, 0x10f70 },
{ X86_VENDOR_AMD, 0x10fc0 }, /* DH7-D0 */
{ X86_VENDOR_AMD, 0x10ff0 },
{ X86_VENDOR_AMD, 0x10f80 }, /* CH7-D0 */
{ X86_VENDOR_AMD, 0x10fb0 },
//AMD_E0_SUPPORT
{ X86_VENDOR_AMD, 0x20f50 }, /* SH7-E0*/
{ X86_VENDOR_AMD, 0x20f40 },
{ X86_VENDOR_AMD, 0x20f70 },
{ X86_VENDOR_AMD, 0x20fc0 }, /* DH7-E0 */ /* DH-E3 */
{ X86_VENDOR_AMD, 0x20ff0 },
{ X86_VENDOR_AMD, 0x20f10 }, /* JH7-E0 */
{ X86_VENDOR_AMD, 0x20f30 },
{ X86_VENDOR_AMD, 0x20f51 }, /* SH-E4 */
{ X86_VENDOR_AMD, 0x20f71 },
{ X86_VENDOR_AMD, 0x20f42 }, /* SH-E5 */
{ X86_VENDOR_AMD, 0x20ff2 }, /* DH-E6 */
{ X86_VENDOR_AMD, 0x20fc2 },
{ X86_VENDOR_AMD, 0x20f12 }, /* JH-E6 */
{ X86_VENDOR_AMD, 0x20f32 },
#endif
{ 0, 0 },
};
static struct cpu_driver model_fxx __cpu_driver = {

10
src/cpu/amd/model_fxx/model_fxx_msr.h
View File

@ -7,4 +7,14 @@
#define DC_CFG_MSR 0xC0011022
#define BU_CFG_MSR 0xC0011023
#define CPU_ID_FEATURES_MSR 0xc0011004
/* D0 only */
#define CPU_ID_HYPER_EXT_FEATURES 0xc001100d
/* E0 only */
#define LOGICAL_CPUS_NUM_MSR 0xc001100d
#define CPU_ID_EXT_FEATURES_MSR 0xc0011005
#endif /* CPU_AMD_MODEL_FXX_MSR_H */

12
src/cpu/amd/model_fxx/node_id.c Normal file
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@ -0,0 +1,12 @@
/* 2004.12 yhlu add dual core support */
#include <arch/cpu.h>
#include "cpu/amd/model_fxx/model_fxx_msr.h"
static inline unsigned get_node_id(void) {
unsigned nodeid;
// get the apicid via cpuid(1) ebx[27:24]
nodeid = (cpuid_ebx(1) >> 24) & 0x7;
return nodeid;
}

2
src/cpu/x86/16bit/reset16.lds
View File

@ -5,7 +5,7 @@
SECTIONS {
/* Trigger an error if I have an unuseable start address */
_ROMTOP = (_start >= 0xffff0000) ? 0xfffffff0 : 0xffffffff8;
_ROMTOP = (_start >= 0xffff0000) ? 0xfffffff0 : 0xfffffff8;
. = _ROMTOP;
.reset . : {
*(.reset)

13
src/cpu/x86/lapic/lapic_cpu_init.c
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@ -11,6 +11,7 @@
#if CONFIG_SMP == 1
/* This is a lot more paranoid now, since Linux can NOT handle
* being told there is a CPU when none exists. So any errors
* will return 0, meaning no CPU.
@ -229,12 +230,16 @@ int start_cpu(device_t cpu)
void secondary_cpu_init(void)
{
atomic_inc(&active_cpus);
#if CONFIG_MAX_CPUS>2
#if SERIAL_CPU_INIT == 1
#if CONFIG_MAX_CPUS>2
spin_lock(&start_cpu_lock);
#endif
#endif
cpu_initialize();
#if CONFIG_MAX_CPUS>2
#if SERIAL_CPU_INIT == 1
#if CONFIG_MAX_CPUS>2
spin_unlock(&start_cpu_lock);
#endif
#endif
atomic_dec(&active_cpus);
stop_this_cpu();
@ -260,8 +265,10 @@ static void initialize_other_cpus(struct bus *cpu_bus)
printk_err("CPU %u would not start!\n",
cpu->path.u.apic.apic_id);
}
#if CONFIG_MAX_CPUS>2
#if SERIAL_CPU_INIT == 1
#if CONFIG_MAX_CPUS>2
udelay(10);
#endif
#endif
}

4
src/cpu/x86/mtrr/mtrr.c
View File

@ -236,8 +236,8 @@ static unsigned int range_to_mtrr(unsigned int reg,
sizek = 1 << align;
printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\n",
reg, range_startk >>10, sizek >> 10,
(type==MTRR_TYPE_UNCACHEABLE)?"NC":
((type==MTRR_TYPE_WRBACK)?"WB":"Other")
(type==MTRR_TYPE_UNCACHEABLE) ? "NC" :
((type==MTRR_TYPE_WRBACK) ? "WB" : "Other")
);
set_var_mtrr(reg++, range_startk, sizek, type);
range_startk += sizek;