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Add directive __SIMPLE_DEVICE__

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The tests for __PRE_RAM__ or __SMM__ were repeatedly used
for detection if dev->ops in the devicetree are not available
and simple device model functions need be used.

If a source file build for ramstage had __PRE_RAM__ inserted
at the beginning, the struct device would no longer match the
allocation the object had taken. This problem is fixed by
replacing such cases with explicit __SIMPLE_DEVICE__.

Change-Id: Ib74c9b2d8753e6e37e1a23fcfaa2f3657790d4c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3555
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Kyösti Mälkki
2013-06-25 23:17:43 +03:00
parent 0aede1185b
commit ef84401149
21 changed files with 138 additions and 57 deletions
Download Patch File Download Diff File Expand all files Collapse all files

34
src/arch/armv7/include/arch/rules.h Normal file
View File

@@ -0,0 +1,34 @@
/*
* This file is part of the coreboot project.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _ARCH_RULES_H
#define _ARCH_RULES_H
/* For romstage and ramstage always build with simple device model, ie.
* PCI, PNP and CPU functions operate without use of devicetree.
*
* For ramstage individual source file may define __SIMPLE_DEVICE__
* before including any header files to force that particular source
* be built with simple device model.
*/
#if defined(__PRE_RAM__)
#define __SIMPLE_DEVICE__
#endif
#endif /* _ARCH_RULES_H */

12
src/arch/x86/include/arch/cpu.h
View File

@@ -2,6 +2,7 @@
#define ARCH_CPU_H
#include <stdint.h>
#include <arch/rules.h>
/*
* EFLAGS bits
@@ -141,12 +142,13 @@ static inline unsigned int cpuid_edx(unsigned int op)
#define X86_VENDOR_ANY 0xfe
#define X86_VENDOR_UNKNOWN 0xff
#if !defined(__PRE_RAM__) && !defined(__SMM__)
#include <device/device.h>
int cpu_phys_address_size(void);
int cpu_have_cpuid(void);
#ifndef __SIMPLE_DEVICE__
struct device;
struct cpu_device_id {
unsigned vendor;
unsigned device;
@@ -163,7 +165,7 @@ struct cpu_driver *find_cpu_driver(struct device *cpu);
struct thread;
struct cpu_info {
device_t cpu;
struct device *cpu;
unsigned int index;
#if CONFIG_COOP_MULTITASKING
struct thread *thread;
@@ -188,8 +190,6 @@ static inline unsigned long cpu_index(void)
ci = cpu_info();
return ci->index;
}
#else
#include <arch/io.h>
#endif
#ifndef __ROMCC__ // romcc is segfaulting in some cases

6
src/arch/x86/include/arch/io.h
View File

@@ -2,6 +2,7 @@
#define _ASM_IO_H
#include <stdint.h>
#include <arch/rules.h>
/*
* This file contains the definitions for the x86 IO instructions
@@ -188,6 +189,9 @@ static inline int log2f(int value)
return r;
}
#endif
#ifdef __SIMPLE_DEVICE__
#define PCI_ADDR(SEGBUS, DEV, FN, WHERE) ( \
(((SEGBUS) & 0xFFF) << 20) | \
@@ -325,7 +329,7 @@ static inline __attribute__((always_inline)) void pnp_set_drq(device_t dev, unsi
pnp_write_config(dev, index, drq & 0xff);
}
#endif /* __PRE_RAM__ */
#endif /* __SIMPLE_DEVICE__ */
#endif

4
src/arch/x86/include/arch/pci_ops.h
View File

@@ -1,6 +1,8 @@
#ifndef ARCH_I386_PCI_OPS_H
#define ARCH_I386_PCI_OPS_H
#ifndef __SIMPLE_DEVICE__
extern const struct pci_bus_operations pci_cf8_conf1;
#if CONFIG_MMCONF_SUPPORT
@@ -9,4 +11,6 @@ extern const struct pci_bus_operations pci_ops_mmconf;
const struct pci_bus_operations *pci_bus_default_ops(device_t dev);
#endif
#endif /* ARCH_I386_PCI_OPS_H */

34
src/arch/x86/include/arch/rules.h Normal file
View File

@@ -0,0 +1,34 @@
/*
* This file is part of the coreboot project.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _ARCH_RULES_H
#define _ARCH_RULES_H
/* For romstage and ramstage always build with simple device model, ie.
* PCI, PNP and CPU functions operate without use of devicetree.
*
* For ramstage individual source file may define __SIMPLE_DEVICE__
* before including any header files to force that particular source
* be built with simple device model.
*/
#if defined(__PRE_RAM__) || defined(__SMM__)
#define __SIMPLE_DEVICE__
#endif
#endif /* _ARCH_RULES_H */