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soc/intel/common: Add save/restore for variable MRC data

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Piggy-back on existing MRC cache infrastructure to store variable MRC data.

Only one set of data can be valid at given point of time. Currently this
magically happens because region alignment is forced to 0x1000 and region
itself is of the same size. This needs to be somehow programmatically
enforced.

Change-Id: I8a660d356ca760b8ff9907396fb9b34cb16cf1db
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/17320
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Andrey Petrov
2016-11-08 08:30:06 -08:00
committed by Aaron Durbin
parent 4ed99ad067
commit ef9a9ea3b7
5 changed files with 96 additions and 31 deletions
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2
src/commonlib/include/commonlib/cbmem_id.h
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@@ -41,6 +41,7 @@
#define CBMEM_ID_MMA_DATA 0x4D4D4144
#define CBMEM_ID_MPTABLE 0x534d5054
#define CBMEM_ID_MRCDATA 0x4d524344
#define CBMEM_ID_VAR_MRCDATA 0x4d524345
#define CBMEM_ID_MTC 0xcb31d31c
#define CBMEM_ID_NONE 0x00000000
#define CBMEM_ID_PIRQ 0x49525154
@@ -92,6 +93,7 @@
{ CBMEM_ID_MMA_DATA, "MMA DATA " }, \
{ CBMEM_ID_MPTABLE, "SMP TABLE " }, \
{ CBMEM_ID_MRCDATA, "MRC DATA " }, \
{ CBMEM_ID_VAR_MRCDATA, "VARMRC DATA" }, \
{ CBMEM_ID_MTC, "MTC " }, \
{ CBMEM_ID_PIRQ, "IRQ TABLE " }, \
{ CBMEM_ID_POWER_STATE, "POWER STATE" }, \