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soc/intel/skylake: Move PCR DMI programming into bootblock

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As per PCH BWG 2.5.16, set up LPC IO Enables PCR[DMI] + 2774h bit
[15:0] to the same value program in LPC PCI offset 82h. Also this
cycle decoding is only allowed to set when SRLOCK is not set.

Hence move the required programming from lpc.c to pch.c.

Also only enable COM port ranges if CONFIG_DRIVERS_UART_8250IO
Kconfig is selected.

Change-Id: Ie706735492a450baa653d8a8bb74c6e42f5150b8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Subrata Banik
2018-02-26 14:49:00 +05:30
committed by Martin Roth
parent d83faceefa
commit efbfdd2d60
2 changed files with 30 additions and 9 deletions
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6
src/soc/intel/skylake/lpc.c
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@@ -82,17 +82,11 @@ void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec)
void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
{
uint16_t lpc_en;
/* Mirror these same settings in DMI PCR */
pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
/* LPC IO Decode Enable */
lpc_en = pci_read_config16(PCH_DEV_LPC, LPC_IO_ENABLES);
pcr_write16(PID_DMI, PCR_DMI_LPCIOE, lpc_en);
}
static const struct reg_script pch_misc_init_script[] = {