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soc/intel/tigerlake: Expose UPD to disable Precision Time Measurement

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Expose a config option that allows disabling the FSP UPD which controls
Precision Time Measurement for a particular PCIe root port.  Since this
is enabled by default the option is inverted to allow disabling for
a particular port while not affecting others.

BUG=b:160996445
TEST=boot on volteer with PTM disabled for the NVMe root port

Change-Id: Icb51b256eb581d942b2d30fcabfae52fa90e48d4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
This commit is contained in:
Duncan Laurie
2020-10-27 17:57:13 -07:00
committed by Jeremy Soller
parent 417fa84913
commit efd716cef0
2 changed files with 4 additions and 0 deletions
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3
src/soc/intel/tigerlake/chip.h
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@@ -243,6 +243,9 @@ struct soc_intel_tigerlake_config {
/* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
/* Disable PCIe Precision Time Measurement for Root Ports (enabled by default) */
uint8_t PciePtmDisable[CONFIG_MAX_ROOT_PORTS];
/* PCIe RP L1 substate */ /* PCIe RP L1 substate */
enum L1_substates_control { enum L1_substates_control {
L1_SS_FSP_DEFAULT, L1_SS_FSP_DEFAULT,

1
src/soc/intel/tigerlake/fsp_params.c
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@@ -187,6 +187,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PcieRpAdvancedErrorReporting[i] = params->PcieRpAdvancedErrorReporting[i] =
config->PcieRpAdvancedErrorReporting[i]; config->PcieRpAdvancedErrorReporting[i];
params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i]; params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i];
params->PciePtm[i] = !config->PciePtmDisable[i];
} }
/* Enable ClkReqDetect for enabled port */ /* Enable ClkReqDetect for enabled port */