soc/intel/tigerlake: Expose UPD to disable Precision Time Measurement

Expose a config option that allows disabling the FSP UPD which controls
Precision Time Measurement for a particular PCIe root port.  Since this
is enabled by default the option is inverted to allow disabling for
a particular port while not affecting others.

BUG=b:160996445
TEST=boot on volteer with PTM disabled for the NVMe root port

Change-Id: Icb51b256eb581d942b2d30fcabfae52fa90e48d4
Signed-off-by: Duncan Laurie <dlaurie@google.com>

src/soc/intel/tigerlake/chip.h

@@ -243,6 +243,9 @@ struct soc_intel_tigerlake_config {
 	/* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
 	uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
 
+	/* Disable PCIe Precision Time Measurement for Root Ports (enabled by default) */
+	uint8_t PciePtmDisable[CONFIG_MAX_ROOT_PORTS];
+
 	/* PCIe RP L1 substate */
 	enum L1_substates_control {
 		L1_SS_FSP_DEFAULT,

src/soc/intel/tigerlake/fsp_params.c

@@ -187,6 +187,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 		params->PcieRpAdvancedErrorReporting[i] =
 			config->PcieRpAdvancedErrorReporting[i];
 		params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i];
+		params->PciePtm[i] = !config->PciePtmDisable[i];
 	}
 
 	/* Enable ClkReqDetect for enabled port */