From efe04c82e0e8937d1adc866836619f6c83a33d14 Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Wed, 12 Aug 2020 11:27:04 -0600 Subject: [PATCH] mb/system76: Fix left USB3 port on gaze14/gaze15 The USB table in the manuals incorrectly list the USB3 port as 5. The labeled pins show it correctly as port 2. Change-Id: I9a6a96af847ca66ad667738d83cfca7c3166956a --- src/mainboard/system76/gaze14/devicetree.cb | 8 ++++---- src/mainboard/system76/gaze15/devicetree.cb | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/mainboard/system76/gaze14/devicetree.cb b/src/mainboard/system76/gaze14/devicetree.cb index c50577707e..25f38e8b3b 100644 --- a/src/mainboard/system76/gaze14/devicetree.cb +++ b/src/mainboard/system76/gaze14/devicetree.cb @@ -99,10 +99,10 @@ chip soc/intel/cannonlake # USB2 register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Right - register "usb2_ports[1]" = "USB2_PORT_EMPTY" + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Left register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C register "usb2_ports[3]" = "USB2_PORT_EMPTY" - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Left + register "usb2_ports[4]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2 Left register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # 3G/LTE register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera @@ -117,10 +117,10 @@ chip soc/intel/cannonlake # USB3 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Right - register "usb3_ports[1]" = "USB3_PORT_EMPTY" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Left register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Left + register "usb3_ports[4]" = "USB3_PORT_EMPTY" register "usb3_ports[5]" = "USB3_PORT_EMPTY" register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 3G/LTE register "usb3_ports[7]" = "USB3_PORT_EMPTY" diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index c50577707e..25f38e8b3b 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -99,10 +99,10 @@ chip soc/intel/cannonlake # USB2 register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Right - register "usb2_ports[1]" = "USB2_PORT_EMPTY" + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Left register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C register "usb2_ports[3]" = "USB2_PORT_EMPTY" - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Left + register "usb2_ports[4]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2 Left register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # 3G/LTE register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera @@ -117,10 +117,10 @@ chip soc/intel/cannonlake # USB3 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Right - register "usb3_ports[1]" = "USB3_PORT_EMPTY" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Left register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Left + register "usb3_ports[4]" = "USB3_PORT_EMPTY" register "usb3_ports[5]" = "USB3_PORT_EMPTY" register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 3G/LTE register "usb3_ports[7]" = "USB3_PORT_EMPTY"