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soc/intel/alderlake: Implement PMC static function lock

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This patch performs PMC static function lockdown.

BUG=b:211954778
TEST=Able to build and boot google/redrix to OS. Verified PMC static PG
lock (bit 31) is set.

> iotools mmio_read32 0xfe001e20
0x80000000

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I68343f9af4f34aceae06293c5f87c5eaa3430a60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Subrata Banik
2022-04-18 12:25:13 +05:30
committed by Felix Held
parent a56642e981
commit f021952c40
2 changed files with 6 additions and 0 deletions
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3
src/soc/intel/alderlake/include/soc/pmc.h
View File

@@ -142,6 +142,9 @@ extern struct device_operations pmc_ops;
#define ACPI_EN (1 << 7) #define ACPI_EN (1 << 7)
#define SCI_IRQ_SEL (7 << 0) #define SCI_IRQ_SEL (7 << 0)
#define ST_PG_FDIS1 0x1e20
#define ST_FDIS_LOCK (1 << 31)
#define SCIS_IRQ9 0 #define SCIS_IRQ9 0
#define SCIS_IRQ10 1 #define SCIS_IRQ10 1
#define SCIS_IRQ11 2 #define SCIS_IRQ11 2

3
src/soc/intel/alderlake/lockdown.c
View File

@@ -23,6 +23,9 @@ static void pmc_lockdown_cfg(int chipset_lockdown)
if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT)
setbits32(pmcbase + GEN_PMCON_B, SMI_LOCK); setbits32(pmcbase + GEN_PMCON_B, SMI_LOCK);
if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM))
setbits32(pmcbase + ST_PG_FDIS1, ST_FDIS_LOCK);
} }
void soc_lockdown_config(int chipset_lockdown) void soc_lockdown_config(int chipset_lockdown)