intel/smm/gen1: Rename header file

Change-Id: I258fccc5e1db0bedb641c8af8cb9727954d4d7c1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/northbridge/intel/gm45/memmap.c

@@ -27,7 +27,7 @@
 #include <cbmem.h>
 #include <program_loading.h>
 #include <stage_cache.h>
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 #include "gm45.h"
 
 /*

src/northbridge/intel/gm45/northbridge.c

@@ -23,7 +23,7 @@
 #include <cpu/cpu.h>
 #include <boot/tables.h>
 #include <arch/acpi.h>
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 
 #include "chip.h"
 #include "gm45.h"

src/northbridge/intel/i945/memmap.c

@@ -24,7 +24,7 @@
 #include <cpu/intel/romstage.h>
 #include <cpu/x86/mtrr.h>
 #include <program_loading.h>
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 #include <stdint.h>
 #include <stage_cache.h>
 

src/northbridge/intel/i945/northbridge.c

@@ -23,7 +23,7 @@
 #include <stdlib.h>
 #include <cpu/cpu.h>
 #include <arch/acpi.h>
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 #include "i945.h"
 
 static int get_pcie_bar(u32 *base)

src/northbridge/intel/nehalem/memmap.c

@@ -24,7 +24,7 @@
 #include <cpu/x86/mtrr.h>
 #include <program_loading.h>
 #include <stage_cache.h>
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 #include "nehalem.h"
 
 static uintptr_t smm_region_start(void)

src/northbridge/intel/nehalem/northbridge.c

@@ -29,7 +29,7 @@
 #include <cpu/cpu.h>
 #include "chip.h"
 #include "nehalem.h"
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 
 static int bridge_revision_id = -1;
 

src/northbridge/intel/nehalem/smi.c

@@ -19,7 +19,7 @@
 #include <device/pci_ops.h>
 #include "nehalem.h"
 
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 
 void northbridge_write_smram(u8 smram)
 {

src/northbridge/intel/pineview/memmap.c

@@ -25,7 +25,7 @@
 #include <northbridge/intel/pineview/pineview.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/intel/romstage.h>
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 #include <stdint.h>
 #include <stage_cache.h>
 

src/northbridge/intel/pineview/northbridge.c

@@ -25,7 +25,7 @@
 #include <boot/tables.h>
 #include <arch/acpi.h>
 #include <northbridge/intel/pineview/pineview.h>
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 
 /* Reserve everything between A segment and 1MB:
  *

src/northbridge/intel/sandybridge/memmap.c

@@ -20,7 +20,7 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <cpu/intel/romstage.h>
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 #include <cpu/x86/mtrr.h>
 #include <program_loading.h>
 #include <stage_cache.h>

src/northbridge/intel/sandybridge/northbridge.c

@@ -28,7 +28,7 @@
 #include <cpu/cpu.h>
 #include "chip.h"
 #include "sandybridge.h"
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 
 static int bridge_revision_id = -1;
 

src/northbridge/intel/x4x/memmap.c

@@ -28,7 +28,7 @@
 #include <cpu/x86/mtrr.h>
 #include <northbridge/intel/x4x/x4x.h>
 #include <program_loading.h>
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 #include <stage_cache.h>
 
 /** Decodes used Graphics Mode Select (GMS) to kilobytes. */

src/northbridge/intel/x4x/northbridge.c

@@ -27,7 +27,7 @@
 #include <northbridge/intel/x4x/iomap.h>
 #include <northbridge/intel/x4x/chip.h>
 #include <northbridge/intel/x4x/x4x.h>
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 
 static const int legacy_hole_base_k = 0xa0000 / 1024;