sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/amd/common: Refactor and consolidate code for spi base

Browse Source 
Previously, the spi base address code was using a number of different
functions in a way that didn't work for use on the PSP.

This patch consolidates all of that to a single saved value that gets
the LPC SPI base address by default on X86, and allows the PSP to set
it to a different value.

BUG=b:159811539
TEST=Build with following patch to set the SPI speed in psp_verstage.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I50d9de269bcb88fbf510056a6216e22a050cae6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43307
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Martin Roth
2020-07-06 23:35:40 -06:00
committed by Patrick Georgi
parent 5a1e2d3f63
commit f09b4b6bee
4 changed files with 40 additions and 41 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
src/soc/amd/stoneyridge/southbridge.c
View File

@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/spi.h>
#include <console/console.h>
#include <device/mmio.h>
#include <bootstate.h>
@ -256,25 +257,17 @@ void sb_clk_output_48Mhz(u32 osc)
misc_write32(MISC_CLK_CNTL1, ctrl);
}
static uintptr_t sb_init_spi_base(void)
static void sb_init_spi_base(void)
{
uintptr_t base;
/* Make sure the base address is predictable */
base = lpc_get_spibase();
if (base)
return base;
lpc_set_spibase(SPI_BASE_ADDRESS);
if (ENV_X86)
lpc_set_spibase(SPI_BASE_ADDRESS);
lpc_enable_spi_rom(SPI_ROM_ENABLE);
return SPI_BASE_ADDRESS;
}
void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm)
{
uintptr_t base = sb_init_spi_base();
uintptr_t base = spi_get_bar();
write16((void *)(base + SPI100_SPEED_CONFIG),
(norm << SPI_NORM_SPEED_NEW_SH) |
(fast << SPI_FAST_SPEED_NEW_SH) |
@ -285,7 +278,7 @@ void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm)
void sb_disable_4dw_burst(void)
{
uintptr_t base = sb_init_spi_base();
uintptr_t base = spi_get_bar();
write16((void *)(base + SPI100_HOST_PREF_CONFIG),
read16((void *)(base + SPI100_HOST_PREF_CONFIG))
& ~SPI_RD4DW_EN_HOST);
@ -293,7 +286,7 @@ void sb_disable_4dw_burst(void)
void sb_read_mode(u32 mode)
{
uintptr_t base = sb_init_spi_base();
uintptr_t base = spi_get_bar();
write32((void *)(base + SPI_CNTRL0),
(read32((void *)(base + SPI_CNTRL0))
& ~SPI_READ_MODE_MASK) | mode);