From f0d5188cf57c9d8fbca91e999c0f37b62d5dbb65 Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Mon, 26 Sep 2022 14:13:09 -0700 Subject: [PATCH] mb/google/brya/variant/brya0: Add power limits for RPL SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the RPL CPU power limits to brya0's power limit table to support both the brya0 ADL sku and the new RPL sku. BUG=b:248126749 TEST="emerge-brya coreboot chromeos-bootimage", flash skolas with image-brya0.serial.bin and verify skolas boots successfully to kernel. Change-Id: I2ac067f98f1ff8f86cff0ed0e15010f454d9c91c Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/67880 Tested-by: build bot (Jenkins) Reviewed-by: Jérémy Compostella Reviewed-by: Bora Guvendik Reviewed-by: Tarun Tuli Reviewed-by: Sumeet R Pawnikar --- src/mainboard/google/brya/variants/brya0/ramstage.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/brya/variants/brya0/ramstage.c b/src/mainboard/google/brya/variants/brya0/ramstage.c index 970c628f50..2aa9ec830a 100644 --- a/src/mainboard/google/brya/variants/brya0/ramstage.c +++ b/src/mainboard/google/brya/variants/brya0/ramstage.c @@ -11,6 +11,10 @@ const struct cpu_power_limits limits[] = { { PCI_DID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 43000, 43000, 105000 }, { PCI_DID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 43000, 43000, 105000 }, { PCI_DID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 80000, 80000, 159000 }, + /* Following values are for performance config as per document #686872 */ + { PCI_DID_INTEL_RPL_P_ID_1, 45, 18000, 45000, 115000, 115000, 210000 }, + { PCI_DID_INTEL_RPL_P_ID_2, 28, 10000, 28000, 64000, 64000, 126000 }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, 6000, 15000, 55000, 55000, 114000 }, }; void variant_devtree_update(void)