nb/intel/x4x: Add DDR3 JEDEC init

Add DDR3 JEDEC init (Power up and Initialization by setting emrs regs)

This also modifies the send_jedec_cmd function as DDR3 dimms can have
ranks mirrored which needs to be accounted for.

The ddr3_emrs1_config array is placed externally since it is also
needed for write leveling.

Change-Id: I510b8669aaa48ba99fb4dcf1ece716aef26741bb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/northbridge/intel/x4x/raminit.c

@@ -408,6 +408,9 @@ static int ddr3_save_dimminfo(u8 dimm_idx, u8 *raw_spd,
 
 	s->dimms[dimm_idx].spd_crc = spd_ddr3_calc_unique_crc(raw_spd,
 							raw_spd[0]);
+
+	s->dimms[dimm_idx].mirrored = decoded_dimm.flags.pins_mirrored;
+
 	return CB_SUCCESS;
 }