intel/fsp: Update cannonlake fsp header

Update Cannonlake FSP header to revision 7.x.25.31. Following changes
had been made:
1. Add PeciSxRest option.
2. Add Thermal Velocity Boost option.
3. Add VR power deliver design option.
4. Match MrcChannelSts.

TEST=NONE
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I32e976eacf39d2cd75f8288c86d1de1a54c194c6
Reviewed-on: https://review.coreboot.org/23677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/cannonlake/romstage/romstage.c

@@ -40,13 +40,6 @@ static struct chipset_power_state power_state CAR_GLOBAL;
 	0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23	\
 }
 
-/* Memory Channel Present Status */
-enum {
-	CHANNEL_NOT_PRESENT,
-	CHANNEL_DISABLED,
-	CHANNEL_PRESENT
-};
-
 /* Save the DIMM information for SMBIOS table 17 */
 static void save_dimm_info(void)
 {