device/pci: Fix PCI accessor headers

PCI config accessors are no longer indirectly included
from <arch/io.h> use <device/pci_ops.h> instead.

Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/southbridge/amd/agesa/hudson/bootblock.c

@@ -15,6 +15,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 
 /*
  * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.

src/southbridge/amd/agesa/hudson/early_setup.c

@@ -18,6 +18,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <arch/acpi.h>
 #include <console/console.h>
 #include <reset.h>

src/southbridge/amd/agesa/hudson/reset.c

@@ -17,6 +17,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <cf9_reset.h>
 #include <reset.h>
 

src/southbridge/amd/amd8111/amd8111.c

@@ -13,6 +13,7 @@
 
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include "amd8111.h"
 

src/southbridge/amd/amd8111/bootblock.c

@@ -16,6 +16,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include <device/pci_type.h>
 

src/southbridge/amd/amd8111/early_smbus.c

@@ -11,6 +11,7 @@
  * GNU General Public License for more details.
  */
 
+#include <device/pci_ops.h>
 #include "amd8111_smbus.h"
 
 #define SMBUS_IO_BASE 0x0f00

src/southbridge/amd/amd8111/reset.c

@@ -15,6 +15,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <reset.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>

src/southbridge/amd/cimx/sb800/bootblock.c

@@ -14,6 +14,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 
 static void enable_rom(void)
 {

src/southbridge/amd/cimx/sb800/fan.c

@@ -16,6 +16,7 @@
 #include <southbridge/amd/cimx/cimx_util.h>
 #include <device/device.h>
 #include <device/pci.h>		/* device_operations */
+#include <device/pci_ops.h>
 #include "SBPLATFORM.h"
 #include "sb_cimx.h"
 #include "chip.h"		/* struct southbridge_amd_cimx_sb800_config */

src/southbridge/amd/cimx/sb800/late.c

@@ -17,6 +17,7 @@
 
 #include <device/device.h>
 #include <device/pci.h>		/* device_operations */
+#include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include <bootstate.h>
 #include <arch/ioapic.h>

src/southbridge/amd/cimx/sb800/lpc.c

@@ -20,6 +20,7 @@
 #include <arch/ioapic.h>
 #include "lpc.h"
 #include <arch/io.h>
+#include <device/pci_ops.h>
 
 void lpc_read_resources(struct device *dev)
 {

src/southbridge/amd/cimx/sb800/reset.c

@@ -17,6 +17,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <cf9_reset.h>
 #include <reset.h>
 

src/southbridge/amd/cimx/sb900/bootblock.c

@@ -14,6 +14,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 
 static void sb900_enable_rom(void)
 {

src/southbridge/amd/cimx/sb900/lpc.c

@@ -14,6 +14,7 @@
  */
 
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include "lpc.h"
 #include <console/console.h>	/* printk */
 #include <arch/ioapic.h>

src/southbridge/amd/cimx/sb900/reset.c

@@ -17,6 +17,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <cf9_reset.h>
 #include <reset.h>
 

src/southbridge/amd/common/amd_pci_util.c

@@ -16,6 +16,7 @@
 #include <console/console.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <string.h>
 #include "amd_pci_util.h"
 #include <pc80/i8259.h>

src/southbridge/amd/pi/hudson/bootblock.c

@@ -15,6 +15,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_ids.h>
 
 /*

src/southbridge/amd/pi/hudson/early_setup.c

@@ -19,6 +19,7 @@
 #include <assert.h>
 #include <stdint.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <arch/acpi.h>
 #include <console/console.h>
 #include <reset.h>

src/southbridge/amd/pi/hudson/imc.c

@@ -17,6 +17,7 @@
 
 #include "imc.h"
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/device.h>
 #include <delay.h>
 #include <Porting.h>

src/southbridge/amd/pi/hudson/reset.c

@@ -17,6 +17,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <cf9_reset.h>
 #include <reset.h>
 

src/southbridge/amd/rs780/early_setup.c

@@ -15,6 +15,7 @@
 
 #include <types.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <northbridge/amd/amdmct/mct/mct_d.h>
 #include <console/console.h>
 #include <cpu/x86/msr.h>

src/southbridge/amd/sb700/bootblock.c

@@ -16,6 +16,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 
 #define IO_MEM_PORT_DECODE_ENABLE_5	0x48
 #define IO_MEM_PORT_DECODE_ENABLE_6	0x4a

src/southbridge/amd/sb700/early_setup.c

@@ -20,6 +20,7 @@
 #include <stdint.h>
 #include <option.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <console/console.h>
 #include <cpu/x86/msr.h>
 #include <device/pci.h>

src/southbridge/amd/sb700/reset.c

@@ -17,6 +17,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <reset.h>
 #include <southbridge/amd/common/reset.h>
 

src/southbridge/amd/sb700/sb700.h

@@ -73,6 +73,7 @@ void sb7xx_51xx_before_pci_init(void);
 uint16_t sb7xx_51xx_decode_last_reset(void);
 #else
 #include <device/pci.h>
+#include <device/pci_ops.h>
 /* allow override in mainboard.c */
 void sb7xx_51xx_setup_sata_phys(struct device *dev);
 void sb7xx_51xx_setup_sata_port_indication(void *sata_bar5);

src/southbridge/amd/sb800/bootblock.c

@@ -15,6 +15,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 
 /*
  * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.

src/southbridge/amd/sr5650/cmn.h

@@ -18,6 +18,7 @@
 #define __SR5650_CMN_H__
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 
 #define NBMISC_INDEX	0x60
 #define NBHTIU_INDEX	0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */

src/southbridge/amd/sr5650/early_setup.c

@@ -18,6 +18,7 @@
 #include <stdint.h>
 #include <arch/cpu.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <console/console.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/msr.h>