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CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEM

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The name was always obscure and confusing. Instead define cbmem_top()
directly in the chipset code for x86 like on ARMs.

TODO: Check TSEG alignment, it used for MTRR programming.

Change-Id: Ibbe5f05ab9c7d87d09caa673766cd17d192cd045
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7888
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Kyösti Mälkki
2014-12-22 12:28:07 +02:00
parent 91fac61240
commit f1e3c763b3
21 changed files with 131 additions and 109 deletions
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4
src/cpu/intel/haswell/romstage.c
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@@ -133,7 +133,7 @@ static void *setup_romstage_stack_after_car(void)
slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);
num_mtrrs++;
top_of_ram = get_top_of_ram();
top_of_ram = (uint32_t)cbmem_top();
/* Cache 8MiB below the top of ram. On haswell systems the top of
* ram under 4GiB is the start of the TSEG region. It is required to
* be 8MiB aligned. Set this area as cacheable so it can be used later
@@ -318,7 +318,7 @@ struct ramstage_cache *ramstage_cache_location(long *size)
/* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
* The top of ram is defined to be the TSEG base address. */
*size = RESERVED_SMM_SIZE;
return (void *)(get_top_of_ram() + RESERVED_SMM_OFFSET);
return (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET);
}
void ramstage_cache_invalid(struct ramstage_cache *cache)