CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEM
The name was always obscure and confusing. Instead define cbmem_top() directly in the chipset code for x86 like on ARMs. TODO: Check TSEG alignment, it used for MTRR programming. Change-Id: Ibbe5f05ab9c7d87d09caa673766cd17d192cd045 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7888 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
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@@ -31,7 +31,7 @@ static inline int smm_region_size(void)
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return CONFIG_SMM_TSEG_SIZE;
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}
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void *smm_region_start(void);
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uintptr_t smm_region_start(void);
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#if !defined(__PRE_RAM__) && !defined(__SMM___)
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#include <stdint.h>
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@@ -22,12 +22,12 @@
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#include <baytrail/iosf.h>
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#include <baytrail/smm.h>
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void *smm_region_start(void)
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uintptr_t smm_region_start(void)
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{
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return (void *)(iosf_bunit_read(BUNIT_SMRRL) << 20);
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return (iosf_bunit_read(BUNIT_SMRRL) << 20);
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}
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unsigned long get_top_of_ram(void)
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void *cbmem_top(void)
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{
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return (unsigned long)smm_region_start();
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return (void *) smm_region_start();
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}
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@@ -23,19 +23,24 @@
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#include <broadwell/pci_devs.h>
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#include <broadwell/systemagent.h>
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unsigned long get_top_of_ram(void)
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static uintptr_t dpr_region_start(void)
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{
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/*
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* Base of DPR is top of usable DRAM below 4GiB. The register has
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* 1 MiB alignment and reports the TOP of the range, the base
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* must be calculated from the size in MiB in bits 11:4.
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*/
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u32 dpr = pci_read_config32(SA_DEV_ROOT, DPR);
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u32 tom = dpr & ~((1 << 20) - 1);
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uintptr_t dpr = pci_read_config32(SA_DEV_ROOT, DPR);
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uintptr_t tom = dpr & ~((1 << 20) - 1);
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/* Subtract DMA Protected Range size if enabled */
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if (dpr & DPR_EPM)
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tom -= (dpr & DPR_SIZE_MASK) << 16;
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return (unsigned long)tom;
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return tom;
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}
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void *cbmem_top(void)
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{
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return (void *) dpr_region_start();
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}
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@@ -44,8 +44,6 @@ ramstage-y += ramstage.c
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ramstage-y += gpio.c
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romstage-y += gpio.c
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ramstage-y += pmutil.c
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romstage-y += raminit.c
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ramstage-y += raminit.c
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ramstage-y += southcluster.c
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romstage-y += reset.c
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ramstage-y += reset.c
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@@ -36,7 +36,7 @@ static inline int smm_region_size(void)
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return CONFIG_SMM_TSEG_SIZE;
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}
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void *smm_region_start(void);
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uintptr_t smm_region_start(void);
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#if !defined(__PRE_RAM__) && !defined(__SMM___)
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#include <stdint.h>
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@@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google, Inc.
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* Copyright (C) 2014 Sage Electronic Engineering, LLC.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@@ -21,8 +22,25 @@
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#include <cbmem.h>
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#include <baytrail/iosf.h>
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#include <baytrail/smm.h>
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#include <drivers/intel/fsp/fsp_util.h>
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void *smm_region_start(void)
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uintptr_t smm_region_start(void)
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{
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return (void *)(iosf_bunit_read(BUNIT_SMRRL) << 20);
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return (iosf_bunit_read(BUNIT_SMRRL) << 20);
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}
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/*
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* Calculate the top of usable (low) DRAM.
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* The FSP's reserved memory sits just below the SMM region,
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* allowing calculation of the top of usable memory.
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*
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* The entire memory map is shown in northcluster.c
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*/
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void *cbmem_top(void)
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{
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uintptr_t tom = smm_region_start();
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if (!tom)
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tom = iosf_bunit_read(BUNIT_BMBOUND);
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return (void *) tom - FSP_RESERVE_MEMORY_SIZE;
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}
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@@ -1,47 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Google Inc.
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* Copyright (C) 2014 Sage Electronic Engineering, LLC.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <arch/io.h>
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#include <cbmem.h>
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#include <device/device.h>
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#include <baytrail/baytrail.h>
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#include <baytrail/iosf.h>
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#include <cpu/x86/msr.h>
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#include <drivers/intel/fsp/fsp_util.h>
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unsigned long get_top_of_ram(void)
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{
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/*
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* Calculate the top of usable (low) DRAM.
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* The FSP's reserved memory sits just below the SMM region,
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* allowing calculation of the top of usable memory.
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*
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* The entire memory map is shown in northcluster.c
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*/
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u32 tom = iosf_bunit_read(BUNIT_BMBOUND);
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u32 bsmmrrl = iosf_bunit_read(BUNIT_SMRRL) << 20;
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if (bsmmrrl) {
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tom = bsmmrrl;
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}
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tom -= FSP_RESERVE_MEMORY_SIZE;
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return (unsigned long) tom;
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}
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