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nb/intel/i945: Use parallel MP init

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Use the parallel mp init path to initialize AP's. This should result
in a moderate speedup.

Tested on Intel D945GCLF (1 core 2 threads), still boots fine and is
26ms faster compared to lapic_cpu_init.

This removes the option to disable HT siblings.

Change-Id: I955551b99e9cbc397f99c2a6bd355c6070390bcb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
This commit is contained in:
Arthur Heymans
2018-04-10 15:15:05 +02:00
committed by Patrick Georgi
parent 6336d4c48d
commit f266932836
29 changed files with 22 additions and 61 deletions
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1
src/cpu/intel/model_f4x/Makefile.inc
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@@ -1,4 +1,5 @@
ramstage-y += model_f4x_init.c
subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin

5
src/cpu/intel/model_f4x/model_f4x_init.c
View File

@@ -24,7 +24,7 @@ static void model_f4x_init(struct device *cpu)
/* Turn on caching if we haven't already */
x86_enable_cache();
if (!intel_ht_sibling()) {
if (!IS_ENABLED(CONFIG_PARALLEL_MP) && !intel_ht_sibling()) {
/* MTRRs are shared between threads */
x86_setup_mtrrs();
x86_mtrr_check();
@@ -37,7 +37,8 @@ static void model_f4x_init(struct device *cpu)
setup_lapic();
/* Start up my CPU siblings */
intel_sibling_init(cpu);
if (!IS_ENABLED(CONFIG_PARALLEL_MP))
intel_sibling_init(cpu);
};
static struct device_operations cpu_dev_ops = {