soc/intel/quark: Add FSP 2.0 romstage support

Add the pieces necessary to successfully build and run romstage using
the FSP 2.0 build.  Because romstage is using postcar, add the postcar
pieces so that romstage can attempt to load postcar.

TEST=Build and run on Galileo Gen2

Change-Id: I66b3437e3c7840223535f6ab643599c9e4924968
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15866
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/soc/intel/quark/Kconfig

@@ -135,6 +135,13 @@ config DCACHE_RAM_SIZE
 	default 0x8000 if PLATFORM_USES_FSP1_1
 	default 0x40000
 
+config DISPLAY_ESRAM_LAYOUT
+	bool "Display ESRAM layout"
+	default n
+	depends on PLATFORM_USES_FSP2_0
+	help
+	  Select this option to display coreboot's use of ESRAM.
+
 #####
 # Flash layout
 #     Specify the size of the coreboot file system in the read-only
@@ -196,8 +203,8 @@ config FSP_LOC
 
 config FSP_ESRAM_LOC
 	hex
-	default 0x80000000
-	depends on PLATFORM_USES_FSP1_1
+	default 0x80000000 if PLATFORM_USES_FSP1_1
+	default 0x80040000
 	help
 	  The location in ESRAM where a copy of the FSP binary is placed.
 
@@ -208,6 +215,16 @@ config RELOCATE_FSP_INTO_DRAM
 	help
 	  Relocate the FSP binary into DRAM before the call to SiliconInit.
 
+config FSP_M_FILE
+	string
+	depends on PLATFORM_USES_FSP2_0
+	default "3rdparty/blobs/soc/intel/quark/FSP_M.fd"
+
+config FSP_S_FILE
+	string
+	depends on PLATFORM_USES_FSP2_0
+	default "3rdparty/blobs/soc/intel/quark/FSP_S.fd"
+
 #####
 # RMU binary
 #     The following options control the Quark chipset microcode file