soc/intel/quark: Add FSP 2.0 romstage support

Add the pieces necessary to successfully build and run romstage using
the FSP 2.0 build.  Because romstage is using postcar, add the postcar
pieces so that romstage can attempt to load postcar.

TEST=Build and run on Galileo Gen2

Change-Id: I66b3437e3c7840223535f6ab643599c9e4924968
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15866
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/soc/intel/quark/include/soc/pm.h

@@ -25,6 +25,10 @@ struct chipset_power_state {
 } __attribute__ ((packed));
 
 struct chipset_power_state *get_power_state(void);
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
 struct chipset_power_state *fill_power_state(void);
-
+#else
+int fill_power_state(void);
 #endif
+
+#endif /* _SOC_PM_H_ */

src/soc/intel/quark/include/soc/ramstage.h

@@ -28,5 +28,6 @@ void mainboard_gpio_i2c_init(device_t dev);
 #if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
 void fsp_silicon_init(void);
 #endif
+asmlinkage void chipset_teardown_car(void);
 
 #endif /* _SOC_RAMSTAGE_H_ */