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superio/ite/*: Factor out generic romstage component

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Following the reasoning of:
cf7b498 superio/fintek/*: Factor out generic romstage component

Change-Id: I4c0a9a5a7786eb8fcb0c3ed6251c7fe9bbbadae7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5585
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
This commit is contained in:
Edward O'Callaghan
2014-04-27 00:41:50 +10:00
committed by Rudolf Marek
parent 946bee1c34
commit f29200240e
50 changed files with 247 additions and 386 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/mainboard/amd/dbm690t/romstage.c
View File

@@ -30,7 +30,8 @@
#include "lib/delay.c"
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/ite/it8712f/early_serial.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
#include <spd.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -38,6 +39,8 @@
#include "southbridge/amd/sb600/early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -80,8 +83,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_rs690_dev8();
sb600_lpc_init();
/* it8712f_enable_serial does not use its 1st parameter. */
it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();

7
src/mainboard/amd/mahogany/romstage.c
View File

@@ -31,7 +31,8 @@
#include "lib/delay.c"
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/ite/it8718f/early_serial.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
@@ -39,6 +40,8 @@
#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -81,7 +84,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_rs780_dev8();
sb7xx_51xx_lpc_init();
it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();

7
src/mainboard/amd/mahogany_fam10/romstage.c
View File

@@ -41,7 +41,8 @@
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
#include "superio/ite/it8718f/early_serial.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
@@ -50,6 +51,8 @@
#include "northbridge/amd/amdfam10/debug.c"
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
@@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_rs780_dev8();
sb7xx_51xx_lpc_init();
it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();

7
src/mainboard/amd/tilapia_fam10/romstage.c
View File

@@ -41,7 +41,8 @@
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
#include "superio/ite/it8718f/early_serial.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
@@ -49,6 +50,8 @@
#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
@@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_rs780_dev8();
sb7xx_51xx_lpc_init();
it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();

10
src/mainboard/asus/a8n_e/romstage.c
View File

@@ -21,8 +21,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* Used by it8712f_enable_serial(). */
/* Used by ite_enable_serial(). */
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO)
#include <stdint.h>
#include <string.h>
@@ -33,7 +34,8 @@
#include <pc80/mc146818rtc.h>
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/ite/it8712f/early_serial.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
#include <cpu/amd/model_fxx_rev.h>
#include <console/console.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
@@ -103,8 +105,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
it8712f_24mhz_clkin();
it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
/* Halt if there was a built in self test failure */

7
src/mainboard/asus/f2a85-m/romstage.c
View File

@@ -36,16 +36,19 @@
#include <southbridge/amd/agesa/hudson/smbus.h>
#include <stdint.h>
#include <string.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
/* TODO: remove .c includes */
#include <drivers/pc80/i8254.c>
#include <drivers/pc80/i8259.c>
#include <superio/ite/it8712f/early_serial.c>
#define MMIO_NON_POSTED_START 0xfed00000
#define MMIO_NON_POSTED_END 0xfedfffff
#define SB_MMIO 0xFED80000
#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x))
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
static void sbxxx_enable_48mhzout(void)
{
/* most likely programming to 48MHz out signal */
@@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* enable SIO clock */
sbxxx_enable_48mhzout();
it8712f_kill_watchdog();
it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_enable_3vsbsw();
console_init();

5
src/mainboard/asus/m2n-e/romstage.c
View File

@@ -37,6 +37,7 @@
#include <spd.h>
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8716f/it8716f.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
@@ -104,8 +105,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_24);
it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
setup_mb_resource_map();
report_bist_failure(bist);

5
src/mainboard/asus/m2v-mx_se/romstage.c
View File

@@ -38,7 +38,8 @@ unsigned int get_sbdn(unsigned bus);
#include "lib/delay.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/ite/it8712f/early_serial.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
#include "southbridge/via/vt8237r/early_smbus.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -127,7 +128,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
int needs_reset = 0;
struct sys_info *sysinfo = &sysinfo_car;
it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog();
it8712f_enable_3vsbsw();
console_init();

12
src/mainboard/asus/m2v/romstage.c
View File

@@ -38,7 +38,8 @@ unsigned int get_sbdn(unsigned bus);
#include "lib/delay.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/ite/it8712f/early_serial.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
#include "southbridge/via/vt8237r/early_smbus.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -46,6 +47,7 @@ unsigned int get_sbdn(unsigned bus);
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO)
#define IT8712F_GPIO_BASE 0x0a20
@@ -163,15 +165,13 @@ static void m2v_it8712f_gpio_init(void)
* 0xc0=0x17, 0xc8=0x17 gpio port 1 select & output enable
* 0xc4=0xc1, 0xcc=0xc1 gpio port 5 select & output enable
*/
it8712f_enter_conf();
giv = gpio_init_data;
while (giv->addr) {
printk(BIOS_SPEW, "it8712f gpio: %02x=%02x\n",
giv->addr, giv->val);
it8712f_sio_write(IT8712F_GPIO, giv->addr, giv->val);
ite_reg_write(IT8712F_GPIO, giv->addr, giv->val);
giv++;
}
it8712f_exit_conf();
printk(BIOS_INFO, "it8712f gpio: Setting DDR2 voltage to 1.80V\n");
/*
@@ -225,8 +225,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
int needs_reset = 0;
struct sys_info *sysinfo = &sysinfo_car;
it8712f_24mhz_clkin();
it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog();
console_init();
enable_rom_decode();

7
src/mainboard/asus/m4a78-em/romstage.c
View File

@@ -41,7 +41,8 @@
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
#include "superio/ite/it8712f/early_serial.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
@@ -49,6 +50,8 @@
#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
@@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_rs780_dev8();
sb7xx_51xx_lpc_init();
it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog();
console_init();

7
src/mainboard/asus/m4a785-m/romstage.c
View File

@@ -41,7 +41,8 @@
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
#include "superio/ite/it8712f/early_serial.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
@@ -49,6 +50,8 @@
#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
@@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_rs780_dev8();
sb7xx_51xx_lpc_init();
it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog();
console_init();

3
src/mainboard/asus/m5a88-v/romstage.c
View File

@@ -41,6 +41,7 @@
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8721f/it8721f.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
@@ -100,7 +101,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_rs780_dev8();
sb800_clk_output_48Mhz();
it8721f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
printk(BIOS_DEBUG, "\n");

10
src/mainboard/ecs/p6iwp-fe/romstage.c
View File

@@ -30,13 +30,17 @@
#include "northbridge/intel/i82810/raminit.h"
#include "drivers/pc80/udelay_io.c"
#include "cpu/x86/bist.h"
#include "superio/ite/it8712f/early_serial.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO)
void main(unsigned long bist)
{
it8712f_24mhz_clkin();
it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter
ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
report_bist_failure(bist);
enable_smbus();

3
src/mainboard/gigabyte/ga-6bxc/romstage.c
View File

@@ -30,8 +30,7 @@
#include "drivers/pc80/udelay_io.c"
#include "lib/delay.c"
#include "cpu/x86/bist.h"
void it8671f_48mhz_clkin(void);
#include "superio/ite/it8671f/early_serial.c"
#include <superio/ite/it8671f/it8671f.h>
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1)

3
src/mainboard/gigabyte/ga-6bxe/romstage.c
View File

@@ -30,8 +30,7 @@
#include "drivers/pc80/udelay_io.c"
#include "lib/delay.c"
#include "cpu/x86/bist.h"
static void it8671f_48mhz_clkin(void);
#include "superio/ite/it8671f/early_serial.c"
#include <superio/ite/it8671f/it8671f.h>
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1)

5
src/mainboard/gigabyte/ga_2761gxdk/romstage.c
View File

@@ -38,6 +38,7 @@
#include "lib/delay.c"
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8716f/it8716f.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
@@ -125,8 +126,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_48);
it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
setup_mb_resource_map();

5
src/mainboard/gigabyte/m57sli/romstage.c
View File

@@ -35,6 +35,7 @@
#include "lib/delay.c"
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8716f/it8716f.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
@@ -133,8 +134,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV);
#endif
it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_48);
it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
setup_mb_resource_map();

7
src/mainboard/gigabyte/ma785gm/romstage.c
View File

@@ -37,7 +37,8 @@
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
#include "superio/ite/it8718f/early_serial.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
@@ -45,6 +46,8 @@
#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
@@ -91,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_rs780_dev8();
sb7xx_51xx_lpc_init();
it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8718f_disable_reboot();
console_init();

7
src/mainboard/gigabyte/ma785gmt/romstage.c
View File

@@ -37,7 +37,8 @@
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
#include "superio/ite/it8718f/early_serial.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
@@ -45,6 +46,8 @@
#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
@@ -91,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_rs780_dev8();
sb7xx_51xx_lpc_init();
it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8718f_disable_reboot();
console_init();

7
src/mainboard/gigabyte/ma78gm/romstage.c
View File

@@ -41,7 +41,8 @@
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
#include "superio/ite/it8718f/early_serial.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
@@ -49,6 +50,8 @@
#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
@@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_rs780_dev8();
sb7xx_51xx_lpc_init();
it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8718f_disable_reboot();
console_init();

16
src/mainboard/lippert/hurricane-lx/romstage.c
View File

@@ -35,9 +35,13 @@
#include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
#include "superio/ite/it8712f/early_serial.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
#include "northbridge/amd/lx/raminit.h"
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
/* Bit0 enables Spread Spectrum. */
#define SMC_CONFIG 0x01
@@ -77,7 +81,6 @@ static int smc_send_config(unsigned char config_data)
#include "cpu/amd/geode_lx/msrinit.c"
static const u16 sio_init_table[] = { // hi=data, lo=index
0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...)
0x042C, // disable ATXPG; VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 enabled
0x1423, // don't delay PoWeROK1/2
0x9072, // watchdog triggers PWROK, counts seconds
@@ -101,13 +104,10 @@ static void mb_gpio_init(void)
int i;
/* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */
it8712f_enter_conf();
for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) {
u16 val = sio_init_table[i];
outb((u8)val, SIO_INDEX);
outb(val >> 8, SIO_DATA);
u16 reg = sio_init_table[i];
ite_reg_write(GPIO_DEV, (u8) reg, (reg >> 8));
}
it8712f_exit_conf();
}
void main(unsigned long bist)
@@ -126,7 +126,7 @@ void main(unsigned long bist)
* Note: Must do this AFTER the early_setup! It is counting on some
* early MSR setup for CS5536.
*/
it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
mb_gpio_init();
console_init();

16
src/mainboard/lippert/literunner-lx/romstage.c
View File

@@ -35,9 +35,13 @@
#include "southbridge/amd/cs5536/cs5536.h"
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
#include "superio/ite/it8712f/early_serial.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
#include "northbridge/amd/lx/raminit.h"
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
/* Bit0 enables Spread Spectrum, bit1 makes on-board CF slot act as IDE slave. */
#if CONFIG_ONBOARD_IDE_SLAVE
#define SMC_CONFIG 0x03
@@ -118,7 +122,6 @@ static int smc_send_config(unsigned char config_data)
#include "cpu/amd/geode_lx/msrinit.c"
static const u16 sio_init_table[] = { // hi=data, lo=index
0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...)
0x072C, // VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal
0x1423, // don't delay PoWeROK1/2
0x9072, // watchdog triggers PWROK, counts seconds
@@ -143,13 +146,10 @@ static void mb_gpio_init(void)
int i;
/* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */
it8712f_enter_conf();
for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) {
u16 val = sio_init_table[i];
outb((u8)val, SIO_INDEX);
outb(val >> 8, SIO_DATA);
u16 reg = sio_init_table[i];
ite_reg_write(GPIO_DEV, (u8) reg, (reg >> 8));
}
it8712f_exit_conf();
}
void main(unsigned long bist)
@@ -169,7 +169,7 @@ void main(unsigned long bist)
* Note: Must do this AFTER the early_setup! It is counting on some
* early MSR setup for CS5536.
*/
it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
mb_gpio_init();
console_init();

16
src/mainboard/lippert/roadrunner-lx/romstage.c
View File

@@ -35,9 +35,13 @@
#include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
#include "superio/ite/it8712f/early_serial.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
#include "northbridge/amd/lx/raminit.h"
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
int spd_read_byte(unsigned int device, unsigned int address)
{
if (device != DIMM0)
@@ -53,7 +57,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
#include "cpu/amd/geode_lx/msrinit.c"
static const u16 sio_init_table[] = { // hi=data, lo=index
0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...)
0x1E2C, // disable ATXPG; VIN6,FAN4/5,VIN3 enabled, VIN7 internal
0x1423, // don't delay PoWeROK1/2 - triggers 2nd reset
0x9072, // watchdog triggers PWROK, counts seconds
@@ -76,13 +79,10 @@ static void mb_gpio_init(void)
int i;
/* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */
it8712f_enter_conf();
for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) {
u16 val = sio_init_table[i];
outb((u8)val, SIO_INDEX);
outb(val >> 8, SIO_DATA);
u16 reg = sio_init_table[i];
ite_reg_write(GPIO_DEV, (u8) reg, (reg >> 8));
}
it8712f_exit_conf();
}
void main(unsigned long bist)
@@ -101,7 +101,7 @@ void main(unsigned long bist)
* Note: must do this AFTER the early_setup! It is counting on some
* early MSR setup for CS5536.
*/
it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
mb_gpio_init();
console_init();

16
src/mainboard/lippert/spacerunner-lx/romstage.c
View File

@@ -35,9 +35,13 @@
#include "southbridge/amd/cs5536/cs5536.h"
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
#include "superio/ite/it8712f/early_serial.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
#include "northbridge/amd/lx/raminit.h"
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
/* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */
#if CONFIG_ONBOARD_IDE_SLAVE
#define SMC_CONFIG 0x03
@@ -118,7 +122,6 @@ static int smc_send_config(unsigned char config_data)
#include "cpu/amd/geode_lx/msrinit.c"
static const u16 sio_init_table[] = { // hi=data, lo=index
0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...)
0x072C, // VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal
0x1423, // don't delay PoWeROK1/2
0x9072, // watchdog triggers PWROK, counts seconds
@@ -140,13 +143,10 @@ static void mb_gpio_init(void)
int i;
/* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */
it8712f_enter_conf();
for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) {
u16 val = sio_init_table[i];
outb((u8)val, SIO_INDEX);
outb(val >> 8, SIO_DATA);
u16 reg = sio_init_table[i];
ite_reg_write(GPIO_DEV, (u8) reg, (reg >> 8));
}
it8712f_exit_conf();
}
void main(unsigned long bist)
@@ -166,7 +166,7 @@ void main(unsigned long bist)
* Note: Must do this AFTER the early_setup! It is counting on some
* early MSR setup for CS5536.
*/
it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
mb_gpio_init();
console_init();

8
src/mainboard/siemens/sitemp_g1p1/romstage.c
View File

@@ -35,7 +35,8 @@
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/ite/it8712f/early_serial.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
#include "cpu/x86/bist.h"
@@ -45,6 +46,8 @@
#include "southbridge/amd/sb600/early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
static void memreset(int controllers, const struct mem_controller *ctrl)
{
@@ -103,8 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 0)
check_cmos(); // rebooting in case of corrupted cmos !!!!!
#endif
/* it8712f_enable_serial does not use its 1st parameter. */
it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog();
console_init();

3
src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
View File

@@ -30,8 +30,7 @@
#include "drivers/pc80/udelay_io.c"
#include "lib/delay.c"
#include "cpu/x86/bist.h"
void it8671f_48mhz_clkin(void);
#include "superio/ite/it8671f/early_serial.c"
#include <superio/ite/it8671f/it8671f.h>
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x370, IT8671F_SP1)

8
src/mainboard/technexion/tim5690/romstage.c
View File

@@ -32,12 +32,15 @@
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/ite/it8712f/early_serial.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs690/early_setup.c"
#include "southbridge/amd/sb600/early_setup.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -85,8 +88,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_rs690_dev8();
sb600_lpc_init();
/* it8712f_enable_serial does not use its 1st parameter. */
it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog();
console_init();

8
src/mainboard/technexion/tim8690/romstage.c
View File

@@ -32,12 +32,15 @@
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/ite/it8712f/early_serial.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs690/early_setup.c"
#include "southbridge/amd/sb600/early_setup.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -80,8 +83,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_rs690_dev8();
sb600_lpc_init();
/* it8712f_enable_serial does not use its 1st parameter. */
it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog();
console_init();

3
src/mainboard/via/pc2500e/romstage.c
View File

@@ -32,6 +32,7 @@
#include "drivers/pc80/udelay_io.c"
#include "lib/delay.c"
#include "southbridge/via/vt8237r/early_smbus.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8716f/it8716f.h>
#include <spd.h>
@@ -59,7 +60,7 @@ void main(unsigned long bist)
/* Enable multifunction for northbridge. */
pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
enable_smbus();
smbus_fixup(&ctrl);