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superio/ite/*: Factor out generic romstage component

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Following the reasoning of:
cf7b498 superio/fintek/*: Factor out generic romstage component

Change-Id: I4c0a9a5a7786eb8fcb0c3ed6251c7fe9bbbadae7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5585
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
This commit is contained in:
Edward O'Callaghan
2014-04-27 00:41:50 +10:00
committed by Rudolf Marek
parent 946bee1c34
commit f29200240e
50 changed files with 247 additions and 386 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
src/superio/ite/Kconfig
View File

@@ -2,6 +2,7 @@
## This file is part of the coreboot project.
##
## Copyright (C) 2009 Ronald G. Minnich
## Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -17,24 +18,45 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
# Generic ITE romstage driver - Just enough UART initialisation code for
# romstage.
config SUPERIO_ITE_COMMON_ROMSTAGE
bool
config SUPERIO_ITE_IT8661F
bool
select SUPERIO_ITE_COMMON_ROMSTAGE
config SUPERIO_ITE_IT8671F
bool
select SUPERIO_ITE_COMMON_ROMSTAGE
config SUPERIO_ITE_IT8712F
bool
select SUPERIO_ITE_COMMON_ROMSTAGE
config SUPERIO_ITE_IT8716F
bool
select SUPERIO_ITE_COMMON_ROMSTAGE
config SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
bool
depends on SUPERIO_ITE_IT8716F
default n
select SUPERIO_ITE_COMMON_ROMSTAGE
config SUPERIO_ITE_IT8718F
bool
select SUPERIO_ITE_COMMON_ROMSTAGE
config SUPERIO_ITE_IT8721F
bool
select SUPERIO_ITE_COMMON_ROMSTAGE
config SUPERIO_ITE_IT8728F
bool
select SUPERIO_ITE_COMMON_ROMSTAGE
config SUPERIO_ITE_IT8772F
bool
select SUPERIO_ITE_COMMON_ROMSTAGE

3
src/superio/ite/Makefile.inc
View File

@@ -17,6 +17,9 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
## include generic ite pre-ram stage driver
romstage-$(CONFIG_SUPERIO_ITE_COMMON_ROMSTAGE) += common/early_serial.c
subdirs-y += it8661f
subdirs-y += it8671f
subdirs-y += it8712f

53
src/superio/ite/it8721f/early_serial.c → src/superio/ite/common/early_serial.c
View File

@@ -1,8 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2011 QingPei Wang <wangqingpei@gmail.com>
* Copyright (C) 2013 Damien Zammit <damien@zamaudio.com>
* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
*
* This program is free software; you can redistribute it and/or modify
@@ -23,21 +22,23 @@
#include <arch/io.h>
#include <device/pnp.h>
#include <stdint.h>
#include "it8721f.h"
#include "ite.h"
/* Global configuration registers. */
#define IT8721F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
#define IT8721F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
#define IT8721F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
#define IT8721F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
#define ITE_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
#define ITE_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
#define ITE_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
#define ITE_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
static void it8721f_sio_write(device_t dev, u8 index, u8 value)
/* Helper procedure */
static void ite_sio_write(device_t dev, u8 reg, u8 value)
{
pnp_set_logical_device(dev);
pnp_write_config(dev, index, value);
pnp_write_config(dev, reg, value);
}
static void it8721f_enter_conf(device_t dev)
/* Enable configuration */
static void pnp_enter_conf_state(device_t dev)
{
u16 port = dev >> 8;
@@ -47,39 +48,39 @@ static void it8721f_enter_conf(device_t dev)
outb((port == 0x4e) ? 0xaa : 0x55, port);
}
static void it8721f_exit_conf(device_t dev)
/* Disable configuration */
static void pnp_exit_conf_state(device_t dev)
{
it8721f_sio_write(dev, IT8721F_CONFIG_REG_CC, 0x02);
ite_sio_write(dev, ITE_CONFIG_REG_CC, 0x02);
}
static void it8721f_reg_write(device_t dev, u8 index, u8 value)
void ite_reg_write(device_t dev, u8 reg, u8 value)
{
it8721f_enter_conf(dev);
it8721f_sio_write(dev, index, value);
it8721f_exit_conf(dev);
pnp_enter_conf_state(dev);
ite_sio_write(dev, reg, value);
pnp_exit_conf_state(dev);
}
/*
* in romstage.c
* #define CLKIN_DEV PNP_DEV(0x2e, IT8721F_GPIO)
* #define CLKIN_DEV PNP_DEV(0x2e, ITE_GPIO)
* and pass: CLKIN_DEV
* IT8721F_UART_CLK_PREDIVIDE_24
* IT8721F_UART_CLK_PREDIVIDE_48 (default)
* ITE_UART_CLK_PREDIVIDE_24
* ITE_UART_CLK_PREDIVIDE_48 (default)
*/
void it8721f_conf_clkin(device_t dev, u8 predivide)
void ite_conf_clkin(device_t dev, u8 predivide)
{
it8721f_reg_write(dev, IT8721F_CONFIG_REG_CLOCKSEL, (0x1 & predivide));
ite_reg_write(dev, ITE_CONFIG_REG_CLOCKSEL, (0x1 & predivide));
}
/* Enable the serial port(s). */
void it8721f_enable_serial(device_t dev, u16 iobase)
/* Bring up early serial debugging output before the RAM is initialized. */
void ite_enable_serial(device_t dev, u16 iobase)
{
it8721f_enter_conf(dev);
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
it8721f_exit_conf(dev);
pnp_exit_conf_state(dev);
}

36
src/superio/ite/common/ite.h Normal file
View File

@@ -0,0 +1,36 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef SUPERIO_ITE_COMMON_ROMSTAGE_H
#define SUPERIO_ITE_COMMON_ROMSTAGE_H
#include <arch/io.h>
#include <stdint.h>
#define ITE_UART_CLK_PREDIVIDE_48 0x00 /* default */
#define ITE_UART_CLK_PREDIVIDE_24 0x01
void ite_conf_clkin(device_t dev, u8 predivide);
void ite_enable_serial(device_t dev, u16 iobase);
/* Some boards need to init wdt+gpio's very early */
void ite_reg_write(device_t dev, u8 reg, u8 value);
#endif /* SUPERIO_ITE_COMMON_ROMSTAGE_H */

2
src/superio/ite/it8671f/Makefile.inc
View File

@@ -18,5 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
romstage-$(CONFIG_SUPERIO_ITE_IT8671F) += early_serial.c
ramstage-$(CONFIG_SUPERIO_ITE_IT8671F) += superio.c

4
src/superio/ite/it8671f/early_serial.c
View File

@@ -19,6 +19,8 @@
*/
#include <arch/io.h>
#include <device/pnp.h>
#include <stdint.h>
#include "it8671f.h"
/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */
@@ -87,7 +89,7 @@ void it8671f_48mhz_clkin(void)
}
/* Enable the serial port(s). */
static void it8671f_enable_serial(device_t dev, u16 iobase)
void it8671f_enable_serial(device_t dev, u16 iobase)
{
it8671f_enter_conf();

12
src/superio/ite/it8671f/it8671f.h
View File

@@ -18,8 +18,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef SUPERIO_ITE_IT8671F_IT8671F_H
#define SUPERIO_ITE_IT8671F_IT8671F_H
#ifndef SUPERIO_ITE_IT8671F_H
#define SUPERIO_ITE_IT8671F_H
#include <arch/io.h>
#include <stdint.h>
/* Datasheet: Not available online, got it from ITE per request. */
@@ -30,4 +33,7 @@
#define IT8671F_KBCK 0x05 /* PS/2 keyboard */
#define IT8671F_KBCM 0x06 /* PS/2 mouse */
#endif
void it8671f_48mhz_clkin(void);
void it8671f_enable_serial(device_t dev, u16 iobase);
#endif /* SUPERIO_ITE_IT8671F__H */

2
src/superio/ite/it8712f/Makefile.inc
View File

@@ -18,5 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
romstage-$(CONFIG_SUPERIO_ITE_IT8712F) += early_serial.c
ramstage-$(CONFIG_SUPERIO_ITE_IT8712F) += superio.c

38
src/superio/ite/it8712f/early_serial.c
View File

@@ -19,6 +19,8 @@
*/
#include <arch/io.h>
#include <device/pnp.h>
#include <stdint.h>
#include "it8712f.h"
/* The base address is 0x2e or 0x4e, depending on config bytes. */
@@ -30,7 +32,6 @@
#define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
#define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
#define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
#define IT8712F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
#define IT8712F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
#define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */
#define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */
@@ -58,14 +59,6 @@ static void it8712f_exit_conf(void)
it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02);
}
/* Select 24MHz CLKIN (48MHz is the default). */
void it8712f_24mhz_clkin(void)
{
it8712f_enter_conf();
it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x1);
it8712f_exit_conf();
}
/*
* We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2!
*
@@ -88,30 +81,3 @@ void it8712f_kill_watchdog(void)
it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_WATCHDOG, 0x00);
it8712f_exit_conf();
}
/* Enable the serial port(s). */
void it8712f_enable_serial(device_t dev, u16 iobase)
{
/* (1) Enter the configuration state (MB PnP mode). */
it8712f_enter_conf();
/* (2) Modify the data of configuration registers. */
/*
* Select the chip to configure (if there's more than one).
* Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
* If this register is not written, both chips are configured.
*/
/* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CONFIGSEL, 0x00); */
/* Enable serial port(s). */
it8712f_sio_write(IT8712F_SP1, 0x30, 0x1); /* Serial port 1 */
it8712f_sio_write(IT8712F_SP2, 0x30, 0x1); /* Serial port 2 */
/* Clear software suspend mode (clear bit 0). TODO: Needed? */
/* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_SWSUSP, 0x00); */
/* (3) Exit the configuration state (MB PnP mode). */
it8712f_exit_conf();
}

9
src/superio/ite/it8712f/it8712f.h
View File

@@ -18,8 +18,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef SUPERIO_ITE_IT8712F_IT8712F_H
#define SUPERIO_ITE_IT8712F_IT8712F_H
#ifndef SUPERIO_ITE_IT8712F_H
#define SUPERIO_ITE_IT8712F_H
/* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8712_2.asp */
@@ -36,7 +36,6 @@
#define IT8712F_IR 0x0a /* Consumer IR */
void it8712f_kill_watchdog(void);
void it8712f_enable_serial(device_t dev, u16 iobase);
void it8712f_24mhz_clkin(void);
void it8712f_enable_3vsbsw(void);
#endif
#endif /* SUPERIO_ITE_IT8712F_H */

1
src/superio/ite/it8716f/Makefile.inc
View File

@@ -18,5 +18,4 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
romstage-$(CONFIG_SUPERIO_ITE_IT8716F) += early_serial.c
ramstage-$(CONFIG_SUPERIO_ITE_IT8716F) += superio.c

79
src/superio/ite/it8716f/early_serial.c
View File

@@ -1,79 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2007 AMD Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <device/pnp.h>
#include "it8716f.h"
/* Global configuration registers. */
#define IT8716F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
#define IT8716F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
#define IT8716F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
#define IT8716F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
#define IT8716F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
static void it8716f_enter_conf(device_t dev)
{
u16 port = dev >> 8;
outb(0x87, port);
outb(0x01, port);
outb(0x55, port);
outb((port == 0x4e) ? 0xaa : 0x55, port);
}
static void it8716f_exit_conf(device_t dev)
{
pnp_write_config(dev, IT8716F_CONFIG_REG_CC, 0x02);
}
static void it8716f_reg_write(device_t dev, u8 index, u8 value)
{
it8716f_enter_conf(dev);
pnp_write_config(dev, index, value);
it8716f_exit_conf(dev);
}
/*
* in romstage.c
* #define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO)
* and pass: CLKIN_DEV
* IT8716F_UART_CLK_PREDIVIDE_24
* IT8716F_UART_CLK_PREDIVIDE_48 (default)
*/
void it8716f_conf_clkin(device_t dev, u8 predivide)
{
it8716f_reg_write(dev, IT8716F_CONFIG_REG_CLOCKSEL, (0x1 & predivide));
}
/* Enable the serial port(s). */
void it8716f_enable_serial(device_t dev, u16 iobase)
{
it8716f_enter_conf(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
it8716f_exit_conf(dev);
}

7
src/superio/ite/it8716f/it8716f.h
View File

@@ -21,7 +21,6 @@
#ifndef SUPERIO_ITE_IT8716F_H
#define SUPERIO_ITE_IT8716F_H
#include <device/pnp.h>
#include <stdint.h>
/* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8716_2.asp */
@@ -39,12 +38,6 @@
#define IT8716F_GAME 0x09 /* GAME port */
#define IT8716F_IR 0x0a /* Consumer IR */
#define IT8716F_UART_CLK_PREDIVIDE_48 0x00 /* default */
#define IT8716F_UART_CLK_PREDIVIDE_24 0x01
void it8716f_conf_clkin(device_t dev, u8 predivide);
void it8716f_enable_serial(device_t dev, u16 iobase);
#if CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
/* Provided by mainboard, called by IT8716F superio.c. */
void init_ec(u16 base);

2
src/superio/ite/it8718f/Makefile.inc
View File

@@ -18,5 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
romstage-$(CONFIG_SUPERIO_ITE_IT8718F) += early_serial.c
ramstage-$(CONFIG_SUPERIO_ITE_IT8718F) += superio.c

35
src/superio/ite/it8718f/early_serial.c
View File

@@ -30,7 +30,6 @@
#define IT8718F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
#define IT8718F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
#define IT8718F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
#define IT8718F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
#define IT8718F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
static void it8718f_sio_write(u8 ldn, u8 index, u8 value)
@@ -56,13 +55,6 @@ static void it8718f_exit_conf(void)
it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02);
}
/* Select 24MHz CLKIN (48MHz default). */
void it8718f_24mhz_clkin(void)
{
it8718f_enter_conf();
it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x1);
it8718f_exit_conf();
}
/*
* GIGABYTE uses a special Super I/O register to protect its Dual BIOS
@@ -75,30 +67,3 @@ void it8718f_disable_reboot(void)
it8718f_sio_write(IT8718F_GPIO, 0xEF, 0x7E);
it8718f_exit_conf();
}
/* Enable the serial port(s). */
void it8718f_enable_serial(device_t dev, u16 iobase)
{
/* (1) Enter the configuration state (MB PnP mode). */
it8718f_enter_conf();
/* (2) Modify the data of configuration registers. */
/*
* Select the chip to configure (if there's more than one).
* Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
* If this register is not written, both chips are configured.
*/
/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */
/* Enable serial port(s). */
it8718f_sio_write(IT8718F_SP1, 0x30, 0x1); /* Serial port 1 */
it8718f_sio_write(IT8718F_SP2, 0x30, 0x1); /* Serial port 2 */
/* Clear software suspend mode (clear bit 0). TODO: Needed? */
/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */
/* (3) Exit the configuration state (MB PnP mode). */
it8718f_exit_conf();
}

8
src/superio/ite/it8718f/it8718f.h
View File

@@ -18,8 +18,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef SUPERIO_ITE_IT8718F_IT8718F_H
#define SUPERIO_ITE_IT8718F_IT8718F_H
#ifndef SUPERIO_ITE_IT8718F_H
#define SUPERIO_ITE_IT8718F_H
/* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8718_2.asp */
@@ -34,9 +34,7 @@
#define IT8718F_IR 0x0a /* Consumer IR */
#if defined(__PRE_RAM__)
void it8718f_24mhz_clkin(void);
void it8718f_disable_reboot(void);
void it8718f_enable_serial(device_t dev, u16 iobase);
#endif
#endif
#endif /* SUPERIO_ITE_IT8718F_H */

1
src/superio/ite/it8721f/Makefile.inc
View File

@@ -18,5 +18,4 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
romstage-$(CONFIG_SUPERIO_ITE_IT8721F) += early_serial.c
ramstage-$(CONFIG_SUPERIO_ITE_IT8721F) += superio.c

6
src/superio/ite/it8721f/it8721f.h
View File

@@ -36,10 +36,4 @@
#define IT8721F_GPIO 0x07 /* GPIO */
#define IT8721F_IR 0x0a /* Consumer IR */
#define IT8721F_UART_CLK_PREDIVIDE_48 0x00 /* default */
#define IT8721F_UART_CLK_PREDIVIDE_24 0x01
void it8721f_conf_clkin(device_t dev, u8 predivide);
void it8721f_enable_serial(device_t dev, u16 iobase);
#endif /* SUPERIO_ITE_IT8721F_H */

1
src/superio/ite/it8728f/Makefile.inc
View File

@@ -18,6 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
romstage-$(CONFIG_SUPERIO_ITE_IT8728F) += early_serial.c
ramstage-$(CONFIG_SUPERIO_ITE_IT8728F) += it8728f_hwm.c
ramstage-$(CONFIG_SUPERIO_ITE_IT8728F) += superio.c

74
src/superio/ite/it8728f/early_serial.c
View File

@@ -1,74 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2013 Damien Zammit <damien@zamaudio.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <device/pnp.h>
#include "it8728f.h"
/* Superio raw commands */
static void it8728f_sio_write(device_t dev, u8 index, u8 value)
{
pnp_set_logical_device(dev);
pnp_write_config(dev, index, value);
}
static void it8728f_enter_conf(device_t dev)
{
u16 port = dev >> 8;
outb(0x87, port);
outb(0x01, port);
outb(0x55, port);
outb((port == 0x4e) ? 0xaa : 0x55, port);
}
static void it8728f_exit_conf(device_t dev)
{
it8728f_sio_write(dev, IT8728F_CONFIG_REG_CC, 0x02);
}
/* Superio low level commands */
void it8728f_reg_write(device_t dev, u8 index, u8 value)
{
it8728f_enter_conf(dev);
it8728f_sio_write(dev, index, value);
it8728f_exit_conf(dev);
}
void it8728f_24mhz_clkin(device_t dev)
{
it8728f_reg_write(dev, IT8728F_CONFIG_REG_CLOCKSEL, 0x1);
}
void it8728f_enable_serial(device_t dev, u16 iobase)
{
/* (1) Enter the configuration state (MB PnP mode). */
it8728f_enter_conf(dev);
/* (2) Modify the data of configuration registers. */
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
/* (3) Exit the configuration state (MB PnP mode). */
it8728f_exit_conf(dev);
}

12
src/superio/ite/it8728f/it8728f.h
View File

@@ -39,16 +39,4 @@
#define IT8728F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
#define IT8728F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. 'Special register' */
/*
* Superio low level commands
* Pass dev = PNP_DEV(superiobase, LDN)
*/
void it8728f_reg_write(device_t dev, u8 index, u8 value);
/* Select 24MHz CLKIN (48MHz default). */
void it8728f_24mhz_clkin(device_t dev);
/* Enable the serial port(s). */
void it8728f_enable_serial(device_t dev, u16 iobase);
#endif /* SUPERIO_ITE_IT8728F_H */