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drivers/intel/gma: Move IGD OpRegion to CBMEM

Browse Source 
It never was in GNVS, it never belonged among the ACPI tables. Having
it in CBMEM, makes it easy to look the location up on resume, and saves
us additional boilerplate.

TEST=Booted Linux on Lenovo/X201s, confirmed ASLS is set and
     intel_backlight + acpi_video synchronize, both before and
     after suspend.

Change-Id: I5fdd6634e4a671a85b1df8bc9815296ff42edf29
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40724
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nico Huber
2020-04-26 17:01:25 +02:00
parent 4dc4cb6b5c
commit f2a0be235c
41 changed files with 65 additions and 1252 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
src/soc/intel/apollolake/graphics.c
View File

@@ -20,6 +20,8 @@ uintptr_t fsp_soc_get_igd_bar(void)
void graphics_soc_init(struct device *const dev)
{
intel_gma_init_igd_opregion();
if (CONFIG(RUN_FSP_GOP))
return;
@@ -38,20 +40,3 @@ void graphics_soc_init(struct device *const dev)
pci_dev_init(dev);
}
}
uintptr_t graphics_soc_write_acpi_opregion(const struct device *device,
uintptr_t current, struct acpi_rsdp *rsdp)
{
igd_opregion_t *opregion;
printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
opregion = (igd_opregion_t *)current;
if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
return current;
/* FIXME: Add platform specific mailbox initialization */
current += sizeof(igd_opregion_t);
return acpi_align_current(current);
}

42
src/soc/intel/baytrail/acpi/globalnvs.asl
View File

@@ -53,48 +53,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
TOLM, 32, // 0x34 - Top of Low Memory
CBMC, 32, // 0x38 - coreboot mem console pointer
/* IGD OpRegion */
Offset (0xb4),
ASLB, 32, // 0xb4 - IGD OpRegion Base Address
IBTT, 8, // 0xb8 - IGD boot panel device
IPAT, 8, // 0xb9 - IGD panel type CMOS option
ITVF, 8, // 0xba - IGD TV format CMOS option
ITVM, 8, // 0xbb - IGD TV minor format option
IPSC, 8, // 0xbc - IGD panel scaling
IBLC, 8, // 0xbd - IGD BLC config
IBIA, 8, // 0xbe - IGD BIA config
ISSC, 8, // 0xbf - IGD SSC config
I409, 8, // 0xc0 - IGD 0409 modified settings
I509, 8, // 0xc1 - IGD 0509 modified settings
I609, 8, // 0xc2 - IGD 0609 modified settings
I709, 8, // 0xc3 - IGD 0709 modified settings
IDMM, 8, // 0xc4 - IGD Power conservation feature
IDMS, 8, // 0xc5 - IGD DVMT memory size
IF1E, 8, // 0xc6 - IGD function 1 enable
HVCO, 8, // 0xc7 - IGD HPLL VCO
NXD1, 32, // 0xc8 - IGD _DGS next DID1
NXD2, 32, // 0xcc - IGD _DGS next DID2
NXD3, 32, // 0xd0 - IGD _DGS next DID3
NXD4, 32, // 0xd4 - IGD _DGS next DID4
NXD5, 32, // 0xd8 - IGD _DGS next DID5
NXD6, 32, // 0xdc - IGD _DGS next DID6
NXD7, 32, // 0xe0 - IGD _DGS next DID7
NXD8, 32, // 0xe4 - IGD _DGS next DID8
ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI)
PAVP, 8, // 0xe9 - IGD PAVP data
Offset (0xeb),
OSCC, 8, // 0xeb - PCIe OSC control
NPCE, 8, // 0xec - native PCIe support
PLFL, 8, // 0xed - platform flavor
BREV, 8, // 0xee - board revision
DPBM, 8, // 0xef - digital port b mode
DPCM, 8, // 0xf0 - digital port c mode
DPDM, 8, // 0xf1 - digital port d mode
ALFP, 8, // 0xf2 - active lfp
IMON, 8, // 0xf3 - current graphics turbo imon value
MMIO, 8, // 0xf4 - 64bit mmio support
/* ChromeOS specific */
Offset (0x100),
#include <vendorcode/google/chromeos/acpi/gnvs.asl>

47
src/soc/intel/baytrail/gfx.c
View File

@@ -10,10 +10,8 @@
#include <reg_script.h>
#include <soc/gfx.h>
#include <soc/iosf.h>
#include <soc/nvs.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <cbmem.h>
#include <types.h>
#include "chip.h"
@@ -352,21 +350,10 @@ static void gfx_panel_setup(struct device *dev)
}
}
uintptr_t gma_get_gnvs_aslb(const void *gnvs)
{
const global_nvs_t *gnvs_ptr = gnvs;
return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
}
void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
{
global_nvs_t *gnvs_ptr = gnvs;
if (gnvs_ptr)
gnvs_ptr->aslb = aslb;
}
static void gfx_init(struct device *dev)
{
intel_gma_init_igd_opregion();
/* Pre VBIOS Init */
gfx_pre_vbios_init(dev);
@@ -380,9 +367,6 @@ static void gfx_init(struct device *dev)
/* Post VBIOS Init */
gfx_post_vbios_init(dev);
/* Restore opregion on S3 resume */
intel_gma_restore_opregion();
}
static void gma_generate_ssdt(const struct device *dev)
@@ -392,39 +376,12 @@ static void gma_generate_ssdt(const struct device *dev)
drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
}
static unsigned long
gma_write_acpi_tables(const struct device *const dev,
unsigned long current,
struct acpi_rsdp *const rsdp)
{
igd_opregion_t *opregion = (igd_opregion_t *)current;
global_nvs_t *gnvs;
if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
return current;
current += sizeof(igd_opregion_t);
/* GNVS has been already set up */
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (gnvs) {
/* IGD OpRegion Base Address */
gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion);
} else {
printk(BIOS_ERR, "Error: GNVS table not found.\n");
}
current = acpi_align_current(current);
return current;
}
static struct device_operations gfx_device_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = gfx_init,
.ops_pci = &soc_pci_ops,
.write_acpi_tables = gma_write_acpi_tables,
.acpi_fill_ssdt = gma_generate_ssdt,
};

35
src/soc/intel/baytrail/include/soc/nvs.h
View File

@@ -46,40 +46,7 @@ typedef struct global_nvs_t {
u32 cbmc; /* 0x38 - coreboot memconsole */
u8 rsvd3[120]; /* 0x3c - 0xb3 - unused */
/* IGD OpRegion */
u32 aslb; /* 0xb4 - IGD OpRegion Base Address */
u8 ibtt; /* 0xb8 - IGD boot type */
u8 ipat; /* 0xb9 - IGD panel type */
u8 itvf; /* 0xba - IGD TV format */
u8 itvm; /* 0xbb - IGD TV minor format */
u8 ipsc; /* 0xbc - IGD Panel Scaling */
u8 iblc; /* 0xbd - IGD BLC configuration */
u8 ibia; /* 0xbe - IGD BIA configuration */
u8 issc; /* 0xbf - IGD SSC configuration */
u8 i409; /* 0xc0 - IGD 0409 modified settings */
u8 i509; /* 0xc1 - IGD 0509 modified settings */
u8 i609; /* 0xc2 - IGD 0609 modified settings */
u8 i709; /* 0xc3 - IGD 0709 modified settings */
u8 idmm; /* 0xc4 - IGD Power Conservation */
u8 idms; /* 0xc5 - IGD DVMT memory size */
u8 if1e; /* 0xc6 - IGD Function 1 Enable */
u8 hvco; /* 0xc7 - IGD HPLL VCO */
u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */
u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */
u8 pavp; /* 0xe9 - IGD PAVP data */
u8 rsvd12; /* 0xea - rsvd */
u8 oscc; /* 0xeb - PCIe OSC control */
u8 npce; /* 0xec - native PCIe support */
u8 plfl; /* 0xed - platform flavor */
u8 brev; /* 0xee - board revision */
u8 dpbm; /* 0xef - digital port b mode */
u8 dpcm; /* 0xf0 - digital port c mode */
u8 dpdm; /* 0xf1 - digital port c mode */
u8 alfp; /* 0xf2 - active lfp */
u8 imon; /* 0xf3 - current graphics turbo imon value */
u8 mmio; /* 0xf4 - 64bit mmio support */
u8 unused[11];
u8 unused[76];
/* ChromeOS specific (0x100-0xfff)*/
chromeos_acpi_t chromeos;

22
src/soc/intel/braswell/acpi.c
View File

@@ -460,38 +460,16 @@ unsigned long acpi_madt_irq_overrides(unsigned long current)
return current;
}
/* Initialize IGD OpRegion, called from ACPI code */
static int update_igd_opregion(igd_opregion_t *opregion)
{
/* FIXME: Add platform specific mailbox initialization */
return 0;
}
unsigned long southcluster_write_acpi_tables(const struct device *device, unsigned long current,
struct acpi_rsdp *rsdp)
{
acpi_header_t *ssdt2;
global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!CONFIG(DISABLE_HPET)) {
current = acpi_write_hpet(device, current, rsdp);
current = acpi_align_current(current);
}
if (CONFIG(INTEL_GMA_ADD_VBT)) {
igd_opregion_t *opregion;
printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
opregion = (igd_opregion_t *)current;
intel_gma_init_igd_opregion(opregion);
if (gnvs)
gnvs->aslb = (u32)opregion;
update_igd_opregion(opregion);
current += sizeof(igd_opregion_t);
current = acpi_align_current(current);
}
ssdt2 = (acpi_header_t *)current;
memset(ssdt2, 0, sizeof(acpi_header_t));
acpi_create_serialio_ssdt(ssdt2);

42
src/soc/intel/braswell/acpi/globalnvs.asl
View File

@@ -55,48 +55,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
TOLM, 32, /* 0x34 - Top of Low Memory */
CBMC, 32, /* 0x38 - coreboot mem console pointer */
/* IGD OpRegion */
Offset (0xb4),
ASLB, 32, // 0xb4 - IGD OpRegion Base Address
IBTT, 8, // 0xb8 - IGD boot panel device
IPAT, 8, // 0xb9 - IGD panel type CMOS option
ITVF, 8, // 0xba - IGD TV format CMOS option
ITVM, 8, // 0xbb - IGD TV minor format option
IPSC, 8, // 0xbc - IGD panel scaling
IBLC, 8, // 0xbd - IGD BLC config
IBIA, 8, // 0xbe - IGD BIA config
ISSC, 8, // 0xbf - IGD SSC config
I409, 8, // 0xc0 - IGD 0409 modified settings
I509, 8, // 0xc1 - IGD 0509 modified settings
I609, 8, // 0xc2 - IGD 0609 modified settings
I709, 8, // 0xc3 - IGD 0709 modified settings
IDMM, 8, // 0xc4 - IGD Power conservation feature
IDMS, 8, // 0xc5 - IGD DVMT memory size
IF1E, 8, // 0xc6 - IGD function 1 enable
HVCO, 8, // 0xc7 - IGD HPLL VCO
NXD1, 32, // 0xc8 - IGD _DGS next DID1
NXD2, 32, // 0xcc - IGD _DGS next DID2
NXD3, 32, // 0xd0 - IGD _DGS next DID3
NXD4, 32, // 0xd4 - IGD _DGS next DID4
NXD5, 32, // 0xd8 - IGD _DGS next DID5
NXD6, 32, // 0xdc - IGD _DGS next DID6
NXD7, 32, // 0xe0 - IGD _DGS next DID7
NXD8, 32, // 0xe4 - IGD _DGS next DID8
ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI)
PAVP, 8, // 0xe9 - IGD PAVP data
Offset (0xeb),
OSCC, 8, // 0xeb - PCIe OSC control
NPCE, 8, // 0xec - native PCIe support
PLFL, 8, // 0xed - platform flavor
BREV, 8, // 0xee - board revision
DPBM, 8, // 0xef - digital port b mode
DPCM, 8, // 0xf0 - digital port c mode
DPDM, 8, // 0xf1 - digital port d mode
ALFP, 8, // 0xf2 - active lfp
IMON, 8, // 0xf3 - current graphics turbo imon value
MMIO, 8, // 0xf4 - 64bit mmio support
/* ChromeOS specific */
Offset (0x100),
#include <vendorcode/google/chromeos/acpi/gnvs.asl>

17
src/soc/intel/braswell/gfx.c
View File

@@ -9,7 +9,6 @@
#include <drivers/intel/gma/i915.h>
#include <reg_script.h>
#include <soc/gfx.h>
#include <soc/nvs.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
@@ -50,6 +49,8 @@ static void gfx_init(struct device *dev)
{
printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
intel_gma_init_igd_opregion();
if (!CONFIG(RUN_FSP_GOP)) {
/* Pre VBIOS Init */
gfx_pre_vbios_init(dev);
@@ -60,20 +61,6 @@ static void gfx_init(struct device *dev)
/* Post VBIOS Init */
gfx_post_vbios_init(dev);
}
intel_gma_restore_opregion();
}
uintptr_t gma_get_gnvs_aslb(const void *gnvs)
{
const global_nvs_t *gnvs_ptr = gnvs;
return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
}
void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
{
global_nvs_t *gnvs_ptr = gnvs;
if (gnvs_ptr)
gnvs_ptr->aslb = aslb;
}
static void gma_generate_ssdt(const struct device *dev)

35
src/soc/intel/braswell/include/soc/nvs.h
View File

@@ -48,40 +48,7 @@ typedef struct global_nvs_t {
u32 cbmc; /* 0x38 - coreboot memconsole */
u8 rsvd3[120]; /* 0x3c - 0xb3 - unused */
/* IGD OpRegion */
u32 aslb; /* 0xb4 - IGD OpRegion Base Address */
u8 ibtt; /* 0xb8 - IGD boot type */
u8 ipat; /* 0xb9 - IGD panel type */
u8 itvf; /* 0xba - IGD TV format */
u8 itvm; /* 0xbb - IGD TV minor format */
u8 ipsc; /* 0xbc - IGD Panel Scaling */
u8 iblc; /* 0xbd - IGD BLC configuration */
u8 ibia; /* 0xbe - IGD BIA configuration */
u8 issc; /* 0xbf - IGD SSC configuration */
u8 i409; /* 0xc0 - IGD 0409 modified settings */
u8 i509; /* 0xc1 - IGD 0509 modified settings */
u8 i609; /* 0xc2 - IGD 0609 modified settings */
u8 i709; /* 0xc3 - IGD 0709 modified settings */
u8 idmm; /* 0xc4 - IGD Power Conservation */
u8 idms; /* 0xc5 - IGD DVMT memory size */
u8 if1e; /* 0xc6 - IGD Function 1 Enable */
u8 hvco; /* 0xc7 - IGD HPLL VCO */
u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */
u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */
u8 pavp; /* 0xe9 - IGD PAVP data */
u8 rsvd12; /* 0xea - rsvd */
u8 oscc; /* 0xeb - PCIe OSC control */
u8 npce; /* 0xec - native PCIe support */
u8 plfl; /* 0xed - platform flavor */
u8 brev; /* 0xee - board revision */
u8 dpbm; /* 0xef - digital port b mode */
u8 dpcm; /* 0xf0 - digital port c mode */
u8 dpdm; /* 0xf1 - digital port c mode */
u8 alfp; /* 0xf2 - active lfp */
u8 imon; /* 0xf3 - current graphics turbo imon value */
u8 mmio; /* 0xf4 - 64bit mmio support */
u8 unused[11];
u8 unused[76];
/* ChromeOS specific (0x100-0xfff) */
chromeos_acpi_t chromeos;

42
src/soc/intel/broadwell/acpi/globalnvs.asl
View File

@@ -45,48 +45,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit
GPEI, 64, // 0x28 - 0x2f - GPE wake status bit
/* IGD OpRegion */
Offset (0xb4),
ASLB, 32, // 0xb4 - IGD OpRegion Base Address
IBTT, 8, // 0xb8 - IGD boot panel device
IPAT, 8, // 0xb9 - IGD panel type CMOS option
ITVF, 8, // 0xba - IGD TV format CMOS option
ITVM, 8, // 0xbb - IGD TV minor format option
IPSC, 8, // 0xbc - IGD panel scaling
IBLC, 8, // 0xbd - IGD BLC config
IBIA, 8, // 0xbe - IGD BIA config
ISSC, 8, // 0xbf - IGD SSC config
I409, 8, // 0xc0 - IGD 0409 modified settings
I509, 8, // 0xc1 - IGD 0509 modified settings
I609, 8, // 0xc2 - IGD 0609 modified settings
I709, 8, // 0xc3 - IGD 0709 modified settings
IDMM, 8, // 0xc4 - IGD Power conservation feature
IDMS, 8, // 0xc5 - IGD DVMT memory size
IF1E, 8, // 0xc6 - IGD function 1 enable
HVCO, 8, // 0xc7 - IGD HPLL VCO
NXD1, 32, // 0xc8 - IGD _DGS next DID1
NXD2, 32, // 0xcc - IGD _DGS next DID2
NXD3, 32, // 0xd0 - IGD _DGS next DID3
NXD4, 32, // 0xd4 - IGD _DGS next DID4
NXD5, 32, // 0xd8 - IGD _DGS next DID5
NXD6, 32, // 0xdc - IGD _DGS next DID6
NXD7, 32, // 0xe0 - IGD _DGS next DID7
NXD8, 32, // 0xe4 - IGD _DGS next DID8
ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI)
PAVP, 8, // 0xe9 - IGD PAVP data
Offset (0xeb),
OSCC, 8, // 0xeb - PCIe OSC control
NPCE, 8, // 0xec - native PCIe support
PLFL, 8, // 0xed - platform flavor
BREV, 8, // 0xee - board revision
DPBM, 8, // 0xef - digital port b mode
DPCM, 8, // 0xf0 - digital port c mode
DPDM, 8, // 0xf1 - digital port d mode
ALFP, 8, // 0xf2 - active lfp
IMON, 8, // 0xf3 - current graphics turbo imon value
MMIO, 8, // 0xf4 - 64bit mmio support
/* ChromeOS specific */
Offset (0x100),
#include <vendorcode/google/chromeos/acpi/gnvs.asl>

45
src/soc/intel/broadwell/igd.c
View File

@@ -11,13 +11,11 @@
#include <device/pci_ids.h>
#include <string.h>
#include <reg_script.h>
#include <cbmem.h>
#include <drivers/intel/gma/i915.h>
#include <drivers/intel/gma/i915_reg.h>
#include <drivers/intel/gma/libgfxinit.h>
#include <drivers/intel/gma/opregion.h>
#include <soc/cpu.h>
#include <soc/nvs.h>
#include <soc/pm.h>
#include <soc/ramstage.h>
#include <soc/systemagent.h>
@@ -491,24 +489,13 @@ static void igd_cdclk_init(struct device *dev, const int is_broadwell)
gtt_rmw(0x64810, 0xfffff800, dpdiv);
}
uintptr_t gma_get_gnvs_aslb(const void *gnvs)
{
const global_nvs_t *gnvs_ptr = gnvs;
return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
}
void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
{
global_nvs_t *gnvs_ptr = gnvs;
if (gnvs_ptr)
gnvs_ptr->aslb = aslb;
}
static void igd_init(struct device *dev)
{
int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT);
u32 rp1_gfx_freq;
intel_gma_init_igd_opregion();
/* IGD needs to be Bus Master */
u32 reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
@@ -586,33 +573,6 @@ static void igd_init(struct device *dev)
gma_gfxinit(&lightup_ok);
gfx_set_init_done(lightup_ok);
}
intel_gma_restore_opregion();
}
static unsigned long
gma_write_acpi_tables(const struct device *const dev, unsigned long current,
struct acpi_rsdp *const rsdp)
{
igd_opregion_t *opregion = (igd_opregion_t *)current;
global_nvs_t *gnvs;
if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
return current;
current += sizeof(igd_opregion_t);
/* GNVS has been already set up */
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (gnvs) {
/* IGD OpRegion Base Address */
gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion);
} else {
printk(BIOS_ERR, "Error: GNVS table not found.\n");
}
current = acpi_align_current(current);
return current;
}
static void gma_generate_ssdt(const struct device *dev)
@@ -628,7 +588,6 @@ static struct device_operations igd_ops = {
.enable_resources = &pci_dev_enable_resources,
.init = &igd_init,
.ops_pci = &broadwell_pci_ops,
.write_acpi_tables = gma_write_acpi_tables,
.acpi_fill_ssdt = gma_generate_ssdt,
};

35
src/soc/intel/broadwell/include/soc/nvs.h
View File

@@ -38,40 +38,7 @@ typedef struct global_nvs_t {
u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */
u8 unused1[132]; /* 0x30 - 0xb3 - unused */
/* IGD OpRegion */
u32 aslb; /* 0xb4 - IGD OpRegion Base Address */
u8 ibtt; /* 0xb8 - IGD boot type */
u8 ipat; /* 0xb9 - IGD panel type */
u8 itvf; /* 0xba - IGD TV format */
u8 itvm; /* 0xbb - IGD TV minor format */
u8 ipsc; /* 0xbc - IGD Panel Scaling */
u8 iblc; /* 0xbd - IGD BLC configuration */
u8 ibia; /* 0xbe - IGD BIA configuration */
u8 issc; /* 0xbf - IGD SSC configuration */
u8 i409; /* 0xc0 - IGD 0409 modified settings */
u8 i509; /* 0xc1 - IGD 0509 modified settings */
u8 i609; /* 0xc2 - IGD 0609 modified settings */
u8 i709; /* 0xc3 - IGD 0709 modified settings */
u8 idmm; /* 0xc4 - IGD Power Conservation */
u8 idms; /* 0xc5 - IGD DVMT memory size */
u8 if1e; /* 0xc6 - IGD Function 1 Enable */
u8 hvco; /* 0xc7 - IGD HPLL VCO */
u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */
u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */
u8 pavp; /* 0xe9 - IGD PAVP data */
u8 rsvd2; /* 0xea - rsvd */
u8 oscc; /* 0xeb - PCIe OSC control */
u8 npce; /* 0xec - native PCIe support */
u8 plfl; /* 0xed - platform flavor */
u8 brev; /* 0xee - board revision */
u8 dpbm; /* 0xef - digital port b mode */
u8 dpcm; /* 0xf0 - digital port c mode */
u8 dpdm; /* 0xf1 - digital port c mode */
u8 alfp; /* 0xf2 - active lfp */
u8 imon; /* 0xf3 - current graphics turbo imon value */
u8 mmio; /* 0xf4 - 64bit mmio support */
u8 unused2[11];
u8 unused2[76];
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;

18
src/soc/intel/cannonlake/graphics.c
View File

@@ -22,6 +22,8 @@ void graphics_soc_init(struct device *dev)
{
uint32_t ddi_buf_ctl;
intel_gma_init_igd_opregion();
/*
* Enable DDI-A (eDP) 4-lane operation if the link is not up yet.
* This will allow the kernel to use 4-lane eDP links properly
@@ -59,19 +61,3 @@ void graphics_soc_init(struct device *dev)
pci_dev_init(dev);
}
}
uintptr_t graphics_soc_write_acpi_opregion(const struct device *device,
uintptr_t current, struct acpi_rsdp *rsdp)
{
igd_opregion_t *opregion;
printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
opregion = (igd_opregion_t *)current;
if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
return current;
current += sizeof(igd_opregion_t);
return acpi_align_current(current);
}

1
src/soc/intel/common/block/graphics/graphics.c
View File

@@ -119,7 +119,6 @@ static const struct device_operations graphics_ops = {
.init = graphics_soc_init,
.ops_pci = &pci_dev_ops_pci,
#if CONFIG(HAVE_ACPI_TABLES)
.write_acpi_tables = graphics_soc_write_acpi_opregion,
.acpi_fill_ssdt = gma_generate_ssdt,
#endif
.scan_bus = scan_generic_bus,

14
src/soc/intel/common/block/include/intelblocks/graphics.h
View File

@@ -18,20 +18,6 @@
*/
void graphics_soc_init(struct device *dev);
/*
* Write ASL entry for Graphics opregion
* Input:
* struct device *device: device structure
* current: start address of graphics opregion
* rsdp: pointer to RSDT (and XSDT) structure
*
* Output:
* End address of graphics opregion so that the called
* can use the same for future calls to write_acpi_tables
*/
uintptr_t graphics_soc_write_acpi_opregion(const struct device *device,
uintptr_t current, struct acpi_rsdp *rsdp);
/* i915 controller info for ACPI backlight controls */
const struct i915_gpu_controller_info *
intel_igd_get_controller_info(const struct device *device);

19
src/soc/intel/icelake/graphics.c
View File

@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <acpi/acpi.h>
#include <console/console.h>
#include <fsp/util.h>
#include <device/device.h>
@@ -17,6 +16,8 @@ uintptr_t fsp_soc_get_igd_bar(void)
void graphics_soc_init(struct device *dev)
{
intel_gma_init_igd_opregion();
/*
* GFX PEIM module inside FSP binary is taking care of graphics
* initialization based on RUN_FSP_GOP Kconfig
@@ -37,19 +38,3 @@ void graphics_soc_init(struct device *dev)
/* Initialize PCI device, load/execute BIOS Option ROM */
pci_dev_init(dev);
}
uintptr_t graphics_soc_write_acpi_opregion(const struct device *device,
uintptr_t current, struct acpi_rsdp *rsdp)
{
igd_opregion_t *opregion;
printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
opregion = (igd_opregion_t *)current;
if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
return current;
current += sizeof(igd_opregion_t);
return acpi_align_current(current);
}

19
src/soc/intel/jasperlake/graphics.c
View File

@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <acpi/acpi.h>
#include <console/console.h>
#include <fsp/util.h>
#include <device/device.h>
@@ -17,6 +16,8 @@ uintptr_t fsp_soc_get_igd_bar(void)
void graphics_soc_init(struct device *dev)
{
intel_gma_init_igd_opregion();
/*
* GFX PEIM module inside FSP binary is taking care of graphics
* initialization based on RUN_FSP_GOP Kconfig
@@ -37,19 +38,3 @@ void graphics_soc_init(struct device *dev)
/* Initialize PCI device, load/execute BIOS Option ROM */
pci_dev_init(dev);
}
uintptr_t graphics_soc_write_acpi_opregion(const struct device *device,
uintptr_t current, struct acpi_rsdp *rsdp)
{
igd_opregion_t *opregion;
printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
opregion = (igd_opregion_t *)current;
if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
return current;
current += sizeof(igd_opregion_t);
return acpi_align_current(current);
}

42
src/soc/intel/skylake/acpi/globalnvs.asl
View File

@@ -58,48 +58,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
A4GB, 64, // 0x54 - 0x5B Base of above 4GB MMIO Resource
A4GS, 64, // 0x5C - 0x63 Length of above 4GB MMIO Resource
/* IGD OpRegion */
Offset (0xb4),
ASLB, 32, // 0xb4 - IGD OpRegion Base Address
IBTT, 8, // 0xb8 - IGD boot panel device
IPAT, 8, // 0xb9 - IGD panel type CMOS option
ITVF, 8, // 0xba - IGD TV format CMOS option
ITVM, 8, // 0xbb - IGD TV minor format option
IPSC, 8, // 0xbc - IGD panel scaling
IBLC, 8, // 0xbd - IGD BLC config
IBIA, 8, // 0xbe - IGD BIA config
ISSC, 8, // 0xbf - IGD SSC config
I409, 8, // 0xc0 - IGD 0409 modified settings
I509, 8, // 0xc1 - IGD 0509 modified settings
I609, 8, // 0xc2 - IGD 0609 modified settings
I709, 8, // 0xc3 - IGD 0709 modified settings
IDMM, 8, // 0xc4 - IGD Power conservation feature
IDMS, 8, // 0xc5 - IGD DVMT memory size
IF1E, 8, // 0xc6 - IGD function 1 enable
HVCO, 8, // 0xc7 - IGD HPLL VCO
NXD1, 32, // 0xc8 - IGD _DGS next DID1
NXD2, 32, // 0xcc - IGD _DGS next DID2
NXD3, 32, // 0xd0 - IGD _DGS next DID3
NXD4, 32, // 0xd4 - IGD _DGS next DID4
NXD5, 32, // 0xd8 - IGD _DGS next DID5
NXD6, 32, // 0xdc - IGD _DGS next DID6
NXD7, 32, // 0xe0 - IGD _DGS next DID7
NXD8, 32, // 0xe4 - IGD _DGS next DID8
ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI)
PAVP, 8, // 0xe9 - IGD PAVP data
Offset (0xeb),
OSCC, 8, // 0xeb - PCIe OSC control
NPCE, 8, // 0xec - native PCIe support
PLFL, 8, // 0xed - platform flavor
BREV, 8, // 0xee - board revision
DPBM, 8, // 0xef - digital port b mode
DPCM, 8, // 0xf0 - digital port c mode
DPDM, 8, // 0xf1 - digital port d mode
ALFP, 8, // 0xf2 - active lfp
IMON, 8, // 0xf3 - current graphics turbo imon value
MMIO, 8, // 0xf4 - 64bit mmio support
/* ChromeOS specific */
Offset (0x100),
#include <vendorcode/google/chromeos/acpi/gnvs.asl>

54
src/soc/intel/skylake/graphics.c
View File

@@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootmode.h>
#include <cbmem.h>
#include <commonlib/helpers.h>
#include <console/console.h>
#include <device/pci.h>
@@ -12,7 +11,6 @@
#include <drivers/intel/gma/libgfxinit.h>
#include <intelblocks/graphics.h>
#include <drivers/intel/gma/opregion.h>
#include <soc/nvs.h>
#include <soc/ramstage.h>
#include <types.h>
@@ -85,6 +83,8 @@ void graphics_soc_init(struct device *dev)
{
u32 ddi_buf_ctl;
intel_gma_init_igd_opregion();
graphics_setup_panel(dev);
/*
@@ -123,56 +123,6 @@ void graphics_soc_init(struct device *dev)
/* Initialize PCI device, load/execute BIOS Option ROM */
pci_dev_init(dev);
}
intel_gma_restore_opregion();
}
uintptr_t gma_get_gnvs_aslb(const void *gnvs)
{
const global_nvs_t *gnvs_ptr = gnvs;
return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
}
void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
{
global_nvs_t *gnvs_ptr = gnvs;
if (gnvs_ptr)
gnvs_ptr->aslb = aslb;
}
/* Initialize IGD OpRegion, called from ACPI code */
static void update_igd_opregion(igd_opregion_t *opregion)
{
/* FIXME: Add platform specific mailbox initialization */
}
uintptr_t graphics_soc_write_acpi_opregion(const struct device *device,
uintptr_t current, struct acpi_rsdp *rsdp)
{
igd_opregion_t *opregion;
global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
/* If GOP is not used, exit here */
if (!CONFIG(INTEL_GMA_ADD_VBT))
return current;
/* If IGD is disabled, exit here */
if (pci_read_config16(device, PCI_VENDOR_ID) == 0xFFFF)
return current;
printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
opregion = (igd_opregion_t *)current;
if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
return current;
if (gnvs)
gnvs->aslb = (u32)(uintptr_t)opregion;
update_igd_opregion(opregion);
current += sizeof(igd_opregion_t);
current = acpi_align_current(current);
printk(BIOS_DEBUG, "current = %lx\n", current);
return current;
}
const struct i915_gpu_controller_info *

37
src/soc/intel/skylake/include/soc/nvs.h
View File

@@ -47,42 +47,7 @@ typedef struct global_nvs_t {
u64 elng; /* 0x4C - 0x53 EPC Length */
u64 a4gb; /* 0x54 - 0x5B Base of above 4GB MMIO Resource */
u64 a4gs; /* 0x5C - 0x63 Length of above 4GB MMIO Resource */
u8 rsvd[80];
/* IGD OpRegion */
u32 aslb; /* 0xb4 - IGD OpRegion Base Address */
u8 ibtt; /* 0xb8 - IGD boot type */
u8 ipat; /* 0xb9 - IGD panel type */
u8 itvf; /* 0xba - IGD TV format */
u8 itvm; /* 0xbb - IGD TV minor format */
u8 ipsc; /* 0xbc - IGD Panel Scaling */
u8 iblc; /* 0xbd - IGD BLC configuration */
u8 ibia; /* 0xbe - IGD BIA configuration */
u8 issc; /* 0xbf - IGD SSC configuration */
u8 i409; /* 0xc0 - IGD 0409 modified settings */
u8 i509; /* 0xc1 - IGD 0509 modified settings */
u8 i609; /* 0xc2 - IGD 0609 modified settings */
u8 i709; /* 0xc3 - IGD 0709 modified settings */
u8 idmm; /* 0xc4 - IGD Power Conservation */
u8 idms; /* 0xc5 - IGD DVMT memory size */
u8 if1e; /* 0xc6 - IGD Function 1 Enable */
u8 hvco; /* 0xc7 - IGD HPLL VCO */
u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */
u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */
u8 pavp; /* 0xe9 - IGD PAVP data */
u8 rsvd12; /* 0xea - rsvd */
u8 oscc; /* 0xeb - PCIe OSC control */
u8 npce; /* 0xec - native PCIe support */
u8 plfl; /* 0xed - platform flavor */
u8 brev; /* 0xee - board revision */
u8 dpbm; /* 0xef - digital port b mode */
u8 dpcm; /* 0xf0 - digital port c mode */
u8 dpdm; /* 0xf1 - digital port c mode */
u8 alfp; /* 0xf2 - active lfp */
u8 imon; /* 0xf3 - current graphics turbo imon value */
u8 mmio; /* 0xf4 - 64bit mmio support */
u8 unused[11];
u8 rsvd[156];
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;

19
src/soc/intel/tigerlake/graphics.c
View File

@@ -6,7 +6,6 @@
* Chapter number: 4
*/
#include <acpi/acpi.h>
#include <console/console.h>
#include <fsp/util.h>
#include <device/device.h>
@@ -23,6 +22,8 @@ uintptr_t fsp_soc_get_igd_bar(void)
void graphics_soc_init(struct device *dev)
{
intel_gma_init_igd_opregion();
/*
* GFX PEIM module inside FSP binary is taking care of graphics
* initialization based on RUN_FSP_GOP Kconfig
@@ -43,19 +44,3 @@ void graphics_soc_init(struct device *dev)
/* Initialize PCI device, load/execute BIOS Option ROM */
pci_dev_init(dev);
}
uintptr_t graphics_soc_write_acpi_opregion(const struct device *device,
uintptr_t current, struct acpi_rsdp *rsdp)
{
igd_opregion_t *opregion;
printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
opregion = (igd_opregion_t *)current;
if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
return current;
current += sizeof(igd_opregion_t);
return acpi_align_current(current);
}