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mb/intel/archercity_crb: Fix build for specific configurations

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Guard OCP functions calls to allow builds without OCP drivers.

Change-Id: Ie9a82387366a8bb3387bcba3ec7a4c7f0100f78c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Patrick Rudolph 2024-04-19 09:05:04 +02:00 committed by Felix Held
parent 1f199f283d
commit f2ac23fb13
2 changed files with 18 additions and 15 deletions
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3
src/mainboard/intel/archercity_crb/romstage.c
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@ -11,6 +11,7 @@
void mainboard_ewl_check(void) void mainboard_ewl_check(void)
{ {
if (CONFIG(OCP_EWL))
get_ewl(); get_ewl();
} }
@ -36,6 +37,7 @@ static void mainboard_config_iio(FSPM_UPD *mupd)
void mainboard_memory_init_params(FSPM_UPD *mupd) void mainboard_memory_init_params(FSPM_UPD *mupd)
{ {
/* Setup FSP log */ /* Setup FSP log */
if (CONFIG(OCP_VPD)) {
mupd->FspmConfig.SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG, mupd->FspmConfig.SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG,
FSP_LOG_DEFAULT); FSP_LOG_DEFAULT);
if (mupd->FspmConfig.SerialIoUartDebugEnable) { if (mupd->FspmConfig.SerialIoUartDebugEnable) {
@ -51,6 +53,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
/* FSP Dfx PMIC Secure mode */ /* FSP Dfx PMIC Secure mode */
mupd->FspmConfig.DfxPmicSecureMode = get_int_from_vpd_range( mupd->FspmConfig.DfxPmicSecureMode = get_int_from_vpd_range(
FSP_PMIC_SECURE_MODE, FSP_PMIC_SECURE_MODE_DEFAULT, 0, 2); FSP_PMIC_SECURE_MODE, FSP_PMIC_SECURE_MODE_DEFAULT, 0, 2);
}
/* Set Rank Margin Tool to disable. */ /* Set Rank Margin Tool to disable. */
mupd->FspmConfig.EnableRMT = 0x0; mupd->FspmConfig.EnableRMT = 0x0;

2
src/mainboard/intel/archercity_crb/util.c
View File

@ -4,7 +4,7 @@
#include <soc/chip_common.h> #include <soc/chip_common.h>
#include <soc/util.h> #include <soc/util.h>
#if CONFIG(SOC_INTEL_HAS_CXL) #if CONFIG(SOC_INTEL_HAS_CXL) && CONFIG(OCP_VPD)
enum xeonsp_cxl_mode get_cxl_mode(void) enum xeonsp_cxl_mode get_cxl_mode(void)
{ {
int ocp_cxl_mode = get_cxl_mode_from_vpd(); int ocp_cxl_mode = get_cxl_mode_from_vpd();