mb/*/*: Drop AMDFAM10 mainboards
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: Ic00ca18de3d73a17041a3a2839307149ad7902b2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36961 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
committed by
Kyösti Mälkki
Kyösti Mälkki
parent
ad983eeec7
commit
f2e42c4a8e
@@ -1,96 +0,0 @@
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if BOARD_ASUS_KCMA_D8
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select CPU_AMD_SOCKET_C32_NON_AGESA
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select DIMM_DDR3
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select DIMM_REGISTERED
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# select QRANK_DIMM_SUPPORT
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select DIMM_VOLTAGE_SET_SUPPORT
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select NORTHBRIDGE_AMD_AMDFAM10
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select SOUTHBRIDGE_AMD_SR5650
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select SOUTHBRIDGE_AMD_SB700
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select SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA
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select SOUTHBRIDGE_AMD_SUBTYPE_SP5100
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select SUPERIO_WINBOND_W83667HG_A
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select PARALLEL_CPU_INIT
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select HAVE_ROMSTAGE_CONSOLE_SPINLOCK
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select HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
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select HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select HAVE_ACPI_TABLES
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select SB_HT_CHAIN_UNITID_OFFSET_ONLY
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select LIFT_BSP_APIC_ID
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select BOARD_ROMSIZE_KB_2048
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select ENABLE_APIC_EXT_ID
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select SPI_FLASH
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select DRIVERS_I2C_W83795
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select DRIVERS_ASPEED_AST2050
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select MAINBOARD_FORCE_NATIVE_VGA_INIT
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select POWER_STATE_DEFAULT_ON_AFTER_FAILURE
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config MAINBOARD_DIR
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string
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default "asus/kcma-d8"
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config BOOTBLOCK_MAINBOARD_INIT
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string
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default "mainboard/asus/kcma-d8/bootblock.c"
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config DCACHE_RAM_BASE
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hex
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default 0xc2000
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config DCACHE_RAM_SIZE
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hex
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default 0x1e000
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config APIC_ID_OFFSET
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hex
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default 0x0
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config MAINBOARD_PART_NUMBER
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string
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default "KCMA-D8"
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config HW_MEM_HOLE_SIZEK
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hex
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default 0x100000
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config MAX_CPUS
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int
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default 16
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# 1 (internal) processor per C32 socket
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config MAX_PHYSICAL_CPUS
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int
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default 2
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config HT_CHAIN_UNITID_BASE
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hex
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default 0x0
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x20
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config IRQ_SLOT_COUNT
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int
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default 13
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config SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD
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hex
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default 0x3f
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config ONBOARD_VGA_IS_PRIMARY
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bool
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default y
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config MAX_REBOOT_CNT
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int
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default 10
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endif # BOARD_ASUS_KCMA_D8
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@@ -1,2 +0,0 @@
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config BOARD_ASUS_KCMA_D8
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bool "KCMA-D8"
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@@ -1,16 +0,0 @@
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#
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# This file is part of the coreboot project.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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romstage-y += resourcemap.c
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ramstage-y += get_bus_conf.c
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@@ -1,368 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Raptor Engineering
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* Copyright (C) 2009 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Port 80 POST card debug */
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OperationRegion (DBG0, SystemIO, 0x80, One)
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Field (DBG0, ByteAcc, NoLock, Preserve) {
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DBG8, 8
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}
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/* SuperIO control port */
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Name (SPIO, 0x2E)
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/* SuperIO control map */
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OperationRegion (SPIM, SystemIO, SPIO, 0x02)
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Field (SPIM, ByteAcc, NoLock, Preserve) {
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INDX, 8,
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DATA, 8
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}
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/* SuperIO control registers */
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IndexField (INDX, DATA, ByteAcc, NoLock, Preserve) {
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Offset (0x07),
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CR07, 8, /* Logical device number */
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Offset (0x2C),
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CR2C, 8, /* GPIO3 multiplexed pin selection */
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Offset (0x30),
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CR30, 8, /* Logical device activation control register */
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Offset (0xE0),
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CRE0, 8, /* Wake control register */
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Offset (0xE4),
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CRE4, 8, /* Standby power control register */
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Offset (0xE6),
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CRE6, 8, /* Mouse wake event configuration register */
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Offset (0xF1),
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CRF1, 8, /* GPIO3 data register */
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Offset (0xF3),
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CRF3, 8, /* SUSLED mode register */
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Offset (0xF6),
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CRF6, 8, /* SMI/PME event generation control register */
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Offset (0xF9),
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CRF9, 8, /* ACPI PME configuration register */
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}
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/* Power Management I/O registers */
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OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
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Field(PIOR, ByteAcc, NoLock, Preserve) {
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PIOI, 0x00000008,
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PIOD, 0x00000008,
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}
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IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
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Offset(0x00), /* MiscControl */
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, 1,
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T1EE, 1,
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T2EE, 1,
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Offset(0x01), /* MiscStatus */
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, 1,
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T1E, 1,
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T2E, 1,
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Offset(0x04), /* SmiWakeUpEventEnable3 */
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, 7,
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SSEN, 1,
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Offset(0x07), /* SmiWakeUpEventStatus3 */
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, 7,
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CSSM, 1,
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Offset(0x10), /* AcpiEnable */
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, 6,
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PWDE, 1,
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Offset(0x1C), /* ProgramIoEnable */
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, 3,
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MKME, 1,
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IO3E, 1,
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IO2E, 1,
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IO1E, 1,
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IO0E, 1,
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Offset(0x1D), /* IOMonitorStatus */
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, 3,
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MKMS, 1,
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IO3S, 1,
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IO2S, 1,
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IO1S, 1,
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IO0S,1,
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Offset(0x20), /* AcpiPmEvtBlk */
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APEB, 16,
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Offset(0x36), /* GEvtLevelConfig */
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, 6,
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ELC6, 1,
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ELC7, 1,
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Offset(0x37), /* GPMLevelConfig0 */
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, 3,
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PLC0, 1,
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PLC1, 1,
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PLC2, 1,
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PLC3, 1,
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PLC8, 1,
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Offset(0x38), /* GPMLevelConfig1 */
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, 1,
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PLC4, 1,
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PLC5, 1,
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, 1,
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PLC6, 1,
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PLC7, 1,
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Offset(0x3B), /* PMEStatus1 */
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GP0S, 1,
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GM4S, 1,
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GM5S, 1,
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APS, 1,
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GM6S, 1,
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GM7S, 1,
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GP2S, 1,
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STSS, 1,
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Offset(0x55), /* SoftPciRst */
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SPRE, 1,
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, 1,
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, 1,
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PNAT, 1,
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PWMK, 1,
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PWNS, 1,
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/* Offset(0x61), */ /* Options_1 */
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/* ,7, */
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/* R617,1, */
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Offset(0x65), /* UsbPMControl */
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, 4,
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URRE, 1,
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, 2,
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BCDL, 1,
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Offset(0x68), /* MiscEnable68 */
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, 2,
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MAPC, 1,
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TMTE, 1,
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, 1,
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Offset(0x7C), /* MiscEnable7C */
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, 2,
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BLNK, 2,
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Offset(0x92), /* GEVENTIN */
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, 7,
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E7IS, 1,
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Offset(0x96), /* GPM98IN */
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G8IS, 1,
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G9IS, 1,
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Offset(0x9A), /* EnhanceControl */
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,7,
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HPDE, 1,
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Offset(0xA8), /* PIO7654Enable */
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IO4E, 1,
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IO5E, 1,
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IO6E, 1,
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IO7E, 1,
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Offset(0xA9), /* PIO7654Status */
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IO4S, 1,
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IO5S, 1,
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IO6S, 1,
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IO7S, 1,
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}
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/* PM1 Event Block
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* First word is PM1_Status, Second word is PM1_Enable
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*/
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OperationRegion(P1EB, SystemIO, APEB, 0x04)
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Field(P1EB, ByteAcc, NoLock, Preserve) {
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TMST, 1,
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, 3,
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BMST, 1,
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GBST, 1,
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Offset(0x01),
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PBST, 1,
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, 1,
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RTST, 1,
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, 3,
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PWST, 1,
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SPWS, 1,
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Offset(0x02),
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TMEN, 1,
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, 4,
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GBEN, 1,
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Offset(0x03),
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PBEN, 1,
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, 1,
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RTEN, 1,
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, 3,
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PWDA, 1,
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}
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/* Wake status package */
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Name(WKST,Package() {Zero, Zero})
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/*
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* \_WAK System Wake method
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*
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* Entry:
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* Arg0=The value of the sleeping state S1=1, S2=2
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*
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* Exit:
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* Return package of 2 DWords
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* Dword 1 - Status
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* 0x00000000 wake succeeded
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* 0x00000001 Wake was signaled but failed due to lack of power
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* 0x00000002 Wake was signaled but failed due to thermal condition
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* Dword 2 - Power Supply state
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* if non-zero the effective S-state the power supply entered
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*/
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Method(\_WAK, 1) {
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Store (0x20, DBG8)
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/* Set up LEDs */
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/* Set power LED to steady on */
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Store(0x0, BLNK)
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/* Configure SuperIO for wake */
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/* Access SuperIO ACPI device */
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Store(0x87, INDX)
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Store(0x87, INDX)
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Store(0x0A, CR07)
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if (LEqual(Arg0, One)) /* Resuming from power state S1 */
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{
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/* Deactivate the ACPI device */
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Store(Zero, CR30)
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/* Disable PS/2 SMI/PME events */
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And(CRF6, 0xCF, CRF6)
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}
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if (Lor(LEqual(Arg0, 0x03), LEqual(Arg0, 0x04))) /* Resuming from power state S3 or S4 */
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{
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/* Disable PS/2 wake */
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And(CRE0, 0x1D, CRE0)
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And(CRE6, 0x7F, CRE6)
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}
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/* Restore default SuperIO access */
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Store(0xAA, INDX)
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Store (0x21, DBG8)
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/* Re-enable HPET */
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Store(1, HPDE)
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/* Restore PCIRST# so it resets USB */
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if (LEqual(Arg0, 3)){
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Store(1, URRE)
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}
|
||||
|
||||
/* Configure southbridge for wake */
|
||||
/* Arbitrarily clear PciExpWakeStatus */
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Store(PWST, Local1)
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Store(Local1, PWST)
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Store (0x22, DBG8)
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Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
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||||
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Return(WKST)
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}
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|
||||
/*
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* \_PTS - Prepare to Sleep method
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*
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* Entry:
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* Arg0=The value of the sleeping state S1=1, S2=2, etc
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||||
*
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* Exit:
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* -none-
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*
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* The _PTS control method is executed at the beginning of the sleep process
|
||||
* for S1-S5. The sleeping value is passed to the _PTS control method. This
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* control method may be executed a relatively long time before entering the
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* sleep state and the OS may abort the operation without notification to
|
||||
* the ACPI driver. This method cannot modify the configuration or power
|
||||
* state of any device in the system.
|
||||
*/
|
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Method(\_PTS, 1) {
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Store (Arg0, DBG8)
|
||||
|
||||
/* Set up LEDs */
|
||||
if (LEqual(Arg0, One)) /* Power state S1 requested */
|
||||
{
|
||||
/* Set suspend LED to 0.25Hz toggle pulse with 50% duty cycle */
|
||||
Store(0x2, BLNK)
|
||||
}
|
||||
|
||||
/* Configure SuperIO for sleep */
|
||||
/* Access SuperIO ACPI device */
|
||||
Store(0x87, INDX)
|
||||
Store(0x87, INDX)
|
||||
Store(0x0A, CR07)
|
||||
|
||||
/* Disable PS/2 wakeup and connect PANSW_IN to PANSW_OUT */
|
||||
And(CRE0, 0x1F, CRE0)
|
||||
|
||||
if (LEqual(Arg0, One)) /* Power state S1 requested */
|
||||
{
|
||||
/* Activate the ACPI device */
|
||||
Store(One, CR30)
|
||||
|
||||
/* Disable SMI/PME events for:
|
||||
* LPT
|
||||
* FDC
|
||||
* UART
|
||||
*/
|
||||
Store(0x00, CRF6)
|
||||
|
||||
/* Enable PS/2 keyboard SMI/PME events */
|
||||
Or(CRF6, 0x10, CRF6)
|
||||
|
||||
/* Enable PS/2 keyboard wake */
|
||||
Or(CRE0, 0x40, CRE0)
|
||||
|
||||
/* Enable PS/2 mouse SMI/PME events */
|
||||
Or(CRF6, 0x20, CRF6)
|
||||
|
||||
/* Enable PS/2 mouse wake */
|
||||
Or(CRE0, 0x20, CRE0)
|
||||
} else {
|
||||
/* Enable PS/2 keyboard wake on any keypress */
|
||||
Or(CRE0, 0x41, CRE0)
|
||||
|
||||
/* Enable PS/2 mouse wake on any click */
|
||||
Or(CRE0, 0x22, CRE0)
|
||||
Or(CRE6, 0x80, CRE6)
|
||||
|
||||
if (LEqual(Arg0, 0x03)) /* Power state S3 requested */
|
||||
{
|
||||
/* Set VSBGATE# to provide standby power during S3 */
|
||||
Or(CRE4, 0x10, CRE4)
|
||||
}
|
||||
}
|
||||
|
||||
/* Restore default SuperIO access */
|
||||
Store(0xAA, INDX)
|
||||
|
||||
Store (0x10, DBG8)
|
||||
|
||||
/* Don't allow PCIRST# to reset USB */
|
||||
if (LEqual(Arg0, 3)){
|
||||
Store(0, URRE)
|
||||
}
|
||||
|
||||
/* Configure southbridge for sleep */
|
||||
/* Use bus clock for delay timebase */
|
||||
Store(0, BCDL)
|
||||
/* Defer APIC interrupts until first ACPI access */
|
||||
Store(One, MAPC)
|
||||
|
||||
/* On older chips, clear PciExpWakeDisEn */
|
||||
// if (LLessEqual(SBRI, 0x13)) {
|
||||
// Store(0, PWDE)
|
||||
// }
|
||||
|
||||
Store (0x11, DBG8)
|
||||
|
||||
/* Clear wake status structure. */
|
||||
Store(0, Index(WKST,0))
|
||||
Store(0, Index(WKST,1))
|
||||
}
|
||||
@@ -1,103 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
struct device *dev;
|
||||
u32 dword;
|
||||
u32 gsi_base = 0;
|
||||
uint32_t apicid_sp5100;
|
||||
uint32_t apicid_sr5650;
|
||||
/* create all subtables for processors */
|
||||
current = acpi_create_madt_lapics(current);
|
||||
|
||||
if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
|
||||
apicid_sp5100 = 0x0;
|
||||
else
|
||||
apicid_sp5100 = 0x20;
|
||||
apicid_sr5650 = apicid_sp5100 + 1;
|
||||
|
||||
/* Write SB700 IOAPIC, only one */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sp5100,
|
||||
IO_APIC_ADDR, gsi_base);
|
||||
/* IOAPIC on rs5690 */
|
||||
gsi_base += 24; /* SB700 has 24 IOAPIC entries. */
|
||||
dev = pcidev_on_root(0, 0);
|
||||
if (dev) {
|
||||
pci_write_config32(dev, 0xF8, 0x1);
|
||||
dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sr5650,
|
||||
dword, gsi_base);
|
||||
}
|
||||
|
||||
/* bus, source, gsirq, flags */
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 0, 2, 0);
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 9, 9, 0xf);
|
||||
|
||||
/* create all subtables for processors */
|
||||
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 0, 1);
|
||||
/* 1: LINT1 connect to NMI */
|
||||
|
||||
return current;
|
||||
}
|
||||
|
||||
unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current)
|
||||
{
|
||||
uint8_t *p;
|
||||
|
||||
uint32_t apicid_sp5100;
|
||||
uint32_t apicid_sr5650;
|
||||
|
||||
if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
|
||||
apicid_sp5100 = 0x0;
|
||||
else
|
||||
apicid_sp5100 = 0x20;
|
||||
apicid_sr5650 = apicid_sp5100 + 1;
|
||||
|
||||
/* Describe NB IOAPIC */
|
||||
p = (uint8_t *)current;
|
||||
p[0] = 0x48; /* Entry type */
|
||||
p[1] = 0; /* Device */
|
||||
p[2] = 0; /* Bus */
|
||||
p[3] = 0x0; /* Data */
|
||||
p[4] = apicid_sr5650; /* IOAPIC ID */
|
||||
p[5] = 0x1; /* Device 0 Function 1 */
|
||||
p[6] = 0x0; /* Northbridge bus */
|
||||
p[7] = 0x1; /* Variety */
|
||||
current += 8;
|
||||
|
||||
/* Describe SB IOAPIC */
|
||||
p = (uint8_t *)current;
|
||||
p[0] = 0x48; /* Entry type */
|
||||
p[1] = 0; /* Device */
|
||||
p[2] = 0; /* Bus */
|
||||
p[3] = 0xd7; /* Data */
|
||||
p[4] = apicid_sp5100; /* IOAPIC ID */
|
||||
p[5] = 0x14 << 3; /* Device 0x14 Function 0 */
|
||||
p[6] = 0x0; /* Southbridge bus */
|
||||
p[7] = 0x1; /* Variety */
|
||||
current += 8;
|
||||
|
||||
return current;
|
||||
}
|
||||
@@ -1,5 +0,0 @@
|
||||
Category: server
|
||||
ROM package: DIP-8
|
||||
ROM protocol: SPI
|
||||
ROM socketed: y
|
||||
Flashrom support: y
|
||||
@@ -1,52 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/pci_ops.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
|
||||
void bootblock_mainboard_init(void)
|
||||
{
|
||||
uint8_t recovery_enabled;
|
||||
unsigned char addr;
|
||||
unsigned char byte;
|
||||
|
||||
bootblock_northbridge_init();
|
||||
bootblock_southbridge_init();
|
||||
|
||||
/* Recovery jumper is connected to SP5100 GPIO61, and clears the GPIO when placed in the Recovery position */
|
||||
byte = pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x56);
|
||||
byte |= 0x1 << 4; /* Set GPIO61 to input mode */
|
||||
pci_io_write_config8(PCI_DEV(0, 0x14, 0), 0x56, byte);
|
||||
recovery_enabled = (!(pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x57) & 0x1));
|
||||
if (recovery_enabled) {
|
||||
#if CONFIG(USE_OPTION_TABLE)
|
||||
/* Clear NVRAM checksum */
|
||||
for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {
|
||||
cmos_write(0x0, addr);
|
||||
}
|
||||
|
||||
/* Set fallback boot */
|
||||
byte = cmos_read(RTC_BOOT_BYTE);
|
||||
byte &= 0xfc;
|
||||
cmos_write(byte, RTC_BOOT_BYTE);
|
||||
#else
|
||||
/* FIXME
|
||||
* Figure out how to recover if the option table is not available
|
||||
*/
|
||||
#endif
|
||||
}
|
||||
}
|
||||
@@ -1,29 +0,0 @@
|
||||
debug_level=Debug
|
||||
multi_core=Enable
|
||||
slow_cpu=off
|
||||
compute_unit_siblings=Enable
|
||||
iommu=Enable
|
||||
nmi=Disable
|
||||
hypertransport_speed_limit=Auto
|
||||
max_mem_clock=DDR3-1600
|
||||
minimum_memory_voltage=1.5V
|
||||
dimm_spd_checksum=Enforce
|
||||
ECC_memory=Enable
|
||||
ECC_redirection=Enable
|
||||
ecc_scrub_rate=1.28us
|
||||
interleave_chip_selects=Enable
|
||||
interleave_nodes=Disable
|
||||
interleave_memory_channels=Enable
|
||||
cpu_c_states=Enable
|
||||
cpu_cc6_state=Enable
|
||||
cpu_core_boost=Enable
|
||||
sata_ahci_mode=Enable
|
||||
sata_alpm=Disable
|
||||
maximum_p_state_limit=0xf
|
||||
probe_filter=Auto
|
||||
l3_cache_partitioning=Disable
|
||||
gart=Enable
|
||||
ehci_async_data_cache=Enable
|
||||
experimental_memory_speed_boost=Disable
|
||||
power_on_after_fail=On
|
||||
boot_option=Fallback
|
||||
@@ -1,149 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
## Copyright (C) 2007 AMD
|
||||
## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
entries
|
||||
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
393 3 r 0 unused
|
||||
#394 7 unused
|
||||
401 1 e 1 interleave_chip_selects
|
||||
402 1 e 1 interleave_nodes
|
||||
403 1 e 1 interleave_memory_channels
|
||||
404 4 e 8 max_mem_clock
|
||||
408 1 e 2 multi_core
|
||||
412 4 e 6 debug_level
|
||||
416 5 e 10 ecc_scrub_rate
|
||||
440 4 e 9 slow_cpu
|
||||
444 1 e 1 nmi
|
||||
445 1 e 1 gart
|
||||
446 2 e 3 power_on_after_fail
|
||||
456 1 e 1 ECC_memory
|
||||
457 1 e 1 ECC_redirection
|
||||
458 4 e 11 hypertransport_speed_limit
|
||||
462 2 e 12 minimum_memory_voltage
|
||||
464 1 e 2 compute_unit_siblings
|
||||
465 1 e 1 cpu_c_states
|
||||
466 1 e 1 cpu_cc6_state
|
||||
467 1 e 1 sata_ahci_mode
|
||||
468 1 e 1 sata_alpm
|
||||
#469 4 unused
|
||||
473 2 e 13 dimm_spd_checksum
|
||||
475 1 e 14 probe_filter
|
||||
476 1 e 1 l3_cache_partitioning
|
||||
478 1 e 1 iommu
|
||||
479 1 e 1 cpu_core_boost
|
||||
480 1 e 2 ehci_async_data_cache
|
||||
481 1 e 1 experimental_memory_speed_boost
|
||||
482 1 r 0 allow_spd_nvram_cache_restore
|
||||
483 4 h 0 maximum_p_state_limit
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
3 0 Off
|
||||
3 1 On
|
||||
3 2 Last
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
6 0 Emergency
|
||||
6 1 Alert
|
||||
6 2 Critical
|
||||
6 3 Error
|
||||
6 4 Warning
|
||||
6 5 Notice
|
||||
6 6 Information
|
||||
6 7 Debug
|
||||
6 8 Spew
|
||||
8 0 DDR3-1866
|
||||
8 1 DDR3-1600
|
||||
8 2 DDR3-1333
|
||||
8 3 DDR3-1066
|
||||
8 4 DDR3-800
|
||||
8 5 DDR3-667
|
||||
9 0 off
|
||||
9 1 87.5%
|
||||
9 2 75.0%
|
||||
9 3 62.5%
|
||||
9 4 50.0%
|
||||
9 5 37.5%
|
||||
9 6 25.0%
|
||||
9 7 12.5%
|
||||
10 0 Disabled
|
||||
10 1 40ns
|
||||
10 2 80ns
|
||||
10 3 160ns
|
||||
10 4 320ns
|
||||
10 5 640ns
|
||||
10 6 1.28us
|
||||
10 7 2.56us
|
||||
10 8 5.12us
|
||||
10 9 10.2us
|
||||
10 10 20.5us
|
||||
10 11 41us
|
||||
10 12 81.9us
|
||||
10 13 163.8us
|
||||
10 14 327.7us
|
||||
10 15 655.4us
|
||||
10 16 1.31ms
|
||||
10 17 2.62ms
|
||||
10 18 5.24ms
|
||||
10 19 10.49ms
|
||||
10 20 20.97ms
|
||||
10 21 42ms
|
||||
10 22 84ms
|
||||
11 0 Auto
|
||||
11 1 3.2GHz
|
||||
11 2 3.0GHz
|
||||
11 3 2.8GHz
|
||||
11 4 2.6GHz
|
||||
11 5 2.4GHz
|
||||
11 6 2.2GHz
|
||||
11 7 2.0GHz
|
||||
11 8 1.8GHz
|
||||
11 9 1.6GHz
|
||||
11 10 1.4GHz
|
||||
11 11 1.2GHz
|
||||
11 12 1.0GHz
|
||||
11 13 800MHz
|
||||
11 14 600MHz
|
||||
11 15 500MHz
|
||||
12 0 1.5V
|
||||
12 1 1.35V
|
||||
12 2 1.25V
|
||||
12 3 1.15V
|
||||
13 0 Enforce
|
||||
13 1 Ignore
|
||||
13 2 Override
|
||||
14 0 Disable
|
||||
14 1 Auto
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
@@ -1,239 +0,0 @@
|
||||
chip northbridge/amd/amdfam10/root_complex # Root complex
|
||||
device cpu_cluster 0 on # (L)APIC cluster
|
||||
chip cpu/amd/socket_F_1207 # CPU socket
|
||||
device lapic 0 on end # Local APIC of the CPU
|
||||
end
|
||||
end
|
||||
device domain 0 on # PCI domain
|
||||
subsystemid 0x1043 0x8163 inherit
|
||||
chip northbridge/amd/amdfam10 # Northbridge / RAM controller
|
||||
register "maximum_memory_capacity" = "0x2000000000" # 128GB
|
||||
device pci 18.0 on end # Link 0 == LDT 0
|
||||
device pci 18.0 on end # Link 1 == LDT 1
|
||||
device pci 18.0 on # Link 2 == LDT 2 [SB on link 2]
|
||||
chip southbridge/amd/sr5650 # Primary southbridge
|
||||
device pci 0.0 on end # HT Root Complex 0x9600
|
||||
device pci 0.1 on end # CLKCONFIG
|
||||
device pci 0.2 on end # IOMMU
|
||||
device pci 2.0 on # PCIE P2P bridge 0x9603 (GPP1 Port0)
|
||||
# Slot # PCI E 1 / PCI E 2
|
||||
end
|
||||
device pci 3.0 off end # PCIE P2P bridge 0x960b (GPP1 Port1)
|
||||
device pci 4.0 on # PCIE P2P bridge 0x9604 (GPP3a Port0)
|
||||
# PIKE SAS
|
||||
end
|
||||
device pci 5.0 off end # PCIE P2P bridge 0x9605 (GPP3a Port1)
|
||||
device pci 6.0 off end # PCIE P2P bridge 0x9606 (GPP3a Port2)
|
||||
device pci 7.0 off end # PCIE P2P bridge 0x9607 (GPP3a Port3)
|
||||
device pci 8.0 off end # NB/SB Link P2P bridge
|
||||
device pci 9.0 on # Bridge (GPP3a Port4)
|
||||
# Onboard # NIC A
|
||||
end
|
||||
device pci a.0 on # Bridge (GPP3a Port5)
|
||||
# Onboard # NIC B
|
||||
end
|
||||
device pci b.0 on # Bridge (GPP2 Port0)
|
||||
# Slot # PCI E 4
|
||||
end
|
||||
register "gpp1_configuration" = "0" # Configuration 16:0 default
|
||||
register "gpp2_configuration" = "1" # Configuration 8:8
|
||||
register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0
|
||||
register "port_enable" = "0x0f1c" # Enable all ports except 0, 1, 5, 6, and 7
|
||||
register "pcie_settling_time" = "1000000" # Allow PIKE to be detected / configured
|
||||
end
|
||||
chip southbridge/amd/sb700 # Secondary southbridge
|
||||
device pci 11.0 on end # SATA
|
||||
device pci 12.0 on end # USB
|
||||
device pci 12.1 on end # USB
|
||||
device pci 12.2 on end # USB
|
||||
device pci 13.0 on end # USB
|
||||
device pci 13.1 on end # USB
|
||||
device pci 13.2 on end # USB
|
||||
device pci 14.0 on # SM
|
||||
chip drivers/generic/generic # DIMM n-0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM n-0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM n-0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM n-0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM n-1-0-0
|
||||
device i2c 54 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM n-1-0-1
|
||||
device i2c 55 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM n-1-1-0
|
||||
device i2c 56 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM n-1-1-1
|
||||
device i2c 57 on end
|
||||
end
|
||||
chip drivers/i2c/w83795
|
||||
register "fanin_ctl1" = "0xff" # Enable monitoring of FANIN1 - FANIN8
|
||||
register "fanin_ctl2" = "0x00" # Connect FANIN11 - FANIN14 to alternate functions
|
||||
register "temp_ctl1" = "0x2a" # Enable monitoring of DTS, VSEN12, and VSEN13
|
||||
register "temp_ctl2" = "0x01" # Enable monitoring of TD1/TR1
|
||||
register "temp_dtse" = "0x03" # Enable DTS1 and DTS2
|
||||
register "volt_ctl1" = "0xff" # Enable monitoring of VSEN1 - VSEN8
|
||||
register "volt_ctl2" = "0xf7" # Enable monitoring of VSEN9 - VSEN11, 3VDD, 3VSB, and VBAT
|
||||
register "temp1_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp1)
|
||||
register "temp2_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp2)
|
||||
register "temp3_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp3)
|
||||
register "temp4_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp4)
|
||||
register "temp5_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp5)
|
||||
register "temp6_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp6)
|
||||
register "temp1_source_select" = "0x00" # Use TD1/TR1 as data source for Temp1
|
||||
register "temp2_source_select" = "0x00" # Use TD2/TR2 as data source for Temp2
|
||||
register "temp3_source_select" = "0x00" # Use TD3/TR3 as data source for Temp3
|
||||
register "temp4_source_select" = "0x00" # Use TD4/TR4 as data source for Temp4
|
||||
register "temp5_source_select" = "0x00" # Use TR5 as data source for Temp5
|
||||
register "temp6_source_select" = "0x00" # Use TR6 as data source for Temp6
|
||||
register "tr1_critical_temperature" = "85" # Set TD1/TR1 critical temperature to 85°C
|
||||
register "tr1_critical_hysteresis" = "80" # Set TD1/TR1 critical hysteresis temperature to 80°C
|
||||
register "tr1_warning_temperature" = "70" # Set TD1/TR1 warning temperature to 70°C
|
||||
register "tr1_warning_hysteresis" = "65" # Set TD1/TR1 warning hysteresis temperature to 65°C
|
||||
register "dts_critical_temperature" = "85" # Set DTS (CPU) critical temperature to 85°C
|
||||
register "dts_critical_hysteresis" = "80" # Set DTS (CPU) critical hysteresis temperature to 80°C
|
||||
register "dts_warning_temperature" = "70" # Set DTS (CPU) warning temperature to 70°C
|
||||
register "dts_warning_hysteresis" = "65" # Set DTS (CPU) warning hysteresis temperature to 65°C
|
||||
register "temp1_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C
|
||||
register "temp2_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C
|
||||
register "temp3_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C
|
||||
register "temp4_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C
|
||||
register "temp5_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C
|
||||
register "temp6_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C
|
||||
register "temp1_target_temperature" = "80" # Set Temp1 target temperature to 80°C
|
||||
register "temp2_target_temperature" = "80" # Set Temp1 target temperature to 80°C
|
||||
register "temp3_target_temperature" = "80" # Set Temp1 target temperature to 80°C
|
||||
register "temp4_target_temperature" = "80" # Set Temp1 target temperature to 80°C
|
||||
register "temp5_target_temperature" = "80" # Set Temp1 target temperature to 80°C
|
||||
register "temp6_target_temperature" = "80" # Set Temp1 target temperature to 80°C
|
||||
register "fan1_nonstop" = "7" # Set Fan 1 minimum speed
|
||||
register "fan2_nonstop" = "7" # Set Fan 2 minimum speed
|
||||
register "fan3_nonstop" = "7" # Set Fan 3 minimum speed
|
||||
register "fan4_nonstop" = "7" # Set Fan 4 minimum speed
|
||||
register "fan5_nonstop" = "7" # Set Fan 5 minimum speed
|
||||
register "fan6_nonstop" = "7" # Set Fan 6 minimum speed
|
||||
register "fan7_nonstop" = "7" # Set Fan 7 minimum speed
|
||||
register "fan8_nonstop" = "7" # Set Fan 8 minimum speed
|
||||
register "default_speed" = "100" # All fans to full speed on power up
|
||||
register "fan1_duty" = "100" # Fan 1 to full speed
|
||||
register "fan2_duty" = "100" # Fan 2 to full speed
|
||||
register "fan3_duty" = "100" # Fan 3 to full speed
|
||||
register "fan4_duty" = "100" # Fan 4 to full speed
|
||||
register "fan5_duty" = "100" # Fan 5 to full speed
|
||||
register "fan6_duty" = "100" # Fan 6 to full speed
|
||||
register "fan7_duty" = "100" # Fan 7 to full speed
|
||||
register "fan8_duty" = "100" # Fan 8 to full speed
|
||||
register "vcore1_high_limit_mv" = "1500" # VCORE1 (Node 0) high limit to 1.5V
|
||||
register "vcore1_low_limit_mv" = "900" # VCORE1 (Node 0) low limit to 0.9V
|
||||
register "vcore2_high_limit_mv" = "1500" # VCORE2 (Node 1) high limit to 1.5V
|
||||
register "vcore2_low_limit_mv" = "900" # VCORE2 (Node 1) low limit to 0.9V
|
||||
register "vsen3_high_limit_mv" = "1600" # VSEN1 (Node 0 RAM voltage) high limit to 1.6V
|
||||
register "vsen3_low_limit_mv" = "1100" # VSEN1 (Node 0 RAM voltage) low limit to 1.1V
|
||||
register "vsen4_high_limit_mv" = "1600" # VSEN2 (Node 1 RAM voltage) high limit to 1.6V
|
||||
register "vsen4_low_limit_mv" = "1100" # VSEN2 (Node 1 RAM voltage) low limit to 1.1V
|
||||
register "vsen5_high_limit_mv" = "1250" # VSEN5 (Node 0 HT link voltage) high limit to 1.25V
|
||||
register "vsen5_low_limit_mv" = "1150" # VSEN5 (Node 0 HT link voltage) low limit to 1.15V
|
||||
register "vsen6_high_limit_mv" = "1250" # VSEN6 (Node 1 HT link voltage) high limit to 1.25V
|
||||
register "vsen6_low_limit_mv" = "1150" # VSEN6 (Node 1 HT link voltage) low limit to 1.15V
|
||||
register "vsen7_high_limit_mv" = "1150" # VSEN7 (Northbridge core voltage) high limit to 1.15V
|
||||
register "vsen7_low_limit_mv" = "1050" # VSEN7 (Northbridge core voltage) low limit to 1.05V
|
||||
register "vsen8_high_limit_mv" = "1900" # VSEN8 (+1.8V) high limit to 1.9V
|
||||
register "vsen8_low_limit_mv" = "1700" # VSEN8 (+1.8V) low limit to 1.7V
|
||||
register "vsen9_high_limit_mv" = "1250" # VSEN9 (+1.2V) high limit to 1.25V
|
||||
register "vsen9_low_limit_mv" = "1150" # VSEN9 (+1.2V) low limit to 1.15V
|
||||
register "vsen10_high_limit_mv" = "1150" # VSEN10 (+1.1V) high limit to 1.15V
|
||||
register "vsen10_low_limit_mv" = "1050" # VSEN10 (+1.1V) low limit to 1.05V
|
||||
register "vsen11_high_limit_mv" = "1625" # VSEN11 (5VSB, scaling factor ~3.2) high limit to 5.2V
|
||||
register "vsen11_low_limit_mv" = "1500" # VSEN11 (5VSB, scaling factor ~3.2) low limit to 4.8V
|
||||
register "vsen12_high_limit_mv" = "1083" # VSEN12 (+12V, scaling factor ~12) high limit to 13V
|
||||
register "vsen12_low_limit_mv" = "917" # VSEN12 (+12V, scaling factor ~12) low limit to 11V
|
||||
register "vsen13_high_limit_mv" = "1625" # VSEN13 (+5V, scaling factor ~3.2) high limit to 5.2V
|
||||
register "vsen13_low_limit_mv" = "1500" # VSEN13 (+5V, scaling factor ~3.2) low limit to 4.8V
|
||||
register "vdd_high_limit_mv" = "3500" # 3VDD high limit to 3.5V
|
||||
register "vdd_low_limit_mv" = "3100" # 3VDD low limit to 3.1V
|
||||
register "vsb_high_limit_mv" = "3500" # 3VSB high limit to 3.5V
|
||||
register "vsb_low_limit_mv" = "3100" # 3VSB low limit to 3.1V
|
||||
register "vbat_high_limit_mv" = "3500" # VBAT (+3V) high limit to 3.5V
|
||||
register "vbat_low_limit_mv" = "2500" # VBAT (+3V) low limit to 2.5V
|
||||
register "smbus_aux" = "1" # Device located on auxiliary SMBUS controller
|
||||
device i2c 0x2f on end
|
||||
end
|
||||
end
|
||||
device pci 14.1 on end # IDE 0x439c
|
||||
device pci 14.2 on end # HDA 0x4383 (ASUS MIO add-on card)
|
||||
device pci 14.3 on # LPC 0x439d (SMBUS primary controller)
|
||||
chip superio/winbond/w83667hg-a # Super I/O
|
||||
device pnp 2e.0 off end # FDC; Not available on the KCMA-D8
|
||||
device pnp 2e.1 off end # LPT1; Not available on the KCMA-D8
|
||||
device pnp 2e.2 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 on # COM2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.5 on # PS/2 keyboard & mouse
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.106 off end # SPI: Not available on the KCMA-D8
|
||||
device pnp 2e.107 off end # GIPO6
|
||||
device pnp 2e.207 off end # GIPO7
|
||||
device pnp 2e.307 off end # GIPO8
|
||||
device pnp 2e.407 off end # GIPO9
|
||||
device pnp 2e.8 off end # WDT
|
||||
device pnp 2e.108 off end # GPIO 1
|
||||
device pnp 2e.9 off end # GPIO2
|
||||
device pnp 2e.109 off end # GPIO3
|
||||
device pnp 2e.209 off end # GPIO4
|
||||
device pnp 2e.309 off end # GPIO5
|
||||
device pnp 2e.a on end # ACPI
|
||||
device pnp 2e.b on # HW Monitor
|
||||
io 0x60 = 0x290
|
||||
# IRQ purposefully not assigned to prevent lockups
|
||||
end
|
||||
device pnp 2e.c off end # PECI
|
||||
device pnp 2e.d off end # VID_BUSSEL
|
||||
device pnp 2e.f off end # GPIO_PP_OD
|
||||
end
|
||||
end
|
||||
device pci 14.4 on # Bridge
|
||||
device pci 1.0 on # Slot
|
||||
# Slot # PCI 0
|
||||
end
|
||||
device pci 2.0 on # Slot
|
||||
# Slot # PCI 1
|
||||
end
|
||||
device pci 3.0 on # Slot
|
||||
# Slot # PCI 2
|
||||
end
|
||||
device pci 5.0 on end # VGA
|
||||
end
|
||||
device pci 14.5 on end # USB OHCI2 0x4399
|
||||
end
|
||||
end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
device pci 18.4 on end
|
||||
device pci 18.5 on end
|
||||
device pci 19.0 on end # Socket 1 node 0
|
||||
device pci 19.1 on end
|
||||
device pci 19.2 on end
|
||||
device pci 19.3 on end
|
||||
device pci 19.4 on end
|
||||
device pci 19.5 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
@@ -1,769 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Raptor Engineering
|
||||
* Copyright (C) 2005 - 2012 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
|
||||
* Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING: Sleep/Wake is a work in progress and is still somewhat flaky!
|
||||
* Everything else does to the best of my knowledge... (T.P. 01/26/2015)
|
||||
*/
|
||||
|
||||
/*
|
||||
* ISA portions taken from QEMU acpi-dsdt.dsl.
|
||||
*/
|
||||
|
||||
/*
|
||||
* PCI link routing templates taken from ck804.asl and modified for this board
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock (
|
||||
"DSDT.AML", /* Output filename */
|
||||
"DSDT", /* Signature */
|
||||
0x02, /* DSDT Revision, needs to be 2 or higher for 64bit */
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x00000001 /* OEM Revision */
|
||||
)
|
||||
{
|
||||
#include <northbridge/amd/amdfam10/amdfam10_util.asl>
|
||||
#include <southbridge/amd/sr5650/acpi/sr5650.asl>
|
||||
|
||||
/* Some global data */
|
||||
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
|
||||
Name(OSV, Ones) /* Assume nothing */
|
||||
Name(PICM, One) /* Assume APIC */
|
||||
|
||||
/* HPET enable */
|
||||
Name (HPTE, 0x1)
|
||||
|
||||
#include <southbridge/amd/common/acpi/sleepstates.asl>
|
||||
|
||||
/* The _PIC method is called by the OS to choose between interrupt
|
||||
* routing via the i8259 interrupt controller or the APIC.
|
||||
*
|
||||
* _PIC is called with a parameter of 0 for i8259 configuration and
|
||||
* with a parameter of 1 for Local Apic/IOAPIC configuration.
|
||||
*/
|
||||
Method (_PIC, 1, Serialized) {
|
||||
If (Arg0)
|
||||
{
|
||||
\_SB.CIRQ()
|
||||
}
|
||||
Store (Arg0, PICM)
|
||||
}
|
||||
|
||||
/* _PR CPU0 is dynamically supplied by SSDT */
|
||||
/* CPU objects and _PSS entries are dynamically supplied by SSDT */
|
||||
|
||||
Scope(\_GPE) { /* Start Scope GPE */
|
||||
/* General event 3 */
|
||||
Method(_L03) {
|
||||
/* Level-Triggered GPE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* General event 4 */
|
||||
Method(_L04) {
|
||||
/* Level-Triggered GPE */
|
||||
Notify (\_SB.PCI0.PBR0, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* Keyboard controller PME# */
|
||||
Method(_L08) {
|
||||
/* Level-Triggered GPE */
|
||||
Notify(\_SB.PCI0.LPC.PS2K, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.LPC.PS2M, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* USB controller PME# */
|
||||
Method(_L0B) {
|
||||
/* Level-Triggered GPE */
|
||||
Notify (\_SB.PCI0.USB0, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PCI0.USB1, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PCI0.USB2, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PCI0.USB3, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PCI0.USB4, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PCI0.USB5, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PCI0.USB6, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* GPIO0 or GEvent8 event */
|
||||
Method(_L18) {
|
||||
/* Level-Triggered GPE */
|
||||
Notify (\_SB.PCI0.PCE1, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PCI0.NICA, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PCI0.NICB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PCI0.PCE4, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
} /* End Scope GPE */
|
||||
|
||||
/* Root of the bus hierarchy */
|
||||
Scope (\_SB)
|
||||
{
|
||||
/* Top southbridge PCI device (SR5670 + SP5100) */
|
||||
Device (PCI0)
|
||||
{
|
||||
/* BUS0 root bus */
|
||||
|
||||
Name (_HID, EisaId ("PNP0A08")) /* PCI-e root bus (SR5670) */
|
||||
Name (_CID, EisaId ("PNP0A03")) /* PCI root bus (SP5100) */
|
||||
Name (_ADR, 0x00180001)
|
||||
Name (_UID, 0x00)
|
||||
|
||||
Name (HCIN, 0x00) // HC1
|
||||
|
||||
Method (_BBN, 0, NotSerialized)
|
||||
{
|
||||
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
|
||||
}
|
||||
|
||||
/* Operating System Capabilities Method */
|
||||
Method(_OSC,4)
|
||||
{
|
||||
/* Let OS control everything */
|
||||
Return (Arg3)
|
||||
}
|
||||
|
||||
External (BUSN)
|
||||
External (MMIO)
|
||||
External (PCIO)
|
||||
External (SBLK)
|
||||
External (TOM1)
|
||||
External (HCLK)
|
||||
External (SBDN)
|
||||
External (HCDN)
|
||||
External (CBST)
|
||||
|
||||
/* PCI Routing Tables */
|
||||
Name (PR00, Package () {
|
||||
/* PIC */
|
||||
/* Top southbridge device (SR5670) */
|
||||
/* HT Link */
|
||||
Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 },
|
||||
|
||||
/* PCI-E Slot 1 (Bridge) */
|
||||
Package (0x04) { 0x0002FFFF, 0x00, LNKE, 0x00 },
|
||||
|
||||
/* NIC A (Bridge) */
|
||||
Package (0x04) { 0x0009FFFF, 0x00, LNKF, 0x00 },
|
||||
|
||||
/* NIC B (Bridge) */
|
||||
Package (0x04) { 0x000AFFFF, 0x00, LNKG, 0x00 },
|
||||
|
||||
/* PCI-E Slot 4 (Bridge) */
|
||||
Package (0x04) { 0x000BFFFF, 0x00, LNKG, 0x00 },
|
||||
|
||||
/* Bottom southbridge device (SP5100) */
|
||||
/* SATA 0 */
|
||||
Package (0x04) { 0x0011FFFF, 0x00, LNKG, 0x00 },
|
||||
|
||||
/* USB 0 */
|
||||
Package (0x04) { 0x0012FFFF, 0x00, LNKA, 0x00 },
|
||||
Package (0x04) { 0x0012FFFF, 0x01, LNKB, 0x00 },
|
||||
Package (0x04) { 0x0012FFFF, 0x02, LNKC, 0x00 },
|
||||
Package (0x04) { 0x0012FFFF, 0x03, LNKD, 0x00 },
|
||||
|
||||
/* USB 1 */
|
||||
Package (0x04) { 0x0013FFFF, 0x00, LNKC, 0x00 },
|
||||
Package (0x04) { 0x0013FFFF, 0x01, LNKD, 0x00 },
|
||||
Package (0x04) { 0x0013FFFF, 0x02, LNKA, 0x00 },
|
||||
Package (0x04) { 0x0013FFFF, 0x03, LNKB, 0x00 },
|
||||
|
||||
/* SMBUS / IDE / LPC / VGA / PCI Slots 0 - 2 */
|
||||
Package (0x04) { 0x0014FFFF, 0x00, LNKA, 0x00 },
|
||||
Package (0x04) { 0x0014FFFF, 0x01, LNKB, 0x00 },
|
||||
Package (0x04) { 0x0014FFFF, 0x02, LNKC, 0x00 },
|
||||
Package (0x04) { 0x0014FFFF, 0x03, LNKD, 0x00 },
|
||||
})
|
||||
|
||||
Name (AR00, Package () {
|
||||
/* APIC */
|
||||
/* Top southbridge device (SR5670) */
|
||||
/* HT Link */
|
||||
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 55 },
|
||||
|
||||
/* PCI-E Slot 1 (Bridge) */
|
||||
Package (0x04) { 0x0002FFFF, 0x00, 0x00, 52 },
|
||||
|
||||
/* NIC A (Bridge) */
|
||||
Package (0x04) { 0x0009FFFF, 0x00, 0x00, 53 },
|
||||
|
||||
/* NIC B (Bridge) */
|
||||
Package (0x04) { 0x000AFFFF, 0x00, 0x00, 54 },
|
||||
|
||||
/* PCI-E Slot 4 (Bridge) */
|
||||
Package (0x04) { 0x000BFFFF, 0x00, 0x00, 54 },
|
||||
|
||||
/* Bottom southbridge device (SP5100) */
|
||||
/* SATA 0 */
|
||||
Package (0x04) { 0x0011FFFF, 0x00, 0x00, 22 },
|
||||
|
||||
/* USB 0 */
|
||||
Package (0x04) { 0x0012FFFF, 0x00, 0x00, 16 },
|
||||
Package (0x04) { 0x0012FFFF, 0x01, 0x00, 17 },
|
||||
Package (0x04) { 0x0012FFFF, 0x02, 0x00, 18 },
|
||||
Package (0x04) { 0x0012FFFF, 0x03, 0x00, 19 },
|
||||
|
||||
/* USB 1 */
|
||||
Package (0x04) { 0x0013FFFF, 0x00, 0x00, 18 },
|
||||
Package (0x04) { 0x0013FFFF, 0x01, 0x00, 19 },
|
||||
Package (0x04) { 0x0013FFFF, 0x02, 0x00, 16 },
|
||||
Package (0x04) { 0x0013FFFF, 0x03, 0x00, 17 },
|
||||
|
||||
/* SMBUS / IDE / LPC / VGA / PCI Slots 0 - 2 */
|
||||
Package (0x04) { 0x0014FFFF, 0x00, 0x00, 16 },
|
||||
Package (0x04) { 0x0014FFFF, 0x01, 0x00, 17 },
|
||||
Package (0x04) { 0x0014FFFF, 0x02, 0x00, 18 },
|
||||
Package (0x04) { 0x0014FFFF, 0x03, 0x00, 19 },
|
||||
})
|
||||
|
||||
Name (PR01, Package () {
|
||||
/* PIC */
|
||||
Package (0x04) { 0x1FFFF, 0x00, LNKE, 0x00 },
|
||||
Package (0x04) { 0x1FFFF, 0x01, LNKF, 0x00 },
|
||||
Package (0x04) { 0x1FFFF, 0x02, LNKG, 0x00 },
|
||||
Package (0x04) { 0x1FFFF, 0x03, LNKH, 0x00 },
|
||||
Package (0x04) { 0x2FFFF, 0x00, LNKF, 0x00 },
|
||||
Package (0x04) { 0x2FFFF, 0x01, LNKG, 0x00 },
|
||||
Package (0x04) { 0x2FFFF, 0x02, LNKH, 0x00 },
|
||||
Package (0x04) { 0x2FFFF, 0x03, LNKE, 0x00 },
|
||||
Package (0x04) { 0x3FFFF, 0x00, LNKG, 0x00 },
|
||||
Package (0x04) { 0x3FFFF, 0x01, LNKH, 0x00 },
|
||||
Package (0x04) { 0x3FFFF, 0x02, LNKE, 0x00 },
|
||||
Package (0x04) { 0x3FFFF, 0x03, LNKF, 0x00 },
|
||||
Package (0x04) { 0x5FFFF, 0x00, LNKH, 0x00 },
|
||||
})
|
||||
|
||||
Name (AR01, Package () {
|
||||
/* APIC */
|
||||
Package (0x04) { 0x1FFFF, 0x00, 0x00, 20 },
|
||||
Package (0x04) { 0x1FFFF, 0x01, 0x00, 21 },
|
||||
Package (0x04) { 0x1FFFF, 0x02, 0x00, 22 },
|
||||
Package (0x04) { 0x1FFFF, 0x03, 0x00, 23 },
|
||||
Package (0x04) { 0x2FFFF, 0x00, 0x00, 21 },
|
||||
Package (0x04) { 0x2FFFF, 0x01, 0x00, 22 },
|
||||
Package (0x04) { 0x2FFFF, 0x02, 0x00, 23 },
|
||||
Package (0x04) { 0x2FFFF, 0x03, 0x00, 20 },
|
||||
Package (0x04) { 0x3FFFF, 0x00, 0x00, 22 },
|
||||
Package (0x04) { 0x3FFFF, 0x01, 0x00, 23 },
|
||||
Package (0x04) { 0x3FFFF, 0x02, 0x00, 20 },
|
||||
Package (0x04) { 0x3FFFF, 0x03, 0x00, 21 },
|
||||
Package (0x04) { 0x5FFFF, 0x00, 0x00, 23 },
|
||||
})
|
||||
|
||||
Name (PR02, Package () {
|
||||
/* PIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 },
|
||||
})
|
||||
|
||||
Name (AR02, Package () {
|
||||
/* APIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, 0x00, 24 },
|
||||
Package (0x04) { 0xFFFF, 0x01, 0x00, 25 },
|
||||
Package (0x04) { 0xFFFF, 0x02, 0x00, 26 },
|
||||
Package (0x04) { 0xFFFF, 0x03, 0x00, 27 },
|
||||
})
|
||||
|
||||
Name (PR03, Package () {
|
||||
/* PIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, LNKE, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x01, LNKF, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x02, LNKG, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x03, LNKH, 0x00 },
|
||||
})
|
||||
|
||||
Name (AR03, Package () {
|
||||
/* APIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, 0x00, 44 },
|
||||
Package (0x04) { 0xFFFF, 0x01, 0x00, 45 },
|
||||
Package (0x04) { 0xFFFF, 0x02, 0x00, 46 },
|
||||
Package (0x04) { 0xFFFF, 0x03, 0x00, 47 },
|
||||
})
|
||||
|
||||
Name (PR04, Package () {
|
||||
/* PIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 },
|
||||
})
|
||||
|
||||
Name (AR04, Package () {
|
||||
/* APIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, 0x00, 48 },
|
||||
Package (0x04) { 0xFFFF, 0x01, 0x00, 49 },
|
||||
Package (0x04) { 0xFFFF, 0x02, 0x00, 50 },
|
||||
Package (0x04) { 0xFFFF, 0x03, 0x00, 51 },
|
||||
})
|
||||
|
||||
Name (PR05, Package () {
|
||||
/* PIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, LNKH, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x01, LNKE, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x02, LNKF, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x03, LNKG, 0x00 },
|
||||
})
|
||||
|
||||
Name (AR05, Package () {
|
||||
/* APIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, 0x00, 47 },
|
||||
Package (0x04) { 0xFFFF, 0x01, 0x00, 44 },
|
||||
Package (0x04) { 0xFFFF, 0x02, 0x00, 45 },
|
||||
Package (0x04) { 0xFFFF, 0x03, 0x00, 46 },
|
||||
})
|
||||
|
||||
Name (PR06, Package () {
|
||||
/* PIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 },
|
||||
})
|
||||
|
||||
Name (AR06, Package () {
|
||||
/* APIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, 0x00, 32 },
|
||||
Package (0x04) { 0xFFFF, 0x01, 0x00, 33 },
|
||||
Package (0x04) { 0xFFFF, 0x02, 0x00, 34 },
|
||||
Package (0x04) { 0xFFFF, 0x03, 0x00, 35 },
|
||||
})
|
||||
|
||||
Name (PR07, Package () {
|
||||
/* PIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, LNKE, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x01, LNKF, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x02, LNKG, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x03, LNKH, 0x00 },
|
||||
})
|
||||
|
||||
Name (AR07, Package () {
|
||||
/* APIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, 0x00, 36 },
|
||||
Package (0x04) { 0xFFFF, 0x01, 0x00, 37 },
|
||||
Package (0x04) { 0xFFFF, 0x02, 0x00, 38 },
|
||||
Package (0x04) { 0xFFFF, 0x03, 0x00, 39 },
|
||||
})
|
||||
|
||||
Name (PR08, Package () {
|
||||
/* PIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 },
|
||||
})
|
||||
|
||||
Name (AR08, Package () {
|
||||
/* APIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, 0x00, 40 },
|
||||
Package (0x04) { 0xFFFF, 0x01, 0x00, 41 },
|
||||
Package (0x04) { 0xFFFF, 0x02, 0x00, 42 },
|
||||
Package (0x04) { 0xFFFF, 0x03, 0x00, 43 },
|
||||
})
|
||||
|
||||
/* PCI Resource Tables */
|
||||
|
||||
/* PCI Resource Settings Access */
|
||||
Method (_CRS, 0, Serialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16,
|
||||
0x0CF8, // Address Range Minimum
|
||||
0x0CF8, // Address Range Maximum
|
||||
0x01, // Address Alignment
|
||||
0x08, // Address Length
|
||||
)
|
||||
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
0x0000, // Address Space Granularity
|
||||
0x0000, // Address Range Minimum
|
||||
0x0CF7, // Address Range Maximum
|
||||
0x0000, // Address Translation Offset
|
||||
0x0CF8, // Address Length
|
||||
,, , TypeStatic)
|
||||
})
|
||||
/* Methods below use SSDT to get actual MMIO regs
|
||||
The IO ports are from 0xd00, optionally an VGA,
|
||||
otherwise the info from MMIO is used.
|
||||
\_SB.GXXX(node, link)
|
||||
*/
|
||||
Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
|
||||
Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
|
||||
Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
|
||||
Return (Local3)
|
||||
}
|
||||
|
||||
/* PCI Routing Table Access */
|
||||
Method (_PRT, 0, NotSerialized) {
|
||||
If (PICM) {
|
||||
Return (AR00)
|
||||
} Else {
|
||||
Return (PR00)
|
||||
}
|
||||
}
|
||||
|
||||
/* 0:11.0 SP5100 SATA 0 */
|
||||
Device(SAT0)
|
||||
{
|
||||
Name (_ADR, 0x00110000) // _ADR: Address
|
||||
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
||||
#include <southbridge/amd/sb700/acpi/sata.asl>
|
||||
}
|
||||
|
||||
/* 0:12.0 SP5100 USB 0 */
|
||||
Device (USB0)
|
||||
{
|
||||
Name (_ADR, 0x00120000) // _ADR: Address
|
||||
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
|
||||
/* 0:12.1 SP5100 USB 1 */
|
||||
Device (USB1)
|
||||
{
|
||||
Name (_ADR, 0x00120001) // _ADR: Address
|
||||
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
|
||||
/* 0:12.2 SP5100 USB 2 */
|
||||
Device (USB2)
|
||||
{
|
||||
Name (_ADR, 0x00120002) // _ADR: Address
|
||||
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
|
||||
/* 0:13.0 SP5100 USB 3 */
|
||||
Device (USB3)
|
||||
{
|
||||
Name (_ADR, 0x00130000) // _ADR: Address
|
||||
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
|
||||
/* 0:13.1 SP5100 USB 4 */
|
||||
Device (USB4)
|
||||
{
|
||||
Name (_ADR, 0x00130001) // _ADR: Address
|
||||
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
|
||||
/* 0:13.2 SP5100 USB 5 */
|
||||
Device (USB5)
|
||||
{
|
||||
Name (_ADR, 0x00130002) // _ADR: Address
|
||||
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
|
||||
/* 0:14.1 SP5100 IDE Controller */
|
||||
Device (IDEC)
|
||||
{
|
||||
Name (_ADR, 0x00140001) // _ADR: Address
|
||||
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
||||
#include <southbridge/amd/sb700/acpi/ide.asl>
|
||||
}
|
||||
|
||||
/* 0:14.3 SP5100 LPC */
|
||||
Device (LPC) {
|
||||
Name (_HID, EisaId ("PNP0A05"))
|
||||
Name (_ADR, 0x00140003)
|
||||
|
||||
/* Real Time Clock Device */
|
||||
Device(RTC0) {
|
||||
Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
|
||||
Name(BUF0, ResourceTemplate() {
|
||||
IO(Decode16, 0x0070, 0x0070, 0x01, 0x02)
|
||||
})
|
||||
Name(BUF1, ResourceTemplate() {
|
||||
IRQNoFlags() { 8 }
|
||||
IO(Decode16, 0x0070, 0x0070, 0x01, 0x02)
|
||||
})
|
||||
Method(_CRS, 0) {
|
||||
If(HPTE) {
|
||||
Return(BUF0)
|
||||
}
|
||||
Return(BUF1)
|
||||
}
|
||||
}
|
||||
|
||||
Device(TMR) { /* Timer */
|
||||
Name(_HID,EISAID("PNP0100")) /* System Timer */
|
||||
Name(BUF0, ResourceTemplate() {
|
||||
IO(Decode16, 0x0040, 0x0040, 0x01, 0x04)
|
||||
})
|
||||
Name(BUF1, ResourceTemplate() {
|
||||
IRQNoFlags() { 0 }
|
||||
IO(Decode16, 0x0040, 0x0040, 0x01, 0x04)
|
||||
})
|
||||
Method(_CRS, 0) {
|
||||
If(HPTE) {
|
||||
Return(BUF0)
|
||||
}
|
||||
Return(BUF1)
|
||||
}
|
||||
}
|
||||
|
||||
Device(SPKR) { /* Speaker */
|
||||
Name(_HID,EISAID("PNP0800")) /* AT style speaker */
|
||||
Name(_CRS, ResourceTemplate() {
|
||||
IO(Decode16, 0x0061, 0x0061, 0, 1)
|
||||
})
|
||||
}
|
||||
|
||||
Device(PIC) {
|
||||
Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
|
||||
Name(_CRS, ResourceTemplate() {
|
||||
IRQNoFlags() { 2 }
|
||||
IO(Decode16,0x0020, 0x0020, 0, 2)
|
||||
IO(Decode16,0x00A0, 0x00A0, 0, 2)
|
||||
})
|
||||
}
|
||||
|
||||
Device(MAD) { /* 8257 DMA */
|
||||
Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
|
||||
Name(_CRS, ResourceTemplate() {
|
||||
DMA(Compatibility,BusMaster,Transfer8){4}
|
||||
IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
|
||||
IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
|
||||
IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
|
||||
IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
|
||||
IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
|
||||
IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
|
||||
}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
|
||||
}
|
||||
|
||||
Device(COPR) {
|
||||
Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
|
||||
Name(_CRS, ResourceTemplate() {
|
||||
IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
|
||||
IRQNoFlags(){13}
|
||||
})
|
||||
}
|
||||
|
||||
#include <superio/winbond/w83667hg-a/ps2_controller.asl>
|
||||
|
||||
/* UART 1 */
|
||||
Device (URT1)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART
|
||||
Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0f) // Always enable
|
||||
}
|
||||
Name (_PRS, ResourceTemplate() {
|
||||
StartDependentFn(0, 1) {
|
||||
IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
|
||||
IRQNoFlags() { 4 }
|
||||
} EndDependentFn()
|
||||
})
|
||||
Method (_CRS, 0)
|
||||
{
|
||||
Return(ResourceTemplate() {
|
||||
IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
|
||||
IRQNoFlags() { 4 }
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
/* UART 2 */
|
||||
Device (URT2)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART
|
||||
Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0f) // Always enable
|
||||
}
|
||||
Name (_PRS, ResourceTemplate() {
|
||||
StartDependentFn(0, 1) {
|
||||
IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
|
||||
IRQNoFlags() { 3 }
|
||||
} EndDependentFn()
|
||||
})
|
||||
Method (_CRS, 0)
|
||||
{
|
||||
Return(ResourceTemplate() {
|
||||
IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
|
||||
IRQNoFlags() { 3 }
|
||||
})
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* High Precision Event Timer */
|
||||
Device (HPET)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0103"))
|
||||
Name (CRS, ResourceTemplate ()
|
||||
{
|
||||
Memory32Fixed(ReadOnly, 0xFED00000, 0x00000400)
|
||||
})
|
||||
Method (_STA, 0)
|
||||
{
|
||||
If(HPTE) {
|
||||
Return (0x0F)
|
||||
}
|
||||
Return (0x0)
|
||||
}
|
||||
Method(_CRS, 0)
|
||||
{
|
||||
Return(CRS)
|
||||
}
|
||||
}
|
||||
|
||||
/* 0:14.4 PCI Bridge */
|
||||
Device (PBR0)
|
||||
{
|
||||
Name (_ADR, 0x00140004) // _ADR: Address
|
||||
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
|
||||
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
||||
{
|
||||
If (PICM) {
|
||||
Return (AR01)
|
||||
} Else {
|
||||
Return (PR01)
|
||||
}
|
||||
}
|
||||
Device (SLT1)
|
||||
{
|
||||
Name (_ADR, 0xFFFF) // _ADR: Address
|
||||
Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
}
|
||||
|
||||
/* 0:14.5 SP5100 USB 6 */
|
||||
Device (USB6)
|
||||
{
|
||||
Name (_ADR, 0x00140005) // _ADR: Address
|
||||
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
|
||||
/* 2:00.0 PCIe x16 */
|
||||
Device (PCE1)
|
||||
{
|
||||
Name (_ADR, 0x00020000) // _ADR: Address
|
||||
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
|
||||
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
||||
{
|
||||
If (PICM) {
|
||||
Return (AR02)
|
||||
} Else {
|
||||
Return (PR02)
|
||||
}
|
||||
}
|
||||
Device (SLT1)
|
||||
{
|
||||
Name (_ADR, 0xFFFF) // _ADR: Address
|
||||
Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
}
|
||||
|
||||
/* 1:00.0 PIKE */
|
||||
Device (PIKE)
|
||||
{
|
||||
Name (_ADR, 0x00040000) // _ADR: Address
|
||||
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
|
||||
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
||||
{
|
||||
If (PICM) {
|
||||
Return (AR03)
|
||||
} Else {
|
||||
Return (PR03)
|
||||
}
|
||||
}
|
||||
Device (SLT1)
|
||||
{
|
||||
Name (_ADR, 0xFFFF) // _ADR: Address
|
||||
Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
}
|
||||
|
||||
/* 3:00.0 PCIe NIC A */
|
||||
Device (NICA)
|
||||
{
|
||||
Name (_ADR, 0x00090000) // _ADR: Address
|
||||
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
|
||||
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
||||
{
|
||||
If (PICM) {
|
||||
Return (AR04)
|
||||
} Else {
|
||||
Return (PR04)
|
||||
}
|
||||
}
|
||||
Device (BDC1)
|
||||
{
|
||||
Name (_ADR, Zero) // _ADR: Address
|
||||
}
|
||||
}
|
||||
|
||||
/* 4:00.0 PCIe NIC B */
|
||||
Device (NICB)
|
||||
{
|
||||
Name (_ADR, 0x000A0000) // _ADR: Address
|
||||
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
|
||||
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
||||
{
|
||||
If (PICM) {
|
||||
Return (AR05)
|
||||
} Else {
|
||||
Return (PR05)
|
||||
}
|
||||
}
|
||||
Device (BDC2)
|
||||
{
|
||||
Name (_ADR, Zero) // _ADR: Address
|
||||
}
|
||||
}
|
||||
|
||||
/* 5:00.0 PCIe x16 */
|
||||
Device (PCE4)
|
||||
{
|
||||
Name (_ADR, 0x000B0000) // _ADR: Address
|
||||
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
|
||||
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
||||
{
|
||||
If (PICM) {
|
||||
Return (AR06)
|
||||
} Else {
|
||||
Return (PR06)
|
||||
}
|
||||
}
|
||||
Device (SLT1)
|
||||
{
|
||||
Name (_ADR, 0xFFFF) // _ADR: Address
|
||||
Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Device (PWRB) { /* Start Power button device */
|
||||
Name(_HID, EISAID("PNP0C0C"))
|
||||
Name(_UID, 0xAA)
|
||||
Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
|
||||
Name(_STA, 0x0B) /* sata is invisible */
|
||||
}
|
||||
}
|
||||
|
||||
#include "acpi/pm_ctrl.asl"
|
||||
|
||||
}
|
||||
@@ -1,29 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/pci.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <cpu/amd/multicore.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
void get_bus_conf(void)
|
||||
{
|
||||
get_default_pci1234(1);
|
||||
sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
|
||||
|
||||
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
|
||||
}
|
||||
@@ -1,123 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2015 Raptor Engineering
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
/* Free irqs are 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15 */
|
||||
#define IRQBM ((1 << 3)|(1 << 4)|(1 << 5)|(1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 12)|(1 << 14)|(1 << 15))
|
||||
|
||||
#define LNKA 1
|
||||
#define LNKB 2
|
||||
#define LNKC 3
|
||||
#define LNKD 4
|
||||
|
||||
/*
|
||||
* For simplicity map LNK[E-H] to LNK[A-D].
|
||||
* This also means we are 82C596 compatible.
|
||||
* Needs 0:11.0 0x46[4] set to 0.
|
||||
*/
|
||||
#define LNKE 1
|
||||
#define LNKF 2
|
||||
#define LNKG 3
|
||||
#define LNKH 4
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
|
||||
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
|
||||
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
|
||||
u8 slot, u8 rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
u32 slot_num;
|
||||
u8 *v;
|
||||
|
||||
u8 sum = 0;
|
||||
int i;
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be between 0xf0000 & 0x100000 */
|
||||
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (u8 *) (addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
/* Where the interrupt router resides */
|
||||
pirq->rtr_bus = pirq_router_bus;
|
||||
pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
pirq->rtr_vendor = PCI_VENDOR_ID_ATI;
|
||||
pirq->rtr_device = PCI_DEVICE_ID_ATI_SB700_PCI;
|
||||
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *)(&pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
|
||||
/* pci bridge */
|
||||
write_pirq_info(pirq_info, pirq_router_bus,
|
||||
PCI_DEVFN(0x14, 4), LNKA, IRQBM, LNKB,
|
||||
IRQBM, LNKC, IRQBM, LNKD, IRQBM, 0, 0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "done.\n");
|
||||
|
||||
return (unsigned long)pirq_info;
|
||||
}
|
||||
@@ -1,113 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/mmio.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <southbridge/amd/sb700/sb700.h>
|
||||
#include <southbridge/amd/sr5650/cmn.h>
|
||||
|
||||
void set_pcie_reset(void)
|
||||
{
|
||||
struct device *pcie_core_dev;
|
||||
|
||||
pcie_core_dev = pcidev_on_root(0, 0);
|
||||
set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828);
|
||||
set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x00000028);
|
||||
}
|
||||
|
||||
void set_pcie_dereset(void)
|
||||
{
|
||||
struct device *pcie_core_dev;
|
||||
|
||||
pcie_core_dev = pcidev_on_root(0, 0);
|
||||
set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F);
|
||||
set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x0000006F);
|
||||
}
|
||||
|
||||
/*************************************************
|
||||
* enable the dedicated function in kgpe-d16 board.
|
||||
* This function is called earlier than sr5650_enable.
|
||||
*************************************************/
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
printk(BIOS_INFO, "Mainboard KCMA-D8 initializing, dev=0x%p\n", dev);
|
||||
|
||||
msr_t msr, msr2;
|
||||
|
||||
/* TOP_MEM: the top of DRAM below 4G */
|
||||
msr = rdmsr(TOP_MEM);
|
||||
printk
|
||||
(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
|
||||
__func__, msr.lo, msr.hi);
|
||||
|
||||
/* TOP_MEM2: the top of DRAM above 4G */
|
||||
msr2 = rdmsr(TOP_MEM2);
|
||||
printk
|
||||
(BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
|
||||
__func__, msr2.lo, msr2.hi);
|
||||
|
||||
set_pcie_dereset();
|
||||
/* get_ide_dma66(); */
|
||||
}
|
||||
|
||||
/* override the default SATA PHY setup */
|
||||
void sb7xx_51xx_setup_sata_phys(struct device *dev)
|
||||
{
|
||||
/* RPR7.6.1 Program the PHY Global Control to 0x2C00 */
|
||||
pci_write_config16(dev, 0x86, 0x2c00);
|
||||
|
||||
/* RPR7.6.2 SATA GENI PHY ports setting */
|
||||
pci_write_config32(dev, 0x88, 0x01b48016);
|
||||
pci_write_config32(dev, 0x8c, 0x01b48016);
|
||||
pci_write_config32(dev, 0x90, 0x01b48016);
|
||||
pci_write_config32(dev, 0x94, 0x01b48016);
|
||||
pci_write_config32(dev, 0x98, 0x01b48016);
|
||||
pci_write_config32(dev, 0x9c, 0x01b48016);
|
||||
|
||||
/* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */
|
||||
pci_write_config16(dev, 0xa0, 0xa07a);
|
||||
pci_write_config16(dev, 0xa2, 0xa07a);
|
||||
pci_write_config16(dev, 0xa4, 0xa07a);
|
||||
pci_write_config16(dev, 0xa6, 0xa07a);
|
||||
pci_write_config16(dev, 0xa8, 0xa07a);
|
||||
pci_write_config16(dev, 0xaa, 0xa07a);
|
||||
}
|
||||
|
||||
/* override the default SATA port setup */
|
||||
void sb7xx_51xx_setup_sata_port_indication(void *sata_bar5)
|
||||
{
|
||||
uint32_t dword;
|
||||
|
||||
/* RPR7.9 Program Port Indication Registers */
|
||||
dword = read32(sata_bar5 + 0xf8);
|
||||
dword &= ~(0x3f << 12); /* All ports are iSATA */
|
||||
dword &= ~0x3f;
|
||||
write32(sata_bar5 + 0xf8, dword);
|
||||
|
||||
dword = read32(sata_bar5 + 0xfc);
|
||||
dword &= ~(0x1 << 20); /* No eSATA ports are present */
|
||||
write32(sata_bar5 + 0xfc, dword);
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
@@ -1,219 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2015 Raptor Engineering
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <stdint.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
u32 apicid_sp5100;
|
||||
u32 apicid_sr5650;
|
||||
struct device *dev;
|
||||
uint8_t sp5100_bus_number;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
|
||||
apicid_sp5100 = 0x0;
|
||||
else
|
||||
apicid_sp5100 = 0x20;
|
||||
apicid_sr5650 = apicid_sp5100 + 1;
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
{
|
||||
uint32_t *dword_ptr;
|
||||
uint32_t dword;
|
||||
uint16_t word;
|
||||
uint8_t byte;
|
||||
|
||||
sp5100_bus_number = 0; //bus_sp5100[0]; TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0.
|
||||
|
||||
dev = dev_find_slot(sp5100_bus_number, PCI_DEVFN(0x14, 0));
|
||||
if (dev) {
|
||||
dword_ptr = (u32 *)(pci_read_config32(dev, 0x74) & 0xfffffff0);
|
||||
smp_write_ioapic(mc, apicid_sp5100, 0x11, dword_ptr);
|
||||
|
||||
/* Initialize interrupt mapping */
|
||||
/* USB 1 & 2 */
|
||||
word = pci_read_config16(dev, 0xbe);
|
||||
word &= ~0x3f3f;
|
||||
word |= 0x0; /* 0: INTA, ...., 7: INTH */
|
||||
word |= (0x1 << 3); /* 0: INTA, ...., 7: INTH */
|
||||
word |= (0x2 << 8); /* 0: INTA, ...., 7: INTH */
|
||||
word |= (0x3 << 11); /* 0: INTA, ...., 7: INTH */
|
||||
pci_write_config16(dev, 0xbe, word);
|
||||
|
||||
/* USB 3 */
|
||||
byte = pci_read_config8(dev, 0x63);
|
||||
byte &= 0xf8;
|
||||
byte |= (0x2 << 4); /* 0: INTA, ...., 7: INTH */
|
||||
pci_write_config8(dev, 0x63, byte);
|
||||
|
||||
dword = pci_read_config32(dev, 0xac);
|
||||
|
||||
/* SATA */
|
||||
dword &= ~(7 << 26);
|
||||
dword |= (0x6 << 26); /* 0: INTA, ...., 7: INTH */
|
||||
|
||||
/* Hide IDE */
|
||||
dword &= ~(0x00080000);
|
||||
|
||||
/* dword_ptr |= 1 << 22; PIC and APIC co exists */
|
||||
pci_write_config32(dev, 0xac, dword);
|
||||
|
||||
/*
|
||||
* 00:12.0: PROG SATA : INT F
|
||||
* 00:13.0: INTA USB_0
|
||||
* 00:13.1: INTB USB_1
|
||||
* 00:13.2: INTC USB_2
|
||||
* 00:13.3: INTD USB_3
|
||||
* 00:13.4: INTC USB_4
|
||||
* 00:13.5: INTD USB2
|
||||
* 00:14.1: INTA IDE
|
||||
* 00:14.2: Prog HDA : INT E
|
||||
* 00:14.5: INTB ACI
|
||||
* 00:14.6: INTB MCI
|
||||
*/
|
||||
}
|
||||
dev = pcidev_on_root(0, 0);
|
||||
if (dev) {
|
||||
pci_write_config32(dev, 0xF8, 0x1);
|
||||
dword_ptr = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
|
||||
smp_write_ioapic(mc, apicid_sr5650, 0x11, dword_ptr);
|
||||
}
|
||||
}
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0);
|
||||
|
||||
/* SR5650 devices */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((0)<<2)|(2)), apicid_sr5650, 31); /* Device 0 Function 2 (LNKA, APIC pin 31) */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((2)<<2)|(0)), apicid_sr5650, 28); /* Device 2 (LNKE, APIC pin 28) */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((4)<<2)|(0)), apicid_sr5650, 28); /* Device 4 (LNKF, APIC pin 28) */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((9)<<2)|(0)), apicid_sr5650, 29); /* Device 9 (LNKG, APIC pin 29) */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((10)<<2)|(0)), apicid_sr5650, 30); /* Device 10 (LNKG, APIC pin 30) */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((11)<<2)|(0)), apicid_sr5650, 30); /* Device 11 (LNKG, APIC pin 30) */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sr5650, 30); /* Device 12 (LNKG, APIC pin 30) */
|
||||
|
||||
dev = pcidev_on_root(0x2, 0);
|
||||
if (dev && dev->enabled) {
|
||||
uint8_t bus_pci = dev->link_list->secondary;
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x2)|(0)), apicid_sr5650, 0); /* card behind dev2 */
|
||||
}
|
||||
dev = pcidev_on_root(0x4, 0);
|
||||
if (dev && dev->enabled) {
|
||||
uint8_t bus_pci = dev->link_list->secondary;
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x4)|(0)), apicid_sr5650, 0); /* PIKE */
|
||||
}
|
||||
dev = pcidev_on_root(0x9, 0);
|
||||
if (dev && dev->enabled) {
|
||||
uint8_t bus_pci = dev->link_list->secondary;
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x9)|(0)), apicid_sr5650, 23); /* NIC A */
|
||||
}
|
||||
dev = pcidev_on_root(0xa, 0);
|
||||
if (dev && dev->enabled) {
|
||||
uint8_t bus_pci = dev->link_list->secondary;
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xa)|(0)), apicid_sr5650, 24); /* NIC B */
|
||||
}
|
||||
dev = pcidev_on_root(0xb, 0);
|
||||
if (dev && dev->enabled) {
|
||||
uint8_t bus_pci = dev->link_list->secondary;
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xb)|(0)), apicid_sr5650, 0); /* card behind dev11 */
|
||||
}
|
||||
dev = pcidev_on_root(0xc, 0);
|
||||
if (dev && dev->enabled) {
|
||||
uint8_t bus_pci = dev->link_list->secondary;
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xc)|(0)), apicid_sr5650, 0); /* card behind dev12 */
|
||||
}
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, interrupt_signal, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(interrupt_signal)), apicid_sp5100, (pin))
|
||||
|
||||
/* USB1 */
|
||||
PCI_INT(sp5100_bus_number, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */
|
||||
PCI_INT(sp5100_bus_number, 0x12, 0x1, 0x11); /* OHCI1 Port 3~5 */
|
||||
|
||||
/* USB2 */
|
||||
PCI_INT(sp5100_bus_number, 0x13, 0x0, 0x12); /* OHCI0 Port 6~8 */
|
||||
PCI_INT(sp5100_bus_number, 0x13, 0x1, 0x13); /* EHCI Port 6~11 */
|
||||
|
||||
/* USB3 */
|
||||
PCI_INT(sp5100_bus_number, 0x14, 0x3, 0x12); /* OHCI0 Port 12~13 */
|
||||
|
||||
/* SATA */
|
||||
PCI_INT(sp5100_bus_number, 0x11, 0x0, 0x16); /* 6, INTG */
|
||||
|
||||
/* PCI slots */
|
||||
dev = pcidev_on_root(0x14, 4);
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
|
||||
/* PCI_SLOT 0 */
|
||||
PCI_INT(bus_pci, 0x1, 0x0, 0x14);
|
||||
PCI_INT(bus_pci, 0x1, 0x1, 0x15);
|
||||
PCI_INT(bus_pci, 0x1, 0x2, 0x16);
|
||||
PCI_INT(bus_pci, 0x1, 0x3, 0x17);
|
||||
|
||||
/* PCI_SLOT 1 */
|
||||
PCI_INT(bus_pci, 0x2, 0x0, 0x15);
|
||||
PCI_INT(bus_pci, 0x2, 0x1, 0x16);
|
||||
PCI_INT(bus_pci, 0x2, 0x2, 0x17);
|
||||
PCI_INT(bus_pci, 0x2, 0x3, 0x14);
|
||||
|
||||
/* PCI_SLOT 2 */
|
||||
PCI_INT(bus_pci, 0x3, 0x0, 0x16);
|
||||
PCI_INT(bus_pci, 0x3, 0x1, 0x17);
|
||||
PCI_INT(bus_pci, 0x3, 0x2, 0x14);
|
||||
PCI_INT(bus_pci, 0x3, 0x3, 0x15);
|
||||
|
||||
/* VGA */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, 0x17);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, 0x14);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, 0x15);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, 0x16);
|
||||
}
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
@@ -1,553 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
*
|
||||
* Copyright (C) 2007 AMD
|
||||
* Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <commonlib/helpers.h>
|
||||
#include <northbridge/amd/amdfam10/amdfam10.h>
|
||||
|
||||
void setup_mb_resource_map(void)
|
||||
{
|
||||
static const unsigned int fam15h_register_values[] = {
|
||||
/* Careful set limit registers before base registers which contain the enables */
|
||||
/* DRAM Limit i Registers
|
||||
* F1:0x44 i = 0
|
||||
* F1:0x4C i = 1
|
||||
* F1:0x54 i = 2
|
||||
* F1:0x5C i = 3
|
||||
* F1:0x64 i = 4
|
||||
* F1:0x6C i = 5
|
||||
* F1:0x74 i = 6
|
||||
* F1:0x7C i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 3] Reserved
|
||||
* [10: 8] Interleave select
|
||||
* specifies the values of A[14:12] to use with interleave enable.
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Limit Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40 bit address
|
||||
* that define the end of the DRAM region.
|
||||
*/
|
||||
// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000,
|
||||
ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001,
|
||||
ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002,
|
||||
ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003,
|
||||
ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004,
|
||||
ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005,
|
||||
ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006,
|
||||
ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
|
||||
|
||||
/* DRAM Base i Registers
|
||||
* F1:0x40 i = 0
|
||||
* F1:0x48 i = 1
|
||||
* F1:0x50 i = 2
|
||||
* F1:0x58 i = 3
|
||||
* F1:0x60 i = 4
|
||||
* F1:0x68 i = 5
|
||||
* F1:0x70 i = 6
|
||||
* F1:0x78 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 7: 2] Reserved
|
||||
* [10: 8] Interleave Enable
|
||||
* 000 = No interleave
|
||||
* 001 = Interleave on A[12] (2 nodes)
|
||||
* 010 = reserved
|
||||
* 011 = Interleave on A[12] and A[14] (4 nodes)
|
||||
* 100 = reserved
|
||||
* 101 = reserved
|
||||
* 110 = reserved
|
||||
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Base Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40-bit address
|
||||
* that define the start of the DRAM region.
|
||||
*/
|
||||
// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
* F1:0x8C i = 1
|
||||
* F1:0x94 i = 2
|
||||
* F1:0x9C i = 3
|
||||
* F1:0xA4 i = 4
|
||||
* F1:0xAC i = 5
|
||||
* F1:0xB4 i = 6
|
||||
* F1:0xBC i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Link 3
|
||||
* [ 6: 6] Reserved
|
||||
* [ 7: 7] Non-Posted
|
||||
* 0 = CPU writes may be posted
|
||||
* 1 = CPU writes must be non-posted
|
||||
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
|
||||
* This field defines the upp address bits of a 40-bit address that
|
||||
* defines the end of a memory-mapped I/O region n
|
||||
*/
|
||||
ADDRMAP_REG(0x84), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x8C), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x94), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x9C), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xA4), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xAC), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xBC), 0x00000048, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Base i Registers
|
||||
* F1:0x80 i = 0
|
||||
* F1:0x88 i = 1
|
||||
* F1:0x90 i = 2
|
||||
* F1:0x98 i = 3
|
||||
* F1:0xA0 i = 4
|
||||
* F1:0xA8 i = 5
|
||||
* F1:0xB0 i = 6
|
||||
* F1:0xB8 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Cpu Disable
|
||||
* 0 = Cpu can use this I/O range
|
||||
* 1 = Cpu requests do not use this I/O range
|
||||
* [ 3: 3] Lock
|
||||
* 0 = base/limit registers i are read/write
|
||||
* 1 = base/limit registers i are read-only
|
||||
* [ 7: 4] Reserved
|
||||
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
|
||||
* This field defines the upper address bits of a 40bit address
|
||||
* that defines the start of memory-mapped I/O region i
|
||||
*/
|
||||
ADDRMAP_REG(0x80), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x88), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x90), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x98), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xB8), 0x000000f0, 0x00000000,
|
||||
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
* F1:0xCC i = 1
|
||||
* F1:0xD4 i = 2
|
||||
* F1:0xDC i = 3
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Link 3
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Limit Address i
|
||||
* This field defines the end of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of CPU 0 --> AMD SR5690 */
|
||||
ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000,
|
||||
ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000,
|
||||
ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
|
||||
|
||||
/* PCI I/O Base i Registers
|
||||
* F1:0xC0 i = 0
|
||||
* F1:0xC8 i = 1
|
||||
* F1:0xD0 i = 2
|
||||
* F1:0xD8 i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 3: 2] Reserved
|
||||
* [ 4: 4] VGA Enable
|
||||
* 0 = VGA matches Disabled
|
||||
* 1 = matches all address < 64K and where A[9:0] is in the
|
||||
* range 3B0-3BB or 3C0-3DF independent of the base & limit registers
|
||||
* [ 5: 5] ISA Enable
|
||||
* 0 = ISA matches Disabled
|
||||
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
|
||||
* from matching agains this base/limit pair
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Base i
|
||||
* This field defines the start of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001013,
|
||||
ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000,
|
||||
ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000,
|
||||
ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
|
||||
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
* F1:0xE8 i = 2
|
||||
* F1:0xEC i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Device Number Compare Enable
|
||||
* 0 = The ranges are based on bus number
|
||||
* 1 = The ranges are ranges of devices on bus 0
|
||||
* [ 3: 3] Reserved
|
||||
* [ 6: 4] Destination Node
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 7] Reserved
|
||||
* [ 9: 8] Destination Link
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 - Link 3
|
||||
* [15:10] Reserved
|
||||
* [23:16] Bus Number Base i
|
||||
* This field defines the lowest bus number in configuration region i
|
||||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration region i
|
||||
*/
|
||||
ADDRMAP_REG(0xE0), 0x0000FC88, 0x05000203, /* link 2 of CPU 0 --> AMD SR5690 */
|
||||
ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000,
|
||||
ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000,
|
||||
ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
|
||||
|
||||
};
|
||||
|
||||
static const unsigned int fam10h_register_values[] = {
|
||||
/* Careful set limit registers before base registers which contain the enables */
|
||||
/* DRAM Limit i Registers
|
||||
* F1:0x44 i = 0
|
||||
* F1:0x4C i = 1
|
||||
* F1:0x54 i = 2
|
||||
* F1:0x5C i = 3
|
||||
* F1:0x64 i = 4
|
||||
* F1:0x6C i = 5
|
||||
* F1:0x74 i = 6
|
||||
* F1:0x7C i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 3] Reserved
|
||||
* [10: 8] Interleave select
|
||||
* specifies the values of A[14:12] to use with interleave enable.
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Limit Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40 bit address
|
||||
* that define the end of the DRAM region.
|
||||
*/
|
||||
// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000,
|
||||
ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001,
|
||||
ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002,
|
||||
ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003,
|
||||
ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004,
|
||||
ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005,
|
||||
ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006,
|
||||
ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
|
||||
|
||||
/* DRAM Base i Registers
|
||||
* F1:0x40 i = 0
|
||||
* F1:0x48 i = 1
|
||||
* F1:0x50 i = 2
|
||||
* F1:0x58 i = 3
|
||||
* F1:0x60 i = 4
|
||||
* F1:0x68 i = 5
|
||||
* F1:0x70 i = 6
|
||||
* F1:0x78 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 7: 2] Reserved
|
||||
* [10: 8] Interleave Enable
|
||||
* 000 = No interleave
|
||||
* 001 = Interleave on A[12] (2 nodes)
|
||||
* 010 = reserved
|
||||
* 011 = Interleave on A[12] and A[14] (4 nodes)
|
||||
* 100 = reserved
|
||||
* 101 = reserved
|
||||
* 110 = reserved
|
||||
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Base Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40-bit address
|
||||
* that define the start of the DRAM region.
|
||||
*/
|
||||
// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
* F1:0x8C i = 1
|
||||
* F1:0x94 i = 2
|
||||
* F1:0x9C i = 3
|
||||
* F1:0xA4 i = 4
|
||||
* F1:0xAC i = 5
|
||||
* F1:0xB4 i = 6
|
||||
* F1:0xBC i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Link 3
|
||||
* [ 6: 6] Reserved
|
||||
* [ 7: 7] Non-Posted
|
||||
* 0 = CPU writes may be posted
|
||||
* 1 = CPU writes must be non-posted
|
||||
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
|
||||
* This field defines the upp address bits of a 40-bit address that
|
||||
* defines the end of a memory-mapped I/O region n
|
||||
*/
|
||||
ADDRMAP_REG(0x84), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x8C), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x94), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x9C), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xA4), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xAC), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xBC), 0x00000048, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Base i Registers
|
||||
* F1:0x80 i = 0
|
||||
* F1:0x88 i = 1
|
||||
* F1:0x90 i = 2
|
||||
* F1:0x98 i = 3
|
||||
* F1:0xA0 i = 4
|
||||
* F1:0xA8 i = 5
|
||||
* F1:0xB0 i = 6
|
||||
* F1:0xB8 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Cpu Disable
|
||||
* 0 = Cpu can use this I/O range
|
||||
* 1 = Cpu requests do not use this I/O range
|
||||
* [ 3: 3] Lock
|
||||
* 0 = base/limit registers i are read/write
|
||||
* 1 = base/limit registers i are read-only
|
||||
* [ 7: 4] Reserved
|
||||
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
|
||||
* This field defines the upper address bits of a 40bit address
|
||||
* that defines the start of memory-mapped I/O region i
|
||||
*/
|
||||
ADDRMAP_REG(0x80), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x88), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x90), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x98), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xB8), 0x000000f0, 0x00000000,
|
||||
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
* F1:0xCC i = 1
|
||||
* F1:0xD4 i = 2
|
||||
* F1:0xDC i = 3
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Link 3
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Limit Address i
|
||||
* This field defines the end of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of CPU 0 --> AMD SR5690 */
|
||||
ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000,
|
||||
ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000,
|
||||
ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
|
||||
|
||||
/* PCI I/O Base i Registers
|
||||
* F1:0xC0 i = 0
|
||||
* F1:0xC8 i = 1
|
||||
* F1:0xD0 i = 2
|
||||
* F1:0xD8 i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 3: 2] Reserved
|
||||
* [ 4: 4] VGA Enable
|
||||
* 0 = VGA matches Disabled
|
||||
* 1 = matches all address < 64K and where A[9:0] is in the
|
||||
* range 3B0-3BB or 3C0-3DF independent of the base & limit registers
|
||||
* [ 5: 5] ISA Enable
|
||||
* 0 = ISA matches Disabled
|
||||
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
|
||||
* from matching agains this base/limit pair
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Base i
|
||||
* This field defines the start of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001013,
|
||||
ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000,
|
||||
ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000,
|
||||
ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
|
||||
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
* F1:0xE8 i = 2
|
||||
* F1:0xEC i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Device Number Compare Enable
|
||||
* 0 = The ranges are based on bus number
|
||||
* 1 = The ranges are ranges of devices on bus 0
|
||||
* [ 3: 3] Reserved
|
||||
* [ 6: 4] Destination Node
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 7] Reserved
|
||||
* [ 9: 8] Destination Link
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 - Link 3
|
||||
* [15:10] Reserved
|
||||
* [23:16] Bus Number Base i
|
||||
* This field defines the lowest bus number in configuration region i
|
||||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration region i
|
||||
*/
|
||||
ADDRMAP_REG(0xE0), 0x0000FC88, 0x05000203, /* link 2 of CPU 0 --> AMD SR5690 */
|
||||
ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000,
|
||||
ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000,
|
||||
ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
|
||||
|
||||
};
|
||||
|
||||
int max;
|
||||
uint8_t fam15h = 0;
|
||||
uint32_t family;
|
||||
|
||||
family = cpuid_eax(0x80000001);
|
||||
family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
|
||||
|
||||
if (family >= 0x6f)
|
||||
/* Family 15h or later */
|
||||
fam15h = 1;
|
||||
|
||||
if (fam15h) {
|
||||
max = ARRAY_SIZE(fam15h_register_values);
|
||||
setup_resource_map(fam15h_register_values, max);
|
||||
} else {
|
||||
max = ARRAY_SIZE(fam10h_register_values);
|
||||
setup_resource_map(fam10h_register_values, max);
|
||||
}
|
||||
}
|
||||
@@ -1,606 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 - 2016 Raptor Engineering, LLC
|
||||
*
|
||||
* Copyright (C) 2007 AMD
|
||||
* Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <console/console.h>
|
||||
#include <romstage_handoff.h>
|
||||
#include <timestamp.h>
|
||||
#include <spd.h>
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
#include <delay.h>
|
||||
#include <superio/winbond/common/winbond.h>
|
||||
#include <superio/winbond/w83667hg-a/w83667hg-a.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include <smp/spinlock.h>
|
||||
#include <cpu/amd/car.h>
|
||||
#include <cpu/amd/msr.h>
|
||||
#include <southbridge/amd/common/reset.h>
|
||||
#include <southbridge/amd/sb700/sb700.h>
|
||||
#include <southbridge/amd/sb700/smbus.h>
|
||||
#include <southbridge/amd/sr5650/sr5650.h>
|
||||
#include <northbridge/amd/amdfam10/raminit.h>
|
||||
#include <northbridge/amd/amdht/ht_wrapper.h>
|
||||
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
|
||||
#include <arch/early_variables.h>
|
||||
#include <cbmem.h>
|
||||
#include <types.h>
|
||||
|
||||
#include "cpu/amd/quadcore/quadcore.c"
|
||||
|
||||
#define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
|
||||
#define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2)
|
||||
|
||||
int spd_read_byte(unsigned int device, unsigned int address);
|
||||
|
||||
inline int spd_read_byte(unsigned int device, unsigned int address)
|
||||
{
|
||||
return do_smbus_read_byte(SMBUS_AUX_IO_BASE, device, address);
|
||||
}
|
||||
|
||||
/*
|
||||
* ASUS KCMA-D8 specific SPD enable/disable magic.
|
||||
*
|
||||
* Setting SP5100 GPIOs 59 and 60 controls an SPI mux with four settings:
|
||||
* 0: Disabled
|
||||
* 1: Normal SPI access
|
||||
* 2: CPU0 SPD
|
||||
* 3: CPU1 SPD
|
||||
*
|
||||
* Disable SPD access after RAM init to allow access to standard SMBus/I2C offsets
|
||||
* which is required e.g. by lm-sensors.
|
||||
*/
|
||||
|
||||
/* Relevant GPIO register information is available in the
|
||||
* AMD SP5100 Register Reference Guide rev. 3.03, page 130
|
||||
*/
|
||||
static void switch_spd_mux(uint8_t channel)
|
||||
{
|
||||
uint8_t byte;
|
||||
|
||||
byte = pci_read_config8(PCI_DEV(0, 0x14, 0), 0x54);
|
||||
byte &= ~0xc; /* Clear SPD mux GPIOs */
|
||||
byte &= ~0xc0; /* Enable SPD mux GPIO output drivers */
|
||||
byte |= (channel << 2) & 0xc; /* Set SPD mux GPIOs */
|
||||
pci_write_config8(PCI_DEV(0, 0x14, 0), 0x54, byte);
|
||||
}
|
||||
|
||||
static const uint8_t spd_addr_fam15[] = {
|
||||
// Socket 0 Node 0 ("Node 0")
|
||||
RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
|
||||
// Socket 1 Node 0 ("Node 1")
|
||||
RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
|
||||
};
|
||||
|
||||
static const uint8_t spd_addr_fam10[] = {
|
||||
// Socket 0 Node 0 ("Node 0")
|
||||
RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
|
||||
// Socket 1 Node 0 ("Node 1")
|
||||
RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
|
||||
};
|
||||
|
||||
void activate_spd_rom(const struct mem_controller *ctrl) {
|
||||
printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id);
|
||||
if (ctrl->node_id == 0) {
|
||||
printk(BIOS_DEBUG, "enable_spd_node0()\n");
|
||||
switch_spd_mux(0x2);
|
||||
} else if (ctrl->node_id == 1) {
|
||||
printk(BIOS_DEBUG, "enable_spd_node1()\n");
|
||||
switch_spd_mux(0x3);
|
||||
}
|
||||
}
|
||||
|
||||
/* Voltages are specified by index
|
||||
* Valid indices for this platform are:
|
||||
* 0: 1.5V
|
||||
* 1: 1.35V
|
||||
* 2: 1.25V
|
||||
* 3: 1.15V
|
||||
*/
|
||||
static void set_ddr3_voltage(uint8_t node, uint8_t index) {
|
||||
uint8_t byte;
|
||||
uint8_t value = 0;
|
||||
|
||||
if (index == 0)
|
||||
value = 0x0;
|
||||
else if (index == 1)
|
||||
value = 0x1;
|
||||
else if (index == 2)
|
||||
value = 0x4;
|
||||
else if (index == 3)
|
||||
value = 0x5;
|
||||
if (node == 1)
|
||||
value <<= 1;
|
||||
|
||||
/* Set GPIOs */
|
||||
byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0xd1);
|
||||
if (node == 0)
|
||||
byte &= ~0x5;
|
||||
if (node == 1)
|
||||
byte &= ~0xa;
|
||||
byte |= value;
|
||||
pci_write_config8(PCI_DEV(0, 0x14, 3), 0xd1, byte);
|
||||
|
||||
/* Enable GPIO output drivers */
|
||||
byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0xd0);
|
||||
byte &= 0x0f;
|
||||
pci_write_config8(PCI_DEV(0, 0x14, 3), 0xd0, byte);
|
||||
|
||||
printk(BIOS_DEBUG, "Node %02d DIMM voltage set to index %02x\n", node, index);
|
||||
}
|
||||
|
||||
void DIMMSetVoltages(struct MCTStatStruc *pMCTstat,
|
||||
struct DCTStatStruc *pDCTstatA) {
|
||||
/* This mainboard allows the DIMM voltage to be set per-socket.
|
||||
* Therefore, for each socket, iterate over all DIMMs to find the
|
||||
* lowest supported voltage common to all DIMMs on that socket.
|
||||
*/
|
||||
uint8_t nvram;
|
||||
uint8_t dimm;
|
||||
uint8_t node;
|
||||
uint8_t socket;
|
||||
uint8_t allowed_voltages = 0xf; /* The mainboard VRMs allow 1.15V, 1.25V, 1.35V, and 1.5V */
|
||||
uint8_t socket_allowed_voltages = allowed_voltages;
|
||||
uint32_t set_voltage = 0;
|
||||
|
||||
if (get_option(&nvram, "minimum_memory_voltage") == CB_SUCCESS) {
|
||||
switch (nvram) {
|
||||
case 2:
|
||||
allowed_voltages = 0x7; /* Allow 1.25V, 1.35V, and 1.5V */
|
||||
break;
|
||||
case 1:
|
||||
allowed_voltages = 0x3; /* Allow 1.35V and 1.5V */
|
||||
break;
|
||||
case 0:
|
||||
default:
|
||||
allowed_voltages = 0x1; /* Allow 1.5V only */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
|
||||
socket = node;
|
||||
struct DCTStatStruc *pDCTstat;
|
||||
pDCTstat = pDCTstatA + node;
|
||||
|
||||
/* reset socket_allowed_voltages before processing each socket */
|
||||
socket_allowed_voltages = allowed_voltages;
|
||||
|
||||
if (pDCTstat->NodePresent) {
|
||||
for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) {
|
||||
if (pDCTstat->DIMMValid & (1 << dimm)) {
|
||||
socket_allowed_voltages &= pDCTstat->DimmSupportedVoltages[dimm];
|
||||
}
|
||||
}
|
||||
|
||||
/* Set voltages */
|
||||
if (socket_allowed_voltages & 0x8) {
|
||||
set_voltage = 0x8;
|
||||
set_ddr3_voltage(socket, 3);
|
||||
} else if (socket_allowed_voltages & 0x4) {
|
||||
set_voltage = 0x4;
|
||||
set_ddr3_voltage(socket, 2);
|
||||
} else if (socket_allowed_voltages & 0x2) {
|
||||
set_voltage = 0x2;
|
||||
set_ddr3_voltage(socket, 1);
|
||||
} else {
|
||||
set_voltage = 0x1;
|
||||
set_ddr3_voltage(socket, 0);
|
||||
}
|
||||
|
||||
/* Save final DIMM voltages for MCT and SMBIOS use */
|
||||
for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) {
|
||||
pDCTstat->DimmConfiguredVoltage[dimm] = set_voltage;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Allow the DDR supply voltages to settle */
|
||||
udelay(100000);
|
||||
}
|
||||
|
||||
static void set_peripheral_control_lines(void) {
|
||||
uint8_t byte;
|
||||
|
||||
/* Enable PCICLK5 */
|
||||
outb(0x41, 0xcd6);
|
||||
outb(0x02, 0xcd7);
|
||||
|
||||
/* Enable the RTC AltCentury register */
|
||||
outb(0x41, 0xcd6);
|
||||
byte = inb(0xcd7);
|
||||
byte |= 0x10;
|
||||
outb(byte, 0xcd7);
|
||||
}
|
||||
|
||||
#ifdef TEST_MEMORY
|
||||
static void execute_memory_test(void)
|
||||
{
|
||||
/* Test DRAM functionality */
|
||||
uint32_t i;
|
||||
uint32_t v;
|
||||
uint32_t w;
|
||||
uint32_t x;
|
||||
uint32_t y;
|
||||
uint32_t z;
|
||||
uint32_t *dataptr;
|
||||
uint32_t readback;
|
||||
uint32_t start = 0x300000;
|
||||
printk(BIOS_DEBUG, "Writing test pattern 1 to memory...\n");
|
||||
for (i = 0; i < 0x1000000; i = i + 8) {
|
||||
dataptr = (void *)(start + i);
|
||||
*dataptr = 0x55555555;
|
||||
dataptr = (void *)(start + i + 4);
|
||||
*dataptr = 0xaaaaaaaa;
|
||||
}
|
||||
printk(BIOS_DEBUG, "Done!\n");
|
||||
printk(BIOS_DEBUG, "Testing memory...\n");
|
||||
for (i = 0; i < 0x1000000; i = i + 8) {
|
||||
dataptr = (void *)(start + i);
|
||||
readback = *dataptr;
|
||||
if (readback != 0x55555555)
|
||||
printk(BIOS_DEBUG, "%p: INCORRECT VALUE %08x (should have been %08x)\n", dataptr, readback, 0x55555555);
|
||||
dataptr = (void *)(start + i + 4);
|
||||
readback = *dataptr;
|
||||
if (readback != 0xaaaaaaaa)
|
||||
printk(BIOS_DEBUG, "%p: INCORRECT VALUE %08x (should have been %08x)\n", dataptr, readback, 0xaaaaaaaa);
|
||||
}
|
||||
printk(BIOS_DEBUG, "Done!\n");
|
||||
printk(BIOS_DEBUG, "Writing test pattern 2 to memory...\n");
|
||||
/* Set up the PRNG seeds for initial write */
|
||||
w = 0x55555555;
|
||||
x = 0xaaaaaaaa;
|
||||
y = 0x12345678;
|
||||
z = 0x87654321;
|
||||
for (i = 0; i < 0x1000000; i = i + 4) {
|
||||
/* Use Xorshift as a PRNG to stress test the bus */
|
||||
v = x;
|
||||
v ^= v << 11;
|
||||
v ^= v >> 8;
|
||||
x = y;
|
||||
y = z;
|
||||
z = w;
|
||||
w ^= w >> 19;
|
||||
w ^= v;
|
||||
dataptr = (void *)(start + i);
|
||||
*dataptr = w;
|
||||
}
|
||||
printk(BIOS_DEBUG, "Done!\n");
|
||||
printk(BIOS_DEBUG, "Testing memory...\n");
|
||||
/* Reset the PRNG seeds for readback */
|
||||
w = 0x55555555;
|
||||
x = 0xaaaaaaaa;
|
||||
y = 0x12345678;
|
||||
z = 0x87654321;
|
||||
for (i = 0; i < 0x1000000; i = i + 4) {
|
||||
/* Use Xorshift as a PRNG to stress test the bus */
|
||||
v = x;
|
||||
v ^= v << 11;
|
||||
v ^= v >> 8;
|
||||
x = y;
|
||||
y = z;
|
||||
z = w;
|
||||
w ^= w >> 19;
|
||||
w ^= v;
|
||||
dataptr = (void *)(start + i);
|
||||
readback = *dataptr;
|
||||
if (readback != w)
|
||||
printk(BIOS_DEBUG, "%p: INCORRECT VALUE %08x (should have been %08x)\n", dataptr, readback, w);
|
||||
}
|
||||
printk(BIOS_DEBUG, "Done!\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
static spinlock_t printk_spinlock CAR_GLOBAL;
|
||||
|
||||
spinlock_t *romstage_console_lock(void)
|
||||
{
|
||||
return car_get_var_ptr(&printk_spinlock);
|
||||
}
|
||||
|
||||
void initialize_romstage_console_lock(void)
|
||||
{
|
||||
spin_unlock(romstage_console_lock());
|
||||
}
|
||||
|
||||
static spinlock_t nvram_cbfs_spinlock CAR_GLOBAL;
|
||||
|
||||
spinlock_t *romstage_nvram_cbfs_lock(void)
|
||||
{
|
||||
return car_get_var_ptr(&nvram_cbfs_spinlock);
|
||||
}
|
||||
|
||||
void initialize_romstage_nvram_cbfs_lock(void)
|
||||
{
|
||||
spin_unlock(romstage_nvram_cbfs_lock());
|
||||
}
|
||||
|
||||
static spinlock_t microcode_cbfs_spinlock CAR_GLOBAL;
|
||||
|
||||
spinlock_t *romstage_microcode_cbfs_lock(void)
|
||||
{
|
||||
return car_get_var_ptr(µcode_cbfs_spinlock);
|
||||
}
|
||||
|
||||
void initialize_romstage_microcode_cbfs_lock(void)
|
||||
{
|
||||
spin_unlock(romstage_microcode_cbfs_lock());
|
||||
}
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
uint32_t esp;
|
||||
__asm__ volatile (
|
||||
"movl %%esp, %0"
|
||||
: "=r" (esp)
|
||||
);
|
||||
|
||||
struct sys_info *sysinfo = get_sysinfo();
|
||||
|
||||
/* Limit the maximum HT speed to 2.6GHz to prevent lockups
|
||||
* due to HT CPU <--> CPU wiring not being validated to 3.2GHz
|
||||
*/
|
||||
sysinfo->ht_link_cfg.ht_speed_limit = 2600;
|
||||
|
||||
uint32_t bsp_apicid = 0, val;
|
||||
uint8_t byte;
|
||||
uint8_t power_on_reset = 0;
|
||||
msr_t msr;
|
||||
|
||||
int s3resume = acpi_is_wakeup_s3();
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
/* Initial timestamp */
|
||||
timestamp_init(timestamp_get());
|
||||
timestamp_add_now(TS_START_ROMSTAGE);
|
||||
|
||||
/* Initialize the printk, nvram CBFS, and microcode CBFS spinlocks */
|
||||
initialize_romstage_console_lock();
|
||||
initialize_romstage_nvram_cbfs_lock();
|
||||
initialize_romstage_microcode_cbfs_lock();
|
||||
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
set_bsp_node_CHtExtNodeCfgEn();
|
||||
enumerate_ht_chain();
|
||||
|
||||
/* SR56x0 pcie bridges block pci_locate_device() before pcie training.
|
||||
* disable all pcie bridges on SR56x0 to work around it
|
||||
*/
|
||||
sr5650_disable_pcie_bridge();
|
||||
|
||||
/* Initialize southbridge */
|
||||
sb7xx_51xx_pci_port80();
|
||||
|
||||
/* Configure secondary serial port pin mux */
|
||||
winbond_set_pinmux(SERIAL_1_DEV, 0x2a, W83667HG_SPI_PINMUX_GPIO4_SERIAL_B_MASK, W83667HG_SPI_PINMUX_SERIAL_B);
|
||||
|
||||
/* Initialize early serial */
|
||||
winbond_enable_serial(SERIAL_0_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
|
||||
/* Disable LPC legacy DMA support to prevent lockup */
|
||||
byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0x78);
|
||||
byte &= ~(1 << 0);
|
||||
pci_write_config8(PCI_DEV(0, 0x14, 3), 0x78, byte);
|
||||
}
|
||||
|
||||
printk(BIOS_SPEW, "Initial stack pointer: %08x\n", esp);
|
||||
|
||||
post_code(0x30);
|
||||
|
||||
if (bist == 0)
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
|
||||
|
||||
post_code(0x32);
|
||||
|
||||
enable_sr5650_dev8();
|
||||
sb7xx_51xx_lpc_init();
|
||||
|
||||
if (CONFIG_MAX_PHYSICAL_CPUS != 2)
|
||||
printk(BIOS_WARNING, "CONFIG_MAX_PHYSICAL_CPUS is %d, but this is a dual socket AMD C32 board!\n", CONFIG_MAX_PHYSICAL_CPUS);
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
val = cpuid_eax(1);
|
||||
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
|
||||
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
|
||||
printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
|
||||
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
|
||||
|
||||
/* Setup sysinfo defaults */
|
||||
set_sysinfo_in_ram(0);
|
||||
|
||||
if (!sb7xx_51xx_decode_last_reset())
|
||||
power_on_reset = 1;
|
||||
|
||||
initialize_mca(1, power_on_reset);
|
||||
update_microcode(val);
|
||||
|
||||
post_code(0x33);
|
||||
|
||||
cpuSetAMDMSR(0);
|
||||
post_code(0x34);
|
||||
|
||||
amd_ht_init(sysinfo);
|
||||
amd_ht_fixup(sysinfo);
|
||||
post_code(0x35);
|
||||
|
||||
/* Setup nodes PCI space and start core 0 AP init. */
|
||||
finalize_node_setup(sysinfo);
|
||||
|
||||
/* Setup any mainboard PCI settings etc. */
|
||||
setup_mb_resource_map();
|
||||
initialize_mca(0, power_on_reset);
|
||||
post_code(0x36);
|
||||
|
||||
/* Wait for all the APs core0 started by finalize_node_setup. */
|
||||
wait_all_core0_started();
|
||||
|
||||
/* run _early_setup before soft-reset. */
|
||||
sr5650_early_setup();
|
||||
sb7xx_51xx_early_setup();
|
||||
|
||||
if (CONFIG(LOGICAL_CPUS)) {
|
||||
/* Core0 on each node is configured. Now setup any additional cores. */
|
||||
printk(BIOS_DEBUG, "start_other_cores()\n");
|
||||
start_other_cores(bsp_apicid);
|
||||
post_code(0x37);
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
}
|
||||
|
||||
if (CONFIG(SET_FIDVID)) {
|
||||
msr = rdmsr(MSR_COFVID_STS);
|
||||
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
|
||||
|
||||
/* FIXME: The sb fid change may survive the warm reset and only need to be done once */
|
||||
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
|
||||
|
||||
post_code(0x39);
|
||||
|
||||
#if CONFIG(SET_FIDVID)
|
||||
if (!warm_reset_detect(0)) { // BSP is node 0
|
||||
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
|
||||
} else {
|
||||
init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
|
||||
}
|
||||
#endif
|
||||
|
||||
post_code(0x3A);
|
||||
|
||||
/* show final fid and vid */
|
||||
msr = rdmsr(MSR_COFVID_STS);
|
||||
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
post_code(0x38);
|
||||
|
||||
init_timer(); // Need to use TMICT to synconize FID/VID
|
||||
|
||||
sr5650_htinit();
|
||||
|
||||
/* Reset for HT, FIDVID, PLL and errata changes to take effect. */
|
||||
if (!warm_reset_detect(0)) {
|
||||
printk(BIOS_INFO, "...WARM RESET...\n\n\n");
|
||||
soft_reset();
|
||||
die("After soft_reset - shouldn't see this message!!!\n");
|
||||
}
|
||||
|
||||
sr5650_htinit_dect_and_enable_isochronous_link();
|
||||
|
||||
/* Set default DDR memory voltage
|
||||
* This will be overridden later during RAM initialization
|
||||
*/
|
||||
set_lpc_sticky_ctl(1); /* Retain LPC/IMC GPIO configuration during S3 sleep */
|
||||
if (!s3resume) { /* Avoid supply voltage glitches while the DIMMs are retaining data */
|
||||
set_ddr3_voltage(0, 0); /* Node 0 */
|
||||
set_ddr3_voltage(1, 0); /* Node 1 */
|
||||
}
|
||||
|
||||
/* Set up peripheral control lines */
|
||||
set_peripheral_control_lines();
|
||||
|
||||
post_code(0x3B);
|
||||
|
||||
/* Wait for all APs to be stopped, otherwise RAM initialization may hang */
|
||||
if (CONFIG(LOGICAL_CPUS))
|
||||
wait_all_other_cores_stopped(bsp_apicid);
|
||||
|
||||
/* It's the time to set ctrl in sysinfo now; */
|
||||
printk(BIOS_DEBUG, "fill_mem_ctrl() detected %d nodes\n", sysinfo->nodes);
|
||||
if (is_fam15h())
|
||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr_fam15);
|
||||
else
|
||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr_fam10);
|
||||
post_code(0x3D);
|
||||
|
||||
#if 0
|
||||
/* FIXME
|
||||
* After the AMD K10 code has been converted to use
|
||||
* CONFIG(DEBUG_SMBUS) uncomment this block
|
||||
*/
|
||||
if (CONFIG(DEBUG_SMBUS)) {
|
||||
dump_spd_registers(&cpu[0]);
|
||||
dump_smbus_registers();
|
||||
}
|
||||
#endif
|
||||
|
||||
post_code(0x40);
|
||||
|
||||
raminit_amdmct(sysinfo);
|
||||
|
||||
#ifdef TEST_MEMORY
|
||||
execute_memory_test();
|
||||
#endif
|
||||
|
||||
if (s3resume)
|
||||
cbmem_initialize();
|
||||
else
|
||||
cbmem_initialize_empty();
|
||||
post_code(0x41);
|
||||
|
||||
romstage_handoff_init(s3resume);
|
||||
|
||||
amdmct_cbmem_store_info(sysinfo);
|
||||
|
||||
printk(BIOS_DEBUG, "disable_spd()\n");
|
||||
switch_spd_mux(0x1);
|
||||
|
||||
sr5650_before_pci_init();
|
||||
sb7xx_51xx_before_pci_init();
|
||||
|
||||
/* Configure SP5100 GPIOs to match vendor settings */
|
||||
pci_write_config16(PCI_DEV(0, 0x14, 0), 0x50, 0x0170);
|
||||
pci_write_config16(PCI_DEV(0, 0x14, 0), 0x54, 0x0707);
|
||||
pci_write_config16(PCI_DEV(0, 0x14, 0), 0x56, 0x0bb0);
|
||||
pci_write_config16(PCI_DEV(0, 0x14, 0), 0x5a, 0x0ff0);
|
||||
}
|
||||
|
||||
/**
|
||||
* BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
|
||||
* Description:
|
||||
* This routine is called every time a non-coherent chain is processed.
|
||||
* BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
|
||||
* swap list. The first part of the list controls the BUID assignment and the
|
||||
* second part of the list provides the device to device linking. Device orientation
|
||||
* can be detected automatically, or explicitly. See documentation for more details.
|
||||
*
|
||||
* Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
|
||||
* based on each device's unit count.
|
||||
*
|
||||
* Parameters:
|
||||
* @param[in] node = The node on which this chain is located
|
||||
* @param[in] link = The link on the host for this chain
|
||||
* @param[out] List = supply a pointer to a list
|
||||
*/
|
||||
BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
|
||||
{
|
||||
/* Force BUID to 0 */
|
||||
static const u8 swaplist[] = {0, 0, 0xFF, 0, 0xFF};
|
||||
if ((node == 0) && (link == 2)) { /* BSP SB link */
|
||||
*List = swaplist;
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -1,46 +0,0 @@
|
||||
====================================================================================================
|
||||
SPD mux
|
||||
====================================================================================================
|
||||
SP5100
|
||||
GPIO 60 GPIO 59
|
||||
Disabled 0 0
|
||||
Normal operation 0 1
|
||||
CPU 0 SPD 1 0
|
||||
CPU 1 SPD 1 1
|
||||
|
||||
====================================================================================================
|
||||
W83795
|
||||
====================================================================================================
|
||||
|
||||
Sensor mappings:
|
||||
CPU_FAN1: FAN1
|
||||
CPU_FAN2: FAN2
|
||||
FRNT_FAN1: FAN3
|
||||
FRNT_FAN2: FAN4
|
||||
FRNT_FAN3: FAN5
|
||||
FRNT_FAN4: FAN6
|
||||
FRNT_FAN5: FAN7
|
||||
REAR_FAN1: FAN8
|
||||
|
||||
====================================================================================================
|
||||
Other hardware
|
||||
====================================================================================================
|
||||
|
||||
RECOVERY1 middle pin is connected to southbridge (AMD SP5100) GPIO 61
|
||||
Normal is HIGH, recovery is LOW.
|
||||
|
||||
+12VSB is generated using a charge pump attached to pin 7 of PU24 (APW7145).
|
||||
|
||||
The +12VSB standby voltage to each bank of DIMMs is switched by a bank of small FETs located close to each RAM power regulator control chip.
|
||||
The +12V primary voltage (lower left pin of the FET placed on the upper left of the control chip of the second node) is also connected to the 232GE located near the PCI slot.
|
||||
|
||||
The control line running to the gates of the +12VSB control FETs is connected to the +5VSB power for the USB ports.
|
||||
That line in turn is connected to +5VSB via the lone P06P03G PMOS transistor on the reverse side of the board, near the center on the lower half.
|
||||
The gate of that transistor is connected via a resistor to the source of the P06P03G PMOS transistor located adjacent to the unpopulated SMA clock header.
|
||||
The gate of that transistor is connected directly to the drain of the small FET directly below it.
|
||||
After that, there's a cascade of small FETs and resistors in that region, eventually leading to SuperIO pin 81.
|
||||
|
||||
SuperIO pin 81 (VSBGATE#) enables the standby voltage rails when set LOW.
|
||||
VSBGATE# is reset on every assertion of PWRGOOD.
|
||||
|
||||
Setting SuperIO LDN 9 CRF4 bits 1 or 0 (or both) to 0 disables NICB.
|
||||
@@ -1,88 +0,0 @@
|
||||
if BOARD_ASUS_KFSN4_DRE
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS
|
||||
def_bool y
|
||||
select CPU_AMD_SOCKET_F_1207
|
||||
select DIMM_DDR2
|
||||
select DIMM_REGISTERED
|
||||
select NORTHBRIDGE_AMD_AMDFAM10
|
||||
select SOUTHBRIDGE_NVIDIA_CK804
|
||||
select SUPERIO_WINBOND_W83627THG
|
||||
select PARALLEL_CPU_INIT
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_CMOS_DEFAULT
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_TABLES
|
||||
select LIFT_BSP_APIC_ID
|
||||
select BOARD_ROMSIZE_KB_1024
|
||||
select ENABLE_APIC_EXT_ID
|
||||
select DRIVERS_I2C_W83793
|
||||
select DRIVERS_XGI_Z9S
|
||||
select POWER_STATE_DEFAULT_ON_AFTER_FAILURE
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default asus/kfsn4-dre
|
||||
|
||||
config BOOTBLOCK_MAINBOARD_INIT
|
||||
string
|
||||
default "mainboard/asus/kfsn4-dre/bootblock.c"
|
||||
|
||||
config DCACHE_RAM_BASE
|
||||
hex
|
||||
default 0xc4000
|
||||
|
||||
config DCACHE_RAM_SIZE
|
||||
hex
|
||||
default 0x0c000
|
||||
|
||||
config APIC_ID_OFFSET
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "KFSN4-DRE"
|
||||
|
||||
config HW_MEM_HOLE_SIZEK
|
||||
hex
|
||||
default 0x100000
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 12
|
||||
|
||||
config MAX_PHYSICAL_CPUS
|
||||
int
|
||||
default 2
|
||||
|
||||
config HT_CHAIN_UNITID_BASE
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
config HT_CHAIN_END_UNITID_BASE
|
||||
hex
|
||||
default 0x20
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 13
|
||||
|
||||
config CK804_PCI_E_X
|
||||
int
|
||||
default 1
|
||||
|
||||
config CK804_PCIE_PME_WAKE
|
||||
bool
|
||||
default y
|
||||
|
||||
config ONBOARD_VGA_IS_PRIMARY
|
||||
bool
|
||||
default y
|
||||
|
||||
config MAX_REBOOT_CNT
|
||||
int
|
||||
default 10
|
||||
|
||||
endif # BOARD_ASUS_KFSN4_DRE
|
||||
@@ -1,2 +0,0 @@
|
||||
config BOARD_ASUS_KFSN4_DRE
|
||||
bool "KFSN4-DRE"
|
||||
@@ -1,16 +0,0 @@
|
||||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
|
||||
romstage-y += resourcemap.c
|
||||
|
||||
ramstage-y += get_bus_conf.c
|
||||
@@ -1,241 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
* Copyright (C) 2010 - 2012 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
|
||||
* Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING: Sleep/Wake is a work in progress and is still somewhat flaky!
|
||||
*/
|
||||
|
||||
/* SuperIO control port */
|
||||
Name (SPIO, 0x2E)
|
||||
|
||||
/* SuperIO control map */
|
||||
OperationRegion (SPIM, SystemIO, SPIO, 0x02)
|
||||
Field (SPIM, ByteAcc, NoLock, Preserve) {
|
||||
INDX, 8,
|
||||
DATA, 8
|
||||
}
|
||||
|
||||
/* SuperIO control registers */
|
||||
IndexField (INDX, DATA, ByteAcc, NoLock, Preserve) {
|
||||
Offset (0x07),
|
||||
CR07, 8, /* Logical device number */
|
||||
Offset (0x2C),
|
||||
CR2C, 8, /* GPIO3 multiplexed pin selection */
|
||||
Offset (0x30),
|
||||
CR30, 8, /* Logical device activation control register */
|
||||
Offset (0xE0),
|
||||
CRE0, 8, /* Wake control register */
|
||||
Offset (0xE6),
|
||||
CRE6, 8, /* Mouse wake event configuration register */
|
||||
Offset (0xF1),
|
||||
CRF1, 8, /* GPIO3 data register */
|
||||
Offset (0xF3),
|
||||
CRF3, 8, /* SUSLED mode register */
|
||||
Offset (0xF6),
|
||||
CRF6, 8, /* SMI/PME event generation control register */
|
||||
Offset (0xF9),
|
||||
CRF9, 8, /* ACPI PME configuration register */
|
||||
}
|
||||
|
||||
/* Southbridge control ports */
|
||||
/* Both are offsets from PM base address (0x2000) */
|
||||
Name (SBC1, 0x2090) /* Offset 0x90 */
|
||||
Name (SBC2, 0x2400) /* Offset 0x400 */
|
||||
|
||||
/* Southbridge control maps */
|
||||
OperationRegion (SBM1, SystemIO, SBC1, 0x10)
|
||||
Field (SBM1, ByteAcc, NoLock, Preserve) {
|
||||
S1CT, 2,
|
||||
Offset (0x04),
|
||||
S3CT, 2,
|
||||
Offset (0x08),
|
||||
S4CT, 2,
|
||||
Offset (0x0C),
|
||||
S5CT, 2,
|
||||
}
|
||||
OperationRegion (SBM2, SystemIO, SBC2, 0x08)
|
||||
Field (SBM2, ByteAcc, NoLock, Preserve) {
|
||||
, 15,
|
||||
PS1S, 1,
|
||||
, 31,
|
||||
PS1E, 1,
|
||||
}
|
||||
|
||||
/* Wake status package */
|
||||
Name(WKST,Package(){Zero, Zero})
|
||||
|
||||
/*
|
||||
* \_WAK System Wake method
|
||||
*
|
||||
* Entry:
|
||||
* Arg0=The value of the sleeping state S1=1, S2=2
|
||||
*
|
||||
* Exit:
|
||||
* Return package of 2 DWords
|
||||
* Dword 1 - Status
|
||||
* 0x00000000 wake succeeded
|
||||
* 0x00000001 Wake was signaled but failed due to lack of power
|
||||
* 0x00000002 Wake was signaled but failed due to thermal condition
|
||||
* Dword 2 - Power Supply state
|
||||
* if non-zero the effective S-state the power supply entered
|
||||
*/
|
||||
Method(\_WAK, 1) {
|
||||
/* Set up LEDs */
|
||||
/* Access SuperIO GPIO3/GPIO4 device */
|
||||
Store(0x87, INDX)
|
||||
Store(0x87, INDX)
|
||||
Store(0x09, CR07)
|
||||
|
||||
/* Set GPIO3 pin 64 (power LED) to GP37 mode */
|
||||
And(CR2C, 0xF3, Local0)
|
||||
Or(Local0, 0x04, CR2C)
|
||||
|
||||
/* Set power LED to steady on */
|
||||
Or(CRF1, 0x80, CRF1)
|
||||
|
||||
/* Restore default SuperIO access */
|
||||
Store(0xAA, INDX)
|
||||
|
||||
/* Configure SuperIO for wake */
|
||||
/* Access SuperIO ACPI device */
|
||||
Store(0x87, INDX)
|
||||
Store(0x87, INDX)
|
||||
Store(0x0A, CR07)
|
||||
|
||||
if (LEqual(Arg0, One)) /* Resuming from power state S1 */
|
||||
{
|
||||
/* Set power management to SMI mode and disable SMI events */
|
||||
And(CRF9, 0xFA, CRF9)
|
||||
|
||||
/* Deactivate the ACPI device */
|
||||
Store(Zero, CR30)
|
||||
|
||||
/* Disable PS/2 SMI/PME events */
|
||||
And(CRF6, 0xCF, CRF6)
|
||||
}
|
||||
if (Lor(LEqual(Arg0, 0x03), LEqual(Arg0, 0x04))) /* Resuming from power state S3 or S4 */
|
||||
{
|
||||
/* Disable PS/2 wake */
|
||||
And(CRE0, 0x1D, CRE0)
|
||||
And(CRE6, 0x7F, CRE6)
|
||||
}
|
||||
|
||||
/* Restore default SuperIO access */
|
||||
Store(0xAA, INDX)
|
||||
|
||||
/* Configure southbridge for wake */
|
||||
Store(Zero, PS1E)
|
||||
Store(0x02, S1CT)
|
||||
Store(0x02, S3CT)
|
||||
Store(0x02, S4CT)
|
||||
Store(0x02, S5CT)
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
|
||||
Return(WKST)
|
||||
} /* End Method(\_WAK) */
|
||||
|
||||
/*
|
||||
* \_PTS - Prepare to Sleep method
|
||||
*
|
||||
* Entry:
|
||||
* Arg0=The value of the sleeping state S1=1, S2=2, etc
|
||||
*
|
||||
* Exit:
|
||||
* -none-
|
||||
*
|
||||
* The _PTS control method is executed at the beginning of the sleep process
|
||||
* for S1-S5. The sleeping value is passed to the _PTS control method. This
|
||||
* control method may be executed a relatively long time before entering the
|
||||
* sleep state and the OS may abort the operation without notification to
|
||||
* the ACPI driver. This method cannot modify the configuration or power
|
||||
* state of any device in the system.
|
||||
*/
|
||||
Method(\_PTS, 1) {
|
||||
/* Set up LEDs */
|
||||
if (LEqual(Arg0, One)) /* Power state S1 requested */
|
||||
{
|
||||
/* Access SuperIO GPIO3/GPIO4 device */
|
||||
Store(0x87, INDX)
|
||||
Store(0x87, INDX)
|
||||
Store(0x09, CR07)
|
||||
|
||||
/* Set GPIO3 pin 64 (power LED) to SUSLED mode */
|
||||
And(CR2C, 0xF3, CR2C)
|
||||
|
||||
/* Set suspend LED to 1Hz toggle pulse with 50% duty cycle */
|
||||
Or(CRF3, 0x80, CRF3)
|
||||
|
||||
/* Restore default SuperIO access */
|
||||
Store(0xAA, INDX)
|
||||
}
|
||||
|
||||
/* Configure SuperIO for sleep */
|
||||
/* Access SuperIO ACPI device */
|
||||
Store(0x87, INDX)
|
||||
Store(0x87, INDX)
|
||||
Store(0x0A, CR07)
|
||||
|
||||
/* Disable PS/2 wakeup and connect PANSW_IN to PANSW_OUT */
|
||||
And(CRE0, 0x1F, CRE0)
|
||||
|
||||
if (LEqual(Arg0, One)) /* Power state S1 requested */
|
||||
{
|
||||
/* Set power management to PME mode and enable PME events */
|
||||
Or(CRF9, 0x05, CRF9)
|
||||
|
||||
/* Activate the ACPI device */
|
||||
Store(One, CR30)
|
||||
|
||||
/* Enable PS/2 keyboard SMI/PME events */
|
||||
And(CRF6, 0xEF, CRF6)
|
||||
|
||||
/* Enable PS/2 keyboard wake */
|
||||
Or(CRE0, 0x40, CRE0)
|
||||
|
||||
/* Enable PS/2 mouse SMI/PME events */
|
||||
And(CRF6, 0xDF, CRF6)
|
||||
|
||||
/* Enable PS/2 mouse wake */
|
||||
Or(CRE0, 0x20, CRE0)
|
||||
}
|
||||
else {
|
||||
/* Enable PS/2 keyboard wake on any keypress */
|
||||
Or(CRE0, 0x41, CRE0)
|
||||
|
||||
/* Enable PS/2 mouse wake on any click */
|
||||
Or(CRE0, 0x22, CRE0)
|
||||
Or(CRE6, 0x80, CRE6)
|
||||
}
|
||||
|
||||
/* Restore default SuperIO access */
|
||||
Store(0xAA, INDX)
|
||||
|
||||
/* Configure southbridge for sleep */
|
||||
Store(One, PS1S)
|
||||
Store(One, PS1E)
|
||||
|
||||
/* On older chips, clear PciExpWakeDisEn */
|
||||
/*if (LLessEqual(\_SB.SBRI, 0x13)) {
|
||||
* Store(0,\_SB.PWDE)
|
||||
*}
|
||||
*/
|
||||
|
||||
/* Clear wake status structure. */
|
||||
Store(0, Index(WKST,0))
|
||||
Store(0, Index(WKST,1))
|
||||
} /* End Method(\_PTS) */
|
||||
@@ -1,74 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* ACPI support
|
||||
* written by Stefan Reinauer <stepan@openbios.org>
|
||||
* (C) 2005 Stefan Reinauer
|
||||
*
|
||||
* Copyright 2005 AMD
|
||||
* 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
|
||||
*
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/pci.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
/* APIC */
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
struct device *dev;
|
||||
struct resource *res;
|
||||
|
||||
/* create all subtables for processors */
|
||||
current = acpi_create_madt_lapics(current);
|
||||
|
||||
/* Write NVIDIA CK804 IOAPIC. */
|
||||
dev = pcidev_on_root(sysconf.sbdn + 0x1, 0);
|
||||
ASSERT(dev != NULL);
|
||||
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_1);
|
||||
ASSERT(res != NULL);
|
||||
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
|
||||
CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS, res->base, 0);
|
||||
|
||||
/* Initialize interrupt mapping if mptable.c didn't. */
|
||||
if (!CONFIG(GENERATE_MP_TABLE)) {
|
||||
/* Copied from mptable.c */
|
||||
/* Enable interrupts for commonly used devices (USB, SATA, etc.) */
|
||||
pci_write_config32(dev, 0x7c, 0x0d800018);
|
||||
pci_write_config32(dev, 0x80, 0xd8002009);
|
||||
pci_write_config32(dev, 0x84, 0x00000001);
|
||||
}
|
||||
|
||||
/* IRQ9 */
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
|
||||
/* IRQ14 */
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 14, 14, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH);
|
||||
/* IRQ15 */
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 15, 15, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH);
|
||||
|
||||
/* create all subtables for processors */
|
||||
/* acpi_create_madt_lapic_nmis returns current, not size. */
|
||||
current = acpi_create_madt_lapic_nmis(current,
|
||||
MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
|
||||
|
||||
return current;
|
||||
}
|
||||
@@ -1,6 +0,0 @@
|
||||
Category: server
|
||||
ROM package: PLCC-32
|
||||
ROM protocol: LPC
|
||||
ROM socketed: y
|
||||
Flashrom support: y
|
||||
Release year: 2007
|
||||
@@ -1,83 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_ops.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
|
||||
#include <superio/winbond/common/winbond.h>
|
||||
#include <superio/winbond/w83627thg/w83627thg.h>
|
||||
|
||||
#define GPIO_DEV PNP_DEV(0x2e, W83627THG_GPIO3)
|
||||
|
||||
#define WINBOND_ENTRY_KEY 0x87
|
||||
#define WINBOND_EXIT_KEY 0xAA
|
||||
|
||||
/* Enable configuration: pass entry key '0x87' into index port dev. */
|
||||
static void pnp_enter_conf_state(pnp_devfn_t dev)
|
||||
{
|
||||
u16 port = dev >> 8;
|
||||
outb(WINBOND_ENTRY_KEY, port);
|
||||
outb(WINBOND_ENTRY_KEY, port);
|
||||
}
|
||||
|
||||
/* Disable configuration: pass exit key '0xAA' into index port dev. */
|
||||
static void pnp_exit_conf_state(pnp_devfn_t dev)
|
||||
{
|
||||
u16 port = dev >> 8;
|
||||
outb(WINBOND_EXIT_KEY, port);
|
||||
}
|
||||
|
||||
uint8_t bootblock_read_recovery_jumper(pnp_devfn_t dev)
|
||||
{
|
||||
uint8_t recovery_enabled = 0;
|
||||
|
||||
pnp_enter_conf_state(dev);
|
||||
pnp_set_logical_device(dev);
|
||||
pnp_set_enable(dev, 1); /* Enable GPIO3 */
|
||||
pnp_write_config(dev, 0xf0, 0xff); /* Set GPIO3 to input */
|
||||
recovery_enabled = !(pnp_read_config(dev, 0xf1) & 0x08); /* Read GP33 */
|
||||
pnp_exit_conf_state(dev);
|
||||
|
||||
return recovery_enabled;
|
||||
}
|
||||
|
||||
void bootblock_mainboard_init(void)
|
||||
{
|
||||
uint8_t recovery_enabled;
|
||||
unsigned char addr;
|
||||
unsigned char byte;
|
||||
|
||||
recovery_enabled = bootblock_read_recovery_jumper(GPIO_DEV);
|
||||
if (recovery_enabled) {
|
||||
#if CONFIG(USE_OPTION_TABLE)
|
||||
/* Clear NVRAM checksum */
|
||||
for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {
|
||||
cmos_write(0x0, addr);
|
||||
}
|
||||
|
||||
/* Set fallback boot */
|
||||
byte = cmos_read(RTC_BOOT_BYTE);
|
||||
byte &= 0xfc;
|
||||
cmos_write(byte, RTC_BOOT_BYTE);
|
||||
#else
|
||||
/* FIXME
|
||||
* Figure out how to recover if the option table is not available
|
||||
*/
|
||||
#endif
|
||||
}
|
||||
}
|
||||
@@ -1,13 +0,0 @@
|
||||
debug_level=Debug
|
||||
multi_core=Enable
|
||||
slow_cpu=off
|
||||
hypertransport_speed_limit=Auto
|
||||
max_mem_clock=DDR2-800
|
||||
ECC_memory=Enable
|
||||
ECC_redirection=Disable
|
||||
ecc_scrub_rate=1.28us
|
||||
interleave_chip_selects=Enable
|
||||
interleave_nodes=Disable
|
||||
interleave_memory_channels=Enable
|
||||
power_on_after_fail=Enable
|
||||
boot_option=Fallback
|
||||
@@ -1,119 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
## Copyright (C) 2007 AMD
|
||||
## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
entries
|
||||
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
393 3 r 0 unused
|
||||
#394 8 unused
|
||||
401 1 e 1 interleave_chip_selects
|
||||
402 1 e 1 interleave_nodes
|
||||
403 1 e 1 interleave_memory_channels
|
||||
404 2 e 8 max_mem_clock
|
||||
406 1 e 2 multi_core
|
||||
412 4 e 6 debug_level
|
||||
416 5 e 10 ecc_scrub_rate
|
||||
440 4 e 9 slow_cpu
|
||||
444 1 e 1 nmi
|
||||
445 1 e 1 gart
|
||||
446 1 e 1 power_on_after_fail
|
||||
456 1 e 1 ECC_memory
|
||||
457 1 e 1 ECC_redirection
|
||||
458 4 e 11 hypertransport_speed_limit
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
6 0 Emergency
|
||||
6 1 Alert
|
||||
6 2 Critical
|
||||
6 3 Error
|
||||
6 4 Warning
|
||||
6 5 Notice
|
||||
6 6 Information
|
||||
6 7 Debug
|
||||
6 8 Spew
|
||||
8 0 DDR2-800
|
||||
8 1 DDR2-667
|
||||
8 2 DDR2-533
|
||||
8 3 DDR2-400
|
||||
9 0 off
|
||||
9 1 87.5%
|
||||
9 2 75.0%
|
||||
9 3 62.5%
|
||||
9 4 50.0%
|
||||
9 5 37.5%
|
||||
9 6 25.0%
|
||||
9 7 12.5%
|
||||
10 0 Disabled
|
||||
10 1 40ns
|
||||
10 2 80ns
|
||||
10 3 160ns
|
||||
10 4 320ns
|
||||
10 5 640ns
|
||||
10 6 1.28us
|
||||
10 7 2.56us
|
||||
10 8 5.12us
|
||||
10 9 10.2us
|
||||
10 10 20.5us
|
||||
10 11 41us
|
||||
10 12 81.9us
|
||||
10 13 163.8us
|
||||
10 14 327.7us
|
||||
10 15 655.4us
|
||||
10 16 1.31ms
|
||||
10 17 2.62ms
|
||||
10 18 5.24ms
|
||||
10 19 10.49ms
|
||||
10 20 20.97ms
|
||||
10 21 42ms
|
||||
10 22 84ms
|
||||
11 0 Auto
|
||||
11 1 2.6GHz
|
||||
11 2 2.4GHz
|
||||
11 3 2.2GHz
|
||||
11 4 2.0GHz
|
||||
11 5 1.8GHz
|
||||
11 6 1.6GHz
|
||||
11 7 1.4GHz
|
||||
11 8 1.2GHz
|
||||
11 9 1.0GHz
|
||||
11 10 800MHz
|
||||
11 11 600MHz
|
||||
11 12 500MHz
|
||||
11 13 400MHz
|
||||
11 14 300MHz
|
||||
11 15 200MHz
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
@@ -1,194 +0,0 @@
|
||||
chip northbridge/amd/amdfam10/root_complex # Root complex
|
||||
device cpu_cluster 0 on # (L)APIC cluster
|
||||
chip cpu/amd/socket_F_1207 # CPU socket
|
||||
device lapic 0 on end # Local APIC of the CPU
|
||||
end
|
||||
end
|
||||
device domain 0 on # PCI domain
|
||||
subsystemid 0x1043 0x8162 inherit
|
||||
chip northbridge/amd/amdfam10 # Northbridge / RAM controller
|
||||
register "maximum_memory_capacity" = "0x1000000000" # 64GB
|
||||
device pci 18.0 on end # Link 0 == LDT 0
|
||||
device pci 18.0 on # Link 1 == LDT 1 [SB on link 1]
|
||||
chip southbridge/nvidia/ck804 # Southbridge
|
||||
device pci 0.0 on end # HT
|
||||
device pci 1.0 on # LPC
|
||||
chip superio/winbond/w83627thg # Super I/O
|
||||
device pnp 2e.0 on # Floppy
|
||||
# Set up interface resources
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 off end # Parallel port
|
||||
device pnp 2e.2 on # Com1
|
||||
# Set up interface resources
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 on # Com2
|
||||
# Set up interface resources
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
# Select correct package I/O pins
|
||||
io 0xf1 = 0x04
|
||||
end
|
||||
device pnp 2e.5 on # PS/2 keyboard & mouse
|
||||
# Set up interface resources
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.7 off end # Game port, MIDI, GPIO 1 & 5
|
||||
device pnp 2e.8 off end # GPIO 2
|
||||
device pnp 2e.9 on end # GPIO 3, GPIO 4
|
||||
device pnp 2e.a off end # ACPI
|
||||
device pnp 2e.b on # Hardware monitor
|
||||
# Set up interface resources
|
||||
io 0x60 = 0x290
|
||||
irq 0x70 = 5
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 1.1 on # SM 0
|
||||
chip drivers/generic/generic # DIMM n-0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM n-0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM n-0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM n-0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM n-1-0-0
|
||||
device i2c 54 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM n-1-0-1
|
||||
device i2c 55 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM n-1-1-0
|
||||
device i2c 56 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM n-1-1-1
|
||||
device i2c 57 on end
|
||||
end
|
||||
chip drivers/i2c/w83793
|
||||
register "mfc" = "0x29" # Enable FANIN1/FANIN12, FANIN9/FANIN10, and FANIN8/FANCTRL8 inputs
|
||||
register "fanin" = "0x7f" # Enable monitoring of FANIN6 - FANIN12
|
||||
register "fanin_sel" = "0x0f" # Connect FANIN9 - FANIN12 to pins 37 - 40
|
||||
register "peci_agent_conf" = "0x33" # Set Intel CPU PECI agent domain (not used by AMD but may affect chip operation)
|
||||
register "tcase0" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation)
|
||||
register "tcase1" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation)
|
||||
register "tcase2" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation)
|
||||
register "tcase3" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation)
|
||||
register "tr_enable" = "0x03" # Enable montoring of TR1 and TR2
|
||||
register "td_mode_select" = "0x05" # Use internal temperature sensors and disable unconnected TD3/TD4
|
||||
register "td1_critical_temperature" = "85" # Set TD1 (CPU0) critical temperature to 85°C
|
||||
register "td1_critical_hysteresis" = "80" # Set TD1 (CPU0) critical hysteresis temperature to 80°C
|
||||
register "td1_warning_temperature" = "70" # Set TD1 (CPU0) warning temperature to 70°C
|
||||
register "td1_warning_hysteresis" = "65" # Set TD1 (CPU0) warning hysteresis temperature to 65°C
|
||||
register "td2_critical_temperature" = "85" # Set TD2 (CPU1) critical temperature to 85°C
|
||||
register "td2_critical_hysteresis" = "80" # Set TD2 (CPU1) critical hysteresis temperature to 80°C
|
||||
register "td2_warning_temperature" = "70" # Set TD2 (CPU1) warning temperature to 70°C
|
||||
register "td2_warning_hysteresis" = "65" # Set TD2 (CPU1) warning hysteresis temperature to 65°C
|
||||
register "tr1_critical_temperature" = "60" # Set TR1 (mainboard) critical temperature to 60°C
|
||||
register "tr1_critical_hysteresis" = "55" # Set TR1 (mainboard) critical hysteresis temperature to 55°C
|
||||
register "tr1_warning_temperature" = "50" # Set TR1 (mainboard) warning temperature to 50°C
|
||||
register "tr1_warning_hysteresis" = "45" # Set TR1 (mainboard) warning hysteresis temperature to 45°C
|
||||
register "critical_temperature" = "80" # Set critical temperature to 80°C
|
||||
register "fanctrl1" = "0x48" # Set Fan 4 and Fan 7 to output buffer mode, all others to open drain
|
||||
register "fanctrl2" = "0x01" # Set Fan 4 to Fan 7 to output buffer mode, Fan 1 to DC mode
|
||||
register "first_valid_fan_number" = "2" # Fan 1/Fan 2 controls and sensors are not connected to anything
|
||||
register "td1_fan_select" = "0x00" # All fans to manual mode (no dependence on TD1)
|
||||
register "td2_fan_select" = "0x00" # All fans to manual mode (no dependence on TD2)
|
||||
register "td3_fan_select" = "0x00" # All fans to manual mode (no dependence on TD3)
|
||||
register "td4_fan_select" = "0x00" # All fans to manual mode (no dependence on TD4)
|
||||
register "tr1_fan_select" = "0x00" # All fans to manual mode (no dependence on TR1)
|
||||
register "tr2_fan_select" = "0x00" # All fans to manual mode (no dependence on TR2)
|
||||
register "fan1_nonstop" = "7" # Set Fan 1 minimum speed
|
||||
register "fan2_nonstop" = "7" # Set Fan 2 minimum speed
|
||||
register "fan3_nonstop" = "7" # Set Fan 3 minimum speed
|
||||
register "fan4_nonstop" = "7" # Set Fan 4 minimum speed
|
||||
register "fan5_nonstop" = "7" # Set Fan 5 minimum speed
|
||||
register "fan6_nonstop" = "7" # Set Fan 6 minimum speed
|
||||
register "fan7_nonstop" = "7" # Set Fan 7 minimum speed
|
||||
register "fan8_nonstop" = "7" # Set Fan 8 minimum speed
|
||||
register "default_speed" = "100" # All fans to full speed on power up
|
||||
register "fan1_duty" = "100" # Fan 1 to full speed
|
||||
register "fan2_duty" = "100" # Fan 2 to full speed
|
||||
register "fan3_duty" = "100" # Fan 3 to full speed
|
||||
register "fan4_duty" = "100" # Fan 4 to full speed
|
||||
register "fan5_duty" = "100" # Fan 5 to full speed
|
||||
register "fan6_duty" = "100" # Fan 6 to full speed
|
||||
register "fan7_duty" = "100" # Fan 7 to full speed
|
||||
register "fan8_duty" = "100" # Fan 8 to full speed
|
||||
register "vcorea_high_limit_mv" = "1500" # VCOREA (Node 0) high limit to 1.5V
|
||||
register "vcorea_low_limit_mv" = "900" # VCOREA (Node 0) low limit to 0.9V
|
||||
register "vcoreb_high_limit_mv" = "1500" # VCOREB (Node 1) high limit to 1.5V
|
||||
register "vcoreb_low_limit_mv" = "900" # VCOREB (Node 1) low limit to 0.9V
|
||||
register "vtt_high_limit_mv" = "1250" # VTT (HT link voltage) high limit to 1.25V
|
||||
register "vtt_low_limit_mv" = "1150" # VTT (HT link voltage) low limit to 1.15V
|
||||
register "vsen1_high_limit_mv" = "1900" # VSEN1 (Node 0 RAM voltage) high limit to 1.9V
|
||||
register "vsen1_low_limit_mv" = "1700" # VSEN1 (Node 0 RAM voltage) low limit to 1.7V
|
||||
register "vsen2_high_limit_mv" = "1900" # VSEN2 (Node 1 RAM voltage) high limit to 1.9V
|
||||
register "vsen2_low_limit_mv" = "1700" # VSEN2 (Node 1 RAM voltage) low limit to 1.7V
|
||||
register "vsen3_high_limit_mv" = "3500" # VSEN3 (+3.3V) high limit to 3.5V
|
||||
register "vsen3_low_limit_mv" = "3100" # VSEN3 (+3.3V) low limit to 3.1V
|
||||
register "vsen4_high_limit_mv" = "1070" # VSEN4 (+12V, scaling factor ~12.15) high limit to 13V
|
||||
register "vsen4_low_limit_mv" = "905" # VSEN4 (+12V, scaling factor ~12.15) low limit to 11V
|
||||
register "vdd_high_limit_mv" = "5200" # 5VDD high limit to 5.2V
|
||||
register "vdd_low_limit_mv" = "4800" # 5VDD low limit to 4.8V
|
||||
register "vsb_high_limit_mv" = "5200" # 5VSB high limit to 5.2V
|
||||
register "vsb_low_limit_mv" = "4800" # 5VSB low limit to 4.8V
|
||||
register "vbat_high_limit_mv" = "3500" # VBAT (+3V) high limit to 3.5V
|
||||
register "vbat_low_limit_mv" = "2500" # VBAT (+3V) low limit to 2.5V
|
||||
device i2c 0x2f on end
|
||||
end
|
||||
end
|
||||
device pci 1.1 on end # SM 1
|
||||
device pci 2.0 on end # USB 1.1
|
||||
device pci 2.1 on end # USB 2
|
||||
device pci 4.0 off end # AC'97 Audio (N/A)
|
||||
device pci 4.1 off end # AC'97 Modem (N/A)
|
||||
device pci 6.0 on end # IDE
|
||||
device pci 7.0 on end # SATA 0
|
||||
device pci 8.0 on end # SATA 1
|
||||
device pci 9.0 on # Bridge
|
||||
device pci 4.0 on end # VGA
|
||||
end
|
||||
device pci a.0 off end
|
||||
device pci b.0 on # Bridge
|
||||
device pci 0.0 on end # NIC A
|
||||
end
|
||||
device pci c.0 on # Bridge
|
||||
device pci 0.0 on end # LSI SAS
|
||||
end
|
||||
device pci d.0 on # Bridge
|
||||
device pci 0.0 on end # NIC B
|
||||
end
|
||||
device pci e.0 on # Bridge
|
||||
# Slot # PCI E 0
|
||||
end
|
||||
device pci f.0 off end
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
register "sata0_enable" = "1"
|
||||
register "sata1_enable" = "1"
|
||||
end
|
||||
end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
device pci 18.4 on end
|
||||
device pci 19.0 on end
|
||||
device pci 19.1 on end
|
||||
device pci 19.2 on end
|
||||
device pci 19.3 on end
|
||||
device pci 19.4 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
@@ -1,948 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
* Copyright (C) 2005 - 2012 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
|
||||
* Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING: Sleep/Wake is a work in progress and is still somewhat flaky!
|
||||
* Everything else does to the best of my knowledge... (T.P. 01/26/2015)
|
||||
*/
|
||||
|
||||
/*
|
||||
* ISA portions taken from QEMU acpi-dsdt.dsl.
|
||||
*/
|
||||
|
||||
/*
|
||||
* PCI link routing templates taken from ck804.asl and modified for this board
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock (
|
||||
"DSDT.AML", /* Output filename */
|
||||
"DSDT", /* Signature */
|
||||
0x02, /* DSDT Revision, needs to be 2 for 64bit */
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x00000001 /* OEM Revision */
|
||||
)
|
||||
{
|
||||
#include <northbridge/amd/amdfam10/amdfam10_util.asl>
|
||||
|
||||
/* Some global data */
|
||||
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
|
||||
Name(OSV, Ones) /* Assume nothing */
|
||||
Name(PICM, One) /* Assume APIC */
|
||||
|
||||
/* HPET control */
|
||||
Name (SHPB, 0xFED00000)
|
||||
Name (SHPL, 0x1000)
|
||||
|
||||
/* Define power states */
|
||||
Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) /* Normal operation */
|
||||
Name (_S1, Package () { 0x01, 0x00, 0x00, 0x00 }) /* Standby */
|
||||
/* Name (_S3, Package () { 0x05, 0x00, 0x00, 0x00 }) */ /* Not supported by hardware */
|
||||
/* Name (_S4, Package () { 0x06, 0x00, 0x00, 0x00 }) */
|
||||
Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 }) /* Hard power off */
|
||||
|
||||
/* The _PIC method is called by the OS to choose between interrupt
|
||||
* routing via the i8259 interrupt controller or the APIC.
|
||||
*
|
||||
* _PIC is called with a parameter of 0 for i8259 configuration and
|
||||
* with a parameter of 1 for Local Apic/IOAPIC configuration.
|
||||
*/
|
||||
Method (_PIC, 1, Serialized) {
|
||||
Store (Arg0, PICM)
|
||||
}
|
||||
|
||||
/* _PR CPU0 is dynamically supplied by SSDT */
|
||||
/* CPU objects and _PSS entries are dynamically supplied by SSDT */
|
||||
|
||||
Scope(\_GPE) { /* Start Scope GPE */
|
||||
/* VGA controller PME# */
|
||||
Method(_L00) {
|
||||
/* Level-Triggered GPE */
|
||||
Notify(\_SB.PCI0.VGAC, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* Keyboard controller PME# */
|
||||
Method(_L03) {
|
||||
/* Level-Triggered GPE */
|
||||
Notify(\_SB.PCI0.LPC.KBD, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.LPC.MOU, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* USB2 PME# */
|
||||
Method(_L05) {
|
||||
/* Level-Triggered GPE */
|
||||
Notify (\_SB.PCI0.USB2, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* Slot PME# */
|
||||
Method(_L0B) {
|
||||
/* Level-Triggered GPE */
|
||||
Notify (\_SB.PCI0.PCIE.SLT1, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PCI0.LSIC.SLT2, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* USB0 PME# */
|
||||
Method(_L0D) {
|
||||
/* Level-Triggered GPE */
|
||||
Notify (\_SB.PCI0.USB0, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* Keyboard controller PME# */
|
||||
Method(_L10) {
|
||||
/* Level-Triggered GPE */
|
||||
Notify(\_SB.PCI0.LPC.KBD, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.LPC.MOU, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* PCIe PME# */
|
||||
Method(_L11) {
|
||||
/* Level-Triggered GPE */
|
||||
Notify (\_SB.PCI0.NICB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PCI0.PCIE, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PCI0.NICA, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PCI0.LSIC, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
} /* End Scope GPE */
|
||||
|
||||
/* Root of the bus hierarchy */
|
||||
Scope (\_SB)
|
||||
{
|
||||
/* Top PCI device (CK804) */
|
||||
Device (PCI0)
|
||||
{
|
||||
/* BUS0 root bus */
|
||||
|
||||
Name (_HID, EisaId ("PNP0A03"))
|
||||
Name (_ADR, 0x00180001)
|
||||
Name (_UID, 0x00)
|
||||
|
||||
Name (HCIN, 0x00) // HC1
|
||||
|
||||
Method (_BBN, 0, NotSerialized)
|
||||
{
|
||||
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
|
||||
}
|
||||
|
||||
/* Operating System Capabilities Method */
|
||||
Method(_OSC,4)
|
||||
{
|
||||
/* Let OS control everything */
|
||||
Return (Arg3)
|
||||
}
|
||||
|
||||
External (BUSN)
|
||||
External (MMIO)
|
||||
External (PCIO)
|
||||
External (SBLK)
|
||||
External (TOM1)
|
||||
External (HCLK)
|
||||
External (SBDN)
|
||||
External (HCDN)
|
||||
External (CBST)
|
||||
|
||||
/* PCI Routing Tables */
|
||||
Name (PR00, Package () {
|
||||
/* PIC */
|
||||
/* ISA Bridge */
|
||||
Package (0x04) { 0x0001FFFF, 0x00, LKSM, 0x00 },
|
||||
|
||||
/* USB */
|
||||
Package (0x04) { 0x0002FFFF, 0x00, LUB0, 0x00 },
|
||||
Package (0x04) { 0x0002FFFF, 0x01, LUB2, 0x00 },
|
||||
|
||||
/* SATA 0 */
|
||||
Package (0x04) { 0x0007FFFF, 0x00, LSA0, 0x00 },
|
||||
|
||||
/* SATA 1 */
|
||||
Package (0x04) { 0x0008FFFF, 0x00, LSA1, 0x00 },
|
||||
|
||||
/* NIC A (Bridge) */
|
||||
Package (0x04) { 0x000BFFFF, 0x00, LNKB, 0x00 },
|
||||
Package (0x04) { 0x000BFFFF, 0x01, LNKC, 0x00 },
|
||||
Package (0x04) { 0x000BFFFF, 0x02, LNKD, 0x00 },
|
||||
Package (0x04) { 0x000BFFFF, 0x03, LNKA, 0x00 },
|
||||
|
||||
/* NIC B (Bridge) */
|
||||
Package (0x04) { 0x000CFFFF, 0x00, LNKA, 0x00 },
|
||||
Package (0x04) { 0x000CFFFF, 0x01, LNKB, 0x00 },
|
||||
Package (0x04) { 0x000CFFFF, 0x02, LNKC, 0x00 },
|
||||
Package (0x04) { 0x000CFFFF, 0x03, LNKD, 0x00 },
|
||||
|
||||
/* LSI SAS Controller (Bridge) */
|
||||
Package (0x04) { 0x000DFFFF, 0x00, LNKD, 0x00 },
|
||||
Package (0x04) { 0x000DFFFF, 0x01, LNKA, 0x00 },
|
||||
Package (0x04) { 0x000DFFFF, 0x02, LNKB, 0x00 },
|
||||
Package (0x04) { 0x000DFFFF, 0x03, LNKC, 0x00 },
|
||||
|
||||
/* PCI-E Slot (Bridge) */
|
||||
Package (0x04) { 0x000EFFFF, 0x00, LNKC, 0x00 },
|
||||
Package (0x04) { 0x000EFFFF, 0x01, LNKD, 0x00 },
|
||||
Package (0x04) { 0x000EFFFF, 0x02, LNKA, 0x00 },
|
||||
Package (0x04) { 0x000EFFFF, 0x03, LNKB, 0x00 },
|
||||
})
|
||||
|
||||
Name (AR00, Package () {
|
||||
/* APIC */
|
||||
/* ISA Bridge */
|
||||
Package (0x04) { 0x0001FFFF, 0x00, LKSM, 0x00 },
|
||||
|
||||
/* USB */
|
||||
Package (0x04) { 0x0002FFFF, 0x00, LUB0, 0x00 },
|
||||
Package (0x04) { 0x0002FFFF, 0x01, LUB2, 0x00 },
|
||||
|
||||
/* SATA 0 */
|
||||
Package (0x04) { 0x0007FFFF, 0x00, LSA0, 0x00 },
|
||||
|
||||
/* SATA 1 */
|
||||
Package (0x04) { 0x0008FFFF, 0x00, LSA1, 0x00 },
|
||||
|
||||
/* NIC A (Bridge) */
|
||||
Package (0x04) { 0x000BFFFF, 0x00, LNIB, 0x00 },
|
||||
Package (0x04) { 0x000BFFFF, 0x01, LNIC, 0x00 },
|
||||
Package (0x04) { 0x000BFFFF, 0x02, LNND, 0x00 },
|
||||
Package (0x04) { 0x000BFFFF, 0x03, LNIA, 0x00 },
|
||||
|
||||
/* NIC B (Bridge) */
|
||||
Package (0x04) { 0x000CFFFF, 0x00, LNIA, 0x00 },
|
||||
Package (0x04) { 0x000CFFFF, 0x01, LNIB, 0x00 },
|
||||
Package (0x04) { 0x000CFFFF, 0x02, LNIC, 0x00 },
|
||||
Package (0x04) { 0x000CFFFF, 0x03, LNND, 0x00 },
|
||||
|
||||
/* LSI SAS Controller (Bridge) */
|
||||
Package (0x04) { 0x000DFFFF, 0x00, LNND, 0x00 },
|
||||
Package (0x04) { 0x000DFFFF, 0x01, LNIA, 0x00 },
|
||||
Package (0x04) { 0x000DFFFF, 0x02, LNIB, 0x00 },
|
||||
Package (0x04) { 0x000DFFFF, 0x03, LNIC, 0x00 },
|
||||
|
||||
/* PCI-E Slot (Bridge) */
|
||||
Package (0x04) { 0x000EFFFF, 0x00, LNIC, 0x00 },
|
||||
Package (0x04) { 0x000EFFFF, 0x01, LNND, 0x00 },
|
||||
Package (0x04) { 0x000EFFFF, 0x02, LNIA, 0x00 },
|
||||
Package (0x04) { 0x000EFFFF, 0x03, LNIB, 0x00 },
|
||||
})
|
||||
|
||||
Name (PR01, Package () {
|
||||
/* PIC */
|
||||
Package (0x04) { 0x0004FFFF, 0x00, LNKA, 0x00 },
|
||||
})
|
||||
|
||||
Name (AR01, Package () {
|
||||
/* APIC */
|
||||
Package (0x04) { 0x0004FFFF, 0x00, LNIA, 0x00 },
|
||||
})
|
||||
|
||||
Name (PR02, Package () {
|
||||
/* PIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, LNKB, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x01, LNKC, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x02, LNKD, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x03, LNKA, 0x00 },
|
||||
})
|
||||
|
||||
Name (AR02, Package () {
|
||||
/* APIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, LNIB, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x01, LNIC, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x02, LNND, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x03, LNIA, 0x00 },
|
||||
})
|
||||
|
||||
Name (PR03, Package () {
|
||||
/* PIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 },
|
||||
})
|
||||
|
||||
Name (AR03, Package () {
|
||||
/* APIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, LNIA, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x01, LNIB, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x02, LNIC, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x03, LNND, 0x00 },
|
||||
})
|
||||
|
||||
Name (PR04, Package () {
|
||||
/* PIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, LNKD, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x01, LNKA, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x02, LNKB, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x03, LNKC, 0x00 },
|
||||
})
|
||||
|
||||
Name (AR04, Package () {
|
||||
/* APIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, LNND, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x01, LNIA, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x02, LNIB, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x03, LNIC, 0x00 },
|
||||
})
|
||||
|
||||
Name (PR05, Package () {
|
||||
/* PIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, LNKC, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x01, LNKD, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x02, LNKA, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x03, LNKB, 0x00 },
|
||||
})
|
||||
|
||||
Name (AR05, Package () {
|
||||
/* APIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, LNIC, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x01, LNND, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x02, LNIA, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x03, LNIB, 0x00 },
|
||||
})
|
||||
|
||||
/* PCI Resource Tables */
|
||||
|
||||
Name (RSIA, ResourceTemplate () {
|
||||
/* PIC */
|
||||
IRQ (Level, ActiveLow, Shared, ) {8}
|
||||
})
|
||||
|
||||
Name (RSMA, ResourceTemplate () {
|
||||
/* APIC */
|
||||
Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {16}
|
||||
})
|
||||
|
||||
Name (RSIB, ResourceTemplate () {
|
||||
/* PIC */
|
||||
IRQ (Level, ActiveLow, Shared, ) {1}
|
||||
})
|
||||
|
||||
Name (RSMB, ResourceTemplate () {
|
||||
/* APIC */
|
||||
Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {17}
|
||||
})
|
||||
|
||||
Name (RSIC, ResourceTemplate () {
|
||||
/* PIC */
|
||||
IRQ (Level, ActiveLow, Shared, ) {2}
|
||||
})
|
||||
|
||||
Name (RSMC, ResourceTemplate () {
|
||||
/* APIC */
|
||||
Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {18}
|
||||
})
|
||||
|
||||
Name (RSND, ResourceTemplate () {
|
||||
/* PIC */
|
||||
IRQ (Level, ActiveLow, Shared, ) {13}
|
||||
})
|
||||
|
||||
Name (RSMD, ResourceTemplate () {
|
||||
/* APIC */
|
||||
Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {19}
|
||||
})
|
||||
|
||||
Name (RSS2, ResourceTemplate ()
|
||||
{
|
||||
/* PIC */
|
||||
IRQ (Level, ActiveLow, Shared, )
|
||||
{3, 4, 5, 7, 9, 10, 11, 12, 14, 15}
|
||||
})
|
||||
|
||||
Name (RSA1, ResourceTemplate ()
|
||||
{
|
||||
/* APIC */
|
||||
IRQ (Level, ActiveLow, Shared, )
|
||||
{3, 4, 5, 6, 7, 10, 11, 12, 14, 15}
|
||||
})
|
||||
|
||||
Method (_CRS, 0, Serialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16,
|
||||
0x0CF8, // Address Range Minimum
|
||||
0x0CF8, // Address Range Maximum
|
||||
0x01, // Address Alignment
|
||||
0x08, // Address Length
|
||||
)
|
||||
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
0x0000, // Address Space Granularity
|
||||
0x0000, // Address Range Minimum
|
||||
0x0CF7, // Address Range Maximum
|
||||
0x0000, // Address Translation Offset
|
||||
0x0CF8, // Address Length
|
||||
,, , TypeStatic)
|
||||
})
|
||||
/* Methods below use SSDT to get actual MMIO regs
|
||||
The IO ports are from 0xd00, optionally an VGA,
|
||||
otherwise the info from MMIO is used.
|
||||
\_SB.GXXX(node, link)
|
||||
*/
|
||||
Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
|
||||
Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
|
||||
Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
|
||||
Return (Local3)
|
||||
}
|
||||
|
||||
#include <southbridge/nvidia/ck804/acpi/ck804.asl>
|
||||
|
||||
/* PCI Routing Table Access */
|
||||
Method (_PRT, 0, NotSerialized) {
|
||||
If (PICM) {
|
||||
Return (AR00)
|
||||
} Else {
|
||||
Return (PR00)
|
||||
}
|
||||
}
|
||||
|
||||
/* USB0 */
|
||||
Device (LUB0)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
|
||||
Name (_UID, 0x05) // _UID: Unique ID
|
||||
|
||||
Method (_STA, 0, Serialized) {
|
||||
If (\_SB.PCI0.LPCB.INTQ) {
|
||||
Return (0xb)
|
||||
} Else {
|
||||
Return (0x9)
|
||||
}
|
||||
}
|
||||
Method (_DIS, 0, Serialized) {
|
||||
Store (0, \_SB.PCI0.LPCB.INTQ)
|
||||
}
|
||||
Method (_PRS, 0, Serialized) {
|
||||
If (PICM) {
|
||||
Return (PRSC)
|
||||
} Else {
|
||||
Return (RSA1)
|
||||
}
|
||||
}
|
||||
Method (_CRS, 0, Serialized) {
|
||||
If (PICM) {
|
||||
Return (CRSC(\_SB.PCI0.LPCB.INTQ))
|
||||
} Else {
|
||||
Return (CRSA(\_SB.PCI0.LPCB.INTQ))
|
||||
}
|
||||
}
|
||||
Method (_SRS, 1, Serialized) {
|
||||
If (PICM) {
|
||||
Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTQ)
|
||||
} Else {
|
||||
Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTQ)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB2 */
|
||||
Device (LUB2)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
|
||||
Name (_UID, 0x07) // _UID: Unique ID
|
||||
|
||||
Method (_STA, 0, Serialized) {
|
||||
If (\_SB.PCI0.LPCB.INTL) {
|
||||
Return (0xb)
|
||||
} Else {
|
||||
Return (0x9)
|
||||
}
|
||||
}
|
||||
Method (_DIS, 0, Serialized) {
|
||||
Store (0, \_SB.PCI0.LPCB.INTL)
|
||||
}
|
||||
Method (_PRS, 0, Serialized) {
|
||||
If (PICM) {
|
||||
Return (PRSC)
|
||||
} Else {
|
||||
Return (RSA1)
|
||||
}
|
||||
}
|
||||
Method (_CRS, 0, Serialized) {
|
||||
If (PICM) {
|
||||
Return (CRSC(\_SB.PCI0.LPCB.INTL))
|
||||
} Else {
|
||||
Return (CRSA(\_SB.PCI0.LPCB.INTL))
|
||||
}
|
||||
}
|
||||
Method (_SRS, 1, Serialized) {
|
||||
If (PICM) {
|
||||
Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTL)
|
||||
} Else {
|
||||
Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTL)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* ISA Bridge */
|
||||
Device (LKSM)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
|
||||
Name (_UID, 0x0C) // _UID: Unique ID
|
||||
|
||||
Method (_STA, 0, Serialized) {
|
||||
If (\_SB.PCI0.LPCB.INTK) {
|
||||
Return (0xb)
|
||||
} Else {
|
||||
Return (0x9)
|
||||
}
|
||||
}
|
||||
Method (_DIS, 0, Serialized) {
|
||||
Store (0, \_SB.PCI0.LPCB.INTK)
|
||||
}
|
||||
Method (_PRS, 0, Serialized) {
|
||||
If (PICM) {
|
||||
Return (RSA1)
|
||||
} Else {
|
||||
Return (RSS2)
|
||||
}
|
||||
}
|
||||
Method (_CRS, 0, Serialized) {
|
||||
If (PICM) {
|
||||
Return (CRSB(\_SB.PCI0.LPCB.INTK))
|
||||
} Else {
|
||||
Return (CRSA(\_SB.PCI0.LPCB.INTK))
|
||||
}
|
||||
}
|
||||
Method (_SRS, 1, Serialized) {
|
||||
If (PICM) {
|
||||
Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTK)
|
||||
} Else {
|
||||
Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTK)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Bridge device link (NIC A) */
|
||||
Device (LNIA)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
|
||||
Name (_UID, 0x10) // _UID: Unique ID
|
||||
|
||||
Method (_STA, 0, Serialized) {
|
||||
If (\_SB.PCI0.LPCB.INTA) {
|
||||
Return (0xb)
|
||||
} Else {
|
||||
Return (0x9)
|
||||
}
|
||||
}
|
||||
Method (_DIS, 0, Serialized) {
|
||||
Store (0, \_SB.PCI0.LPCB.INTA)
|
||||
}
|
||||
Method (_PRS, 0, Serialized) {
|
||||
If (PICM) {
|
||||
Return (RSMA)
|
||||
} Else {
|
||||
Return (RSIA)
|
||||
}
|
||||
}
|
||||
Method (_CRS, 0, Serialized) {
|
||||
If (PICM) {
|
||||
Return (CRSB(\_SB.PCI0.LPCB.INTA))
|
||||
} Else {
|
||||
Return (CRSA(\_SB.PCI0.LPCB.INTA))
|
||||
}
|
||||
}
|
||||
Method (_SRS, 1, Serialized) {
|
||||
If (PICM) {
|
||||
Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTA)
|
||||
} Else {
|
||||
Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTA)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Bridge device link (NIC B) */
|
||||
Device (LNIB)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
|
||||
Name (_UID, 0x11) // _UID: Unique ID
|
||||
|
||||
Method (_STA, 0, Serialized) {
|
||||
If (\_SB.PCI0.LPCB.INTB) {
|
||||
Return (0xb)
|
||||
} Else {
|
||||
Return (0x9)
|
||||
}
|
||||
}
|
||||
Method (_DIS, 0, Serialized) {
|
||||
Store (0, \_SB.PCI0.LPCB.INTB)
|
||||
}
|
||||
Method (_PRS, 0, Serialized) {
|
||||
If (PICM) {
|
||||
Return (RSMB)
|
||||
} Else {
|
||||
Return (RSIB)
|
||||
}
|
||||
}
|
||||
Method (_CRS, 0, Serialized) {
|
||||
If (PICM) {
|
||||
Return (CRSB(\_SB.PCI0.LPCB.INTB))
|
||||
} Else {
|
||||
Return (CRSA(\_SB.PCI0.LPCB.INTB))
|
||||
}
|
||||
}
|
||||
Method (_SRS, 1, Serialized) {
|
||||
If (PICM) {
|
||||
Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTB)
|
||||
} Else {
|
||||
Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTB)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Bridge device link */
|
||||
Device (LNIC)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
|
||||
Name (_UID, 0x12) // _UID: Unique ID
|
||||
|
||||
Method (_STA, 0, Serialized) {
|
||||
If (\_SB.PCI0.LPCB.INTC) {
|
||||
Return (0xb)
|
||||
} Else {
|
||||
Return (0x9)
|
||||
}
|
||||
}
|
||||
Method (_DIS, 0, Serialized) {
|
||||
Store (0, \_SB.PCI0.LPCB.INTC)
|
||||
}
|
||||
Method (_PRS, 0, Serialized) {
|
||||
If (PICM) {
|
||||
Return (RSMC)
|
||||
} Else {
|
||||
Return (RSIC)
|
||||
}
|
||||
}
|
||||
Method (_CRS, 0, Serialized) {
|
||||
If (PICM) {
|
||||
Return (CRSB(\_SB.PCI0.LPCB.INTC))
|
||||
} Else {
|
||||
Return (CRSA(\_SB.PCI0.LPCB.INTC))
|
||||
}
|
||||
}
|
||||
Method (_SRS, 1, Serialized) {
|
||||
If (PICM) {
|
||||
Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTC)
|
||||
} Else {
|
||||
Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTC)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Bridge device link */
|
||||
Device (LNND)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
|
||||
Name (_UID, 0x13) // _UID: Unique ID
|
||||
|
||||
Method (_STA, 0, Serialized) {
|
||||
If (\_SB.PCI0.LPCB.INTD) {
|
||||
Return (0xb)
|
||||
} Else {
|
||||
Return (0x9)
|
||||
}
|
||||
}
|
||||
Method (_DIS, 0, Serialized) {
|
||||
Store (0, \_SB.PCI0.LPCB.INTD)
|
||||
}
|
||||
Method (_PRS, 0, Serialized) {
|
||||
If (PICM) {
|
||||
Return (RSMD)
|
||||
} Else {
|
||||
Return (RSND)
|
||||
}
|
||||
}
|
||||
Method (_CRS, 0, Serialized) {
|
||||
If (PICM) {
|
||||
Return (CRSB(\_SB.PCI0.LPCB.INTD))
|
||||
} Else {
|
||||
Return (CRSA(\_SB.PCI0.LPCB.INTD))
|
||||
}
|
||||
}
|
||||
Method (_SRS, 1, Serialized) {
|
||||
If (PICM) {
|
||||
Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTD)
|
||||
} Else {
|
||||
Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTD)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* 0:02.0 CK804 USB 0 */
|
||||
Device (USB0)
|
||||
{
|
||||
Name (_ADR, 0x00020000) // _ADR: Address
|
||||
Name(_PRW, Package () {0x0D, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
|
||||
/* 0:02.0 CK804 USB 2 */
|
||||
Device (USB2)
|
||||
{
|
||||
Name (_ADR, 0x00020001) // _ADR: Address
|
||||
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
|
||||
/* 1:04.0 VGA Controller */
|
||||
Device (VGAC)
|
||||
{
|
||||
Name (_ADR, 0x00090000) // _ADR: Address
|
||||
Name(_PRW, Package () {0x00, 0x04}) // Wake from S1-S4
|
||||
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
||||
{
|
||||
If (PICM) {
|
||||
Return (AR01)
|
||||
} Else {
|
||||
Return (PR01)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* 2:00.0 PCIe NIC A */
|
||||
Device (NICA)
|
||||
{
|
||||
Name (_ADR, 0x000B0000) // _ADR: Address
|
||||
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
|
||||
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
||||
{
|
||||
If (PICM) {
|
||||
Return (AR02)
|
||||
} Else {
|
||||
Return (PR02)
|
||||
}
|
||||
}
|
||||
Device (BDC1)
|
||||
{
|
||||
Name (_ADR, Zero) // _ADR: Address
|
||||
}
|
||||
}
|
||||
|
||||
/* 3:00.0 PCIe NIC B */
|
||||
Device (NICB)
|
||||
{
|
||||
Name (_ADR, 0x000C0000) // _ADR: Address
|
||||
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
|
||||
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
||||
{
|
||||
If (PICM) {
|
||||
Return (AR03)
|
||||
} Else {
|
||||
Return (PR03)
|
||||
}
|
||||
}
|
||||
Device (BDC2)
|
||||
{
|
||||
Name (_ADR, Zero) // _ADR: Address
|
||||
}
|
||||
}
|
||||
|
||||
/* 4:00.0 PCIe LSI SAS Controller */
|
||||
Device (LSIC)
|
||||
{
|
||||
Name (_ADR, 0x000D0000) // _ADR: Address
|
||||
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
|
||||
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
||||
{
|
||||
If (PICM) {
|
||||
Return (AR04)
|
||||
} Else {
|
||||
Return (PR04)
|
||||
}
|
||||
}
|
||||
|
||||
Device (SLT2)
|
||||
{
|
||||
Name (_ADR, 0xFFFF) // _ADR: Address
|
||||
Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
}
|
||||
|
||||
/* 5:00.0 PCIe x16 */
|
||||
Device (PCIE)
|
||||
{
|
||||
Name (_ADR, 0x000E0000) // _ADR: Address
|
||||
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
|
||||
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
||||
{
|
||||
If (PICM) {
|
||||
Return (AR05)
|
||||
} Else {
|
||||
Return (PR05)
|
||||
}
|
||||
}
|
||||
Device (SLT1)
|
||||
{
|
||||
Name (_ADR, 0xFFFF) // _ADR: Address
|
||||
Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
}
|
||||
|
||||
Device (LPC) {
|
||||
Name (_HID, EisaId ("PNP0A05"))
|
||||
Name (_ADR, 0x00010000)
|
||||
|
||||
/* PS/2 keyboard (seems to be important for WinXP install) */
|
||||
Device (KBD)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0303"))
|
||||
Name (_CID, EisaId ("PNP030B"))
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0f)
|
||||
}
|
||||
Method (_CRS, 0, Serialized)
|
||||
{
|
||||
Name (TMP, ResourceTemplate () {
|
||||
IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
|
||||
IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
|
||||
IRQNoFlags () {1}
|
||||
})
|
||||
Return (TMP)
|
||||
}
|
||||
}
|
||||
|
||||
/* PS/2 mouse */
|
||||
Device (MOU)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0F03"))
|
||||
Name (_CID, EisaId ("PNP0F13"))
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0f)
|
||||
}
|
||||
Method (_CRS, 0, Serialized)
|
||||
{
|
||||
Name (TMP, ResourceTemplate () {
|
||||
IRQNoFlags () {12}
|
||||
})
|
||||
Return (TMP)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* UART 1 */
|
||||
Device (URT1)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART
|
||||
Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0f) // Always enable
|
||||
}
|
||||
Name (_PRS, ResourceTemplate() {
|
||||
StartDependentFn(0, 1) {
|
||||
IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
|
||||
IRQNoFlags() { 4 }
|
||||
} EndDependentFn()
|
||||
})
|
||||
Method (_CRS, 0)
|
||||
{
|
||||
Return(ResourceTemplate() {
|
||||
IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
|
||||
IRQNoFlags() { 4 }
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
/* UART 2 */
|
||||
Device (URT2)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART
|
||||
Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0f) // Always enable
|
||||
}
|
||||
Name (_PRS, ResourceTemplate() {
|
||||
StartDependentFn(0, 1) {
|
||||
IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
|
||||
IRQNoFlags() { 3 }
|
||||
} EndDependentFn()
|
||||
})
|
||||
Method (_CRS, 0)
|
||||
{
|
||||
Return(ResourceTemplate() {
|
||||
IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
|
||||
IRQNoFlags() { 3 }
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
/* Floppy controller */
|
||||
Device (FDC0)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0700"))
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0f)
|
||||
}
|
||||
Method (_CRS, 0, Serialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate () {
|
||||
FixedIO (0x03F0, 0x08)
|
||||
IRQNoFlags () {6}
|
||||
DMA (Compatibility, NotBusMaster, Transfer8) {2}
|
||||
})
|
||||
Return (BUF0)
|
||||
}
|
||||
}
|
||||
Device (HPET)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0103"))
|
||||
Name (CRS, ResourceTemplate ()
|
||||
{
|
||||
Memory32Fixed (ReadOnly,
|
||||
0x00000000,
|
||||
0x00001000,
|
||||
_Y02)
|
||||
IRQNoFlags () {0}
|
||||
IRQNoFlags () {8}
|
||||
})
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0F)
|
||||
}
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._BAS, HPT1)
|
||||
CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._LEN, HPT2)
|
||||
Store (SHPB, HPT1)
|
||||
Store (SHPL, HPT2)
|
||||
Return (CRS)
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Device (PWRB) { /* Start Power button device */
|
||||
Name(_HID, EISAID("PNP0C0C"))
|
||||
Name(_UID, 0xAA)
|
||||
Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
|
||||
Name(_STA, 0x0B) /* sata is invisible */
|
||||
}
|
||||
}
|
||||
|
||||
#include "acpi/pm_ctrl.asl"
|
||||
|
||||
}
|
||||
@@ -1,85 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
* Copyright (C) 2007 AMD
|
||||
* (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
|
||||
* Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
|
||||
* (Thanks to LSRA University of Mannheim for their support)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <cpu/amd/multicore.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
/*
|
||||
* Global variables for MB layouts and these will be shared by irqtable,
|
||||
* mptable and acpi_tables.
|
||||
*/
|
||||
/* busnum is default */
|
||||
unsigned char bus_ck804[6];
|
||||
unsigned int apicid_ck804;
|
||||
|
||||
void get_bus_conf(void)
|
||||
{
|
||||
unsigned int apicid_base, sbdn;
|
||||
struct device *dev;
|
||||
int i;
|
||||
|
||||
get_default_pci1234(32);
|
||||
|
||||
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
|
||||
sbdn = sysconf.sbdn;
|
||||
|
||||
for (i = 0; i < 6; i++)
|
||||
bus_ck804[i] = 0;
|
||||
|
||||
/* CK804 */
|
||||
dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x09, 0));
|
||||
if (dev) {
|
||||
bus_ck804[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804[2]++;
|
||||
} else {
|
||||
printk
|
||||
(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n",
|
||||
sbdn + 0x09);
|
||||
bus_ck804[1] = 2;
|
||||
bus_ck804[2] = 3;
|
||||
}
|
||||
|
||||
for (i = 2; i < 6; i++) {
|
||||
dev = dev_find_slot(bus_ck804[0],
|
||||
PCI_DEVFN(sbdn + 0x0b + i - 2, 0));
|
||||
if (dev) {
|
||||
bus_ck804[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
|
||||
bus_ck804[0], sbdn + 0x0b + i - 2);
|
||||
}
|
||||
}
|
||||
|
||||
if (CONFIG(LOGICAL_CPUS)) {
|
||||
apicid_base = get_apicid_base(1);
|
||||
printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 1: apicid_base: %08x\n", apicid_base);
|
||||
}
|
||||
else {
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 0: apicid_base: %08x\n", apicid_base);
|
||||
}
|
||||
apicid_ck804 = apicid_base + 0;
|
||||
}
|
||||
@@ -1,175 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
*
|
||||
* Copyright (C) 2007 AMD
|
||||
* (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
|
||||
* Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
|
||||
* (Thanks to LSRA University of Mannheim for their support)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
// WARNING
|
||||
// These tables are INVALID for this mainboard!
|
||||
// The ACPI tables are correct; a backport to these PIR tables is needed...
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
extern unsigned char bus_ck804[6];
|
||||
|
||||
|
||||
/**
|
||||
* Add one line to IRQ table.
|
||||
*/
|
||||
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
|
||||
uint8_t devfn, uint8_t link0, uint16_t bitmap0,
|
||||
uint8_t link1, uint16_t bitmap1, uint8_t link2,
|
||||
uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
|
||||
uint8_t slot, uint8_t rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
/**
|
||||
* Create the IRQ routing table.
|
||||
* Values are derived from getpir generated code.
|
||||
*/
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
unsigned int slot_num, sbdn;
|
||||
uint8_t *v, sum = 0;
|
||||
int i;
|
||||
|
||||
sbdn = sysconf.sbdn;
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be between 0xf0000 & 0x100000. */
|
||||
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (uint8_t *)(addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
pirq->rtr_bus = bus_ck804[0];
|
||||
pirq->rtr_devfn = PCI_DEVFN(sbdn + 9, 0);
|
||||
pirq->exclusive_irqs = 0x828;
|
||||
pirq->rtr_vendor = 0x10de;
|
||||
pirq->rtr_device = 0x005c;
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *)(&pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
|
||||
/* Slot1 PCIE 16x */
|
||||
write_pirq_info(pirq_info, bus_ck804[1], PCI_DEVFN(0, 0), 0x3, 0xdeb8, 0x4,
|
||||
0xdeb8, 0x1, 0xdeb8, 0x2, 0xdeb8, 4, 0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
|
||||
|
||||
/* Slot2 PCIE 1x */
|
||||
write_pirq_info(pirq_info, bus_ck804[2], PCI_DEVFN(0, 0), 0x4, 0xdeb8, 0x1,
|
||||
0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 5, 0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
|
||||
/* Slot3 PCIE 1x */
|
||||
write_pirq_info(pirq_info, bus_ck804[3], PCI_DEVFN(0, 0), 0x1, 0xdeb8, 0x2,
|
||||
0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 6, 0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
|
||||
/* Slot4 PCIE 4x */
|
||||
write_pirq_info(pirq_info, bus_ck804[4], PCI_DEVFN(0x4, 0), 0x2,
|
||||
0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8, 7, 0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
|
||||
/* Slot5 - Slot7 PCI */
|
||||
for (i = 0; i < 3; i++) {
|
||||
write_pirq_info(pirq_info, bus_ck804[5], (0 << (6 + i)) | 0,
|
||||
((i + 0) % 4) + 1, 0xdeb8,
|
||||
((i + 1) % 4) + 1, 0xdeb8,
|
||||
((i + 2) % 4) + 1, 0xdeb8,
|
||||
((i + 3) % 4) + 1, 0xdeb8, i, 0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
}
|
||||
|
||||
/* PCI bridge */
|
||||
write_pirq_info(pirq_info, bus_ck804[0], PCI_DEVFN(sbdn + 9, 0), 0x1,
|
||||
0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0, 0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
|
||||
/* SMBus */
|
||||
write_pirq_info(pirq_info, bus_ck804[0], PCI_DEVFN(sbdn + 1, 0), 0x2,
|
||||
0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
|
||||
/* USB */
|
||||
write_pirq_info(pirq_info, bus_ck804[0], PCI_DEVFN(sbdn + 2, 0), 0x1,
|
||||
0xdeb8, 0x2, 0xdeb8, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
|
||||
/* SATA */
|
||||
write_pirq_info(pirq_info, bus_ck804[0], PCI_DEVFN(sbdn + 7, 0), 0x1,
|
||||
0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
|
||||
/* SATA */
|
||||
write_pirq_info(pirq_info, bus_ck804[0], PCI_DEVFN(sbdn + 8, 0), 0x1,
|
||||
0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
if (sum != pirq->checksum)
|
||||
pirq->checksum = sum;
|
||||
|
||||
printk(BIOS_INFO, "done.\n");
|
||||
|
||||
return (unsigned long)pirq_info;
|
||||
}
|
||||
@@ -1,151 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
* Copyright (C) 2007 AMD
|
||||
* (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
|
||||
* Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
|
||||
* (Thanks to LSRA University of Mannheim for their support)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
// WARNING
|
||||
// These tables are INCOMPLETE for this mainboard!
|
||||
// The ACPI tables are correct; a backport to these MP tables is needed...
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <stdint.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
extern unsigned char bus_ck804[6];
|
||||
extern unsigned int apicid_ck804;
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
unsigned int sbdn;
|
||||
int bus_isa;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
sbdn = sysconf.sbdn;
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
{
|
||||
struct device *dev;
|
||||
struct resource *res;
|
||||
|
||||
dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_1);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_ck804, 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
|
||||
/* Initialize interrupt mapping. */
|
||||
|
||||
/*
|
||||
LPC bridge PCI config registers:
|
||||
|
||||
0x7c:0x0000ffff
|
||||
- bitmap of masked pci irqs?
|
||||
- PIRQ[ABCD] possibly?
|
||||
|
||||
0x7c:0x00f00000
|
||||
- sata at f8 - port 1
|
||||
|
||||
0x7c:0x0f000000
|
||||
- sata at f7 - port 1
|
||||
|
||||
0x80:0xf0000000
|
||||
- sata at f7 - port 0
|
||||
|
||||
0x80:0x0f000000
|
||||
- sata at f8 - port 0
|
||||
|
||||
0x80:0x0000f000
|
||||
- EHCI
|
||||
|
||||
0x84:0x00000f00
|
||||
- NIC
|
||||
|
||||
0x84:0x0000000f
|
||||
- OHCI
|
||||
|
||||
known values of nibbles:
|
||||
|
||||
0 - unrouted?
|
||||
1 - irq 23
|
||||
8 - irq 20
|
||||
c - irq 12
|
||||
d - irq 21
|
||||
e - irq 14
|
||||
f - irq 15
|
||||
*/
|
||||
|
||||
// Enable interrupts for commonly used devices (USB, SATA, etc.)
|
||||
pci_write_config32(dev, 0x7c, 0x0d800018);
|
||||
pci_write_config32(dev, 0x80, 0xd8002009);
|
||||
pci_write_config32(dev, 0x84, 0x00000001);
|
||||
}
|
||||
}
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0);
|
||||
|
||||
// Onboard ck804 smbus
|
||||
smp_write_pci_intsrc(mc, mp_INT,
|
||||
bus_ck804[0], sbdn + 1, 1, apicid_ck804,
|
||||
0xa);
|
||||
|
||||
// Onboard ck804 USB 1.1
|
||||
smp_write_pci_intsrc(mc, mp_INT,
|
||||
bus_ck804[0], sbdn + 2, 0, apicid_ck804,
|
||||
0x15);
|
||||
|
||||
// Onboard ck804 USB 2
|
||||
smp_write_pci_intsrc(mc, mp_INT,
|
||||
bus_ck804[0], sbdn + 2, 1, apicid_ck804,
|
||||
0x14);
|
||||
|
||||
// Onboard ck804 SATA 0
|
||||
smp_write_pci_intsrc(mc, mp_INT,
|
||||
bus_ck804[0], sbdn + 7, 0, apicid_ck804,
|
||||
0x17);
|
||||
|
||||
// Onboard ck804 SATA 1
|
||||
smp_write_pci_intsrc(mc, mp_INT,
|
||||
bus_ck804[0], sbdn + 8, 0, apicid_ck804,
|
||||
0x16);
|
||||
|
||||
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
mptable_lintsrc(mc, bus_ck804[0]);
|
||||
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums. */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
@@ -1,283 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
*
|
||||
* Copyright (C) 2007 AMD
|
||||
* Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <commonlib/helpers.h>
|
||||
#include <northbridge/amd/amdfam10/amdfam10.h>
|
||||
|
||||
void setup_mb_resource_map(void)
|
||||
{
|
||||
static const unsigned int register_values[] = {
|
||||
/* Careful set limit registers before base registers which contain the enables */
|
||||
/* DRAM Limit i Registers
|
||||
* F1:0x44 i = 0
|
||||
* F1:0x4C i = 1
|
||||
* F1:0x54 i = 2
|
||||
* F1:0x5C i = 3
|
||||
* F1:0x64 i = 4
|
||||
* F1:0x6C i = 5
|
||||
* F1:0x74 i = 6
|
||||
* F1:0x7C i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 3] Reserved
|
||||
* [10: 8] Interleave select
|
||||
* specifies the values of A[14:12] to use with interleave enable.
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Limit Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40 bit address
|
||||
* that define the end of the DRAM region.
|
||||
*/
|
||||
// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000,
|
||||
ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001,
|
||||
ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002,
|
||||
ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003,
|
||||
ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004,
|
||||
ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005,
|
||||
ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006,
|
||||
ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
|
||||
|
||||
/* DRAM Base i Registers
|
||||
* F1:0x40 i = 0
|
||||
* F1:0x48 i = 1
|
||||
* F1:0x50 i = 2
|
||||
* F1:0x58 i = 3
|
||||
* F1:0x60 i = 4
|
||||
* F1:0x68 i = 5
|
||||
* F1:0x70 i = 6
|
||||
* F1:0x78 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 7: 2] Reserved
|
||||
* [10: 8] Interleave Enable
|
||||
* 000 = No interleave
|
||||
* 001 = Interleave on A[12] (2 nodes)
|
||||
* 010 = reserved
|
||||
* 011 = Interleave on A[12] and A[14] (4 nodes)
|
||||
* 100 = reserved
|
||||
* 101 = reserved
|
||||
* 110 = reserved
|
||||
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Base Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40-bit address
|
||||
* that define the start of the DRAM region.
|
||||
*/
|
||||
// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
* F1:0x8C i = 1
|
||||
* F1:0x94 i = 2
|
||||
* F1:0x9C i = 3
|
||||
* F1:0xA4 i = 4
|
||||
* F1:0xAC i = 5
|
||||
* F1:0xB4 i = 6
|
||||
* F1:0xBC i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Reserved
|
||||
* [ 6: 6] Reserved
|
||||
* [ 7: 7] Non-Posted
|
||||
* 0 = CPU writes may be posted
|
||||
* 1 = CPU writes must be non-posted
|
||||
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
|
||||
* This field defines the upp address bits of a 40-bit address that
|
||||
* defines the end of a memory-mapped I/O region n
|
||||
*/
|
||||
ADDRMAP_REG(0x84), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x8C), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x94), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x9C), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xA4), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xAC), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xBC), 0x00000048, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Base i Registers
|
||||
* F1:0x80 i = 0
|
||||
* F1:0x88 i = 1
|
||||
* F1:0x90 i = 2
|
||||
* F1:0x98 i = 3
|
||||
* F1:0xA0 i = 4
|
||||
* F1:0xA8 i = 5
|
||||
* F1:0xB0 i = 6
|
||||
* F1:0xB8 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Cpu Disable
|
||||
* 0 = Cpu can use this I/O range
|
||||
* 1 = Cpu requests do not use this I/O range
|
||||
* [ 3: 3] Lock
|
||||
* 0 = base/limit registers i are read/write
|
||||
* 1 = base/limit registers i are read-only
|
||||
* [ 7: 4] Reserved
|
||||
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
|
||||
* This field defines the upper address bits of a 40bit address
|
||||
* that defines the start of memory-mapped I/O region i
|
||||
*/
|
||||
ADDRMAP_REG(0x80), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x88), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x90), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x98), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xB8), 0x000000f0, 0x00000000,
|
||||
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
* F1:0xCC i = 1
|
||||
* F1:0xD4 i = 2
|
||||
* F1:0xDC i = 3
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = reserved
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Limit Address i
|
||||
* This field defines the end of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> Nvidia CK 804 */
|
||||
ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000,
|
||||
ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000,
|
||||
ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
|
||||
|
||||
/* PCI I/O Base i Registers
|
||||
* F1:0xC0 i = 0
|
||||
* F1:0xC8 i = 1
|
||||
* F1:0xD0 i = 2
|
||||
* F1:0xD8 i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 3: 2] Reserved
|
||||
* [ 4: 4] VGA Enable
|
||||
* 0 = VGA matches Disabled
|
||||
* 1 = matches all address < 64K and where A[9:0] is in the
|
||||
* range 3B0-3BB or 3C0-3DF independent of the base & limit registers
|
||||
* [ 5: 5] ISA Enable
|
||||
* 0 = ISA matches Disabled
|
||||
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
|
||||
* from matching agains this base/limit pair
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Base i
|
||||
* This field defines the start of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001013,
|
||||
ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000,
|
||||
ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000,
|
||||
ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
|
||||
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
* F1:0xE8 i = 2
|
||||
* F1:0xEC i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Device Number Compare Enable
|
||||
* 0 = The ranges are based on bus number
|
||||
* 1 = The ranges are ranges of devices on bus 0
|
||||
* [ 3: 3] Reserved
|
||||
* [ 6: 4] Destination Node
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 7] Reserved
|
||||
* [ 9: 8] Destination Link
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 - Reserved
|
||||
* [15:10] Reserved
|
||||
* [23:16] Bus Number Base i
|
||||
* This field defines the lowest bus number in configuration region i
|
||||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration region i
|
||||
*/
|
||||
ADDRMAP_REG(0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> Nvidia CK 804 */
|
||||
ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000,
|
||||
ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000,
|
||||
ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
|
||||
|
||||
};
|
||||
|
||||
int max;
|
||||
max = ARRAY_SIZE(register_values);
|
||||
setup_resource_map(register_values, max);
|
||||
}
|
||||
@@ -1,372 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
*
|
||||
* Copyright (C) 2007 AMD
|
||||
* Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pnp_ops.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <console/console.h>
|
||||
#include <timestamp.h>
|
||||
#include <spd.h>
|
||||
#include <cbmem.h>
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
#include <cpu/amd/car.h>
|
||||
#include <cpu/amd/msr.h>
|
||||
#include <southbridge/amd/common/reset.h>
|
||||
#include <southbridge/nvidia/ck804/early_smbus.h>
|
||||
#include <delay.h>
|
||||
#include <superio/winbond/common/winbond.h>
|
||||
#include <superio/winbond/w83627thg/w83627thg.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include <northbridge/amd/amdht/ht_wrapper.h>
|
||||
#include <northbridge/amd/amdfam10/raminit.h>
|
||||
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
|
||||
|
||||
#include "cpu/amd/quadcore/quadcore.c"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
|
||||
|
||||
#define CK804_MB_SETUP \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+33, ~(0x0f),(0x04 | 0x01), /* -ENOINFO Proprietary BIOS sets this register; "When in Rome..."*/
|
||||
|
||||
#include <southbridge/nvidia/ck804/early_setup_ss.h>
|
||||
#include "southbridge/nvidia/ck804/early_setup_car.c"
|
||||
|
||||
#define GPIO3_DEV PNP_DEV(0x2e, W83627THG_GPIO3)
|
||||
|
||||
int spd_read_byte(unsigned int device, unsigned int address);
|
||||
|
||||
int spd_read_byte(unsigned int device, unsigned int address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get SouthBridge device number
|
||||
* @param[in] bus target bus number
|
||||
* @return southbridge device number
|
||||
*/
|
||||
unsigned int get_sbdn(unsigned int bus)
|
||||
{
|
||||
pci_devfn_t dev;
|
||||
|
||||
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
|
||||
PCI_DEVICE_ID_NVIDIA_CK804_PRO), bus);
|
||||
return (dev >> 15) & 0x1f;
|
||||
}
|
||||
|
||||
/*
|
||||
* ASUS KFSN4-DRE specific SPD enable/disable magic.
|
||||
*
|
||||
* Setting CK804 GPIO43 and GPIO44 to 0 and 0 respectively will make the
|
||||
* board DIMMs accessible at SMBus/SPD offsets 0x50-0x53. Per default the SPD
|
||||
* offsets 0x50-0x53 are _not_ readable (all SPD reads will return 0xff) which
|
||||
* will make RAM init fail.
|
||||
*
|
||||
* Disable SPD access after RAM init to allow access to standard SMBus/I2C offsets
|
||||
* which is required e.g. by lm-sensors.
|
||||
*/
|
||||
|
||||
#define CK804_BOARD_BOOT_BASE_UNIT_UID 1
|
||||
|
||||
static const unsigned int ctrl_conf_enable_spd_node0[] = {
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x00),/* W2,GPIO43, U6 input S0*/
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x00),/* W3,GPIO44, U6 input S1*/
|
||||
};
|
||||
|
||||
static const unsigned int ctrl_conf_enable_spd_node1[] = {
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x00),/* W2,GPIO43, U6 input S0*/
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x01),/* W3,GPIO44, U6 input S1*/
|
||||
};
|
||||
|
||||
static const unsigned int ctrl_conf_disable_spd[] = {
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x01),/* W2,GPIO43, U6 input S0*/
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x00),/* W3,GPIO44, U6 input S1*/
|
||||
};
|
||||
|
||||
static const unsigned int ctrl_conf_fix_pci_numbering[] = {
|
||||
RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x44), ~(0x00010000), 0x00000000, /* Force CK804 to start its internal device numbering (Base Unit ID) at 0 instead of the power-on default of 1 */
|
||||
};
|
||||
|
||||
static const unsigned int ctrl_conf_enable_msi_mapping[] = {
|
||||
RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xe0), ~(0x00000000), 0x00010000, /* Enable MSI mapping on host bridge -- without this Linux cannot use the network device MSI interrupts! */
|
||||
};
|
||||
|
||||
static void ck804_control(const unsigned int *values, u32 size,
|
||||
uint8_t bus_unit_id)
|
||||
{
|
||||
unsigned int busn[4], io_base[4];
|
||||
int i, ck804_num = 0;
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
u32 id;
|
||||
pci_devfn_t dev;
|
||||
if (i == 0) /* SB chain */
|
||||
dev = PCI_DEV(i * 0x40, bus_unit_id, 0);
|
||||
else
|
||||
dev = 0;
|
||||
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
if (id == 0x005e10de) {
|
||||
busn[ck804_num] = i * 0x40;
|
||||
io_base[ck804_num] = i * 0x4000;
|
||||
ck804_num++;
|
||||
}
|
||||
}
|
||||
|
||||
if (ck804_num < 1) {
|
||||
printk(BIOS_WARNING, "CK804 not found at device base unit id %02x!\n", bus_unit_id);
|
||||
return;
|
||||
}
|
||||
|
||||
ck804_early_set_port(ck804_num, busn, io_base);
|
||||
|
||||
setup_resource_map_x_offset(values,
|
||||
size,
|
||||
PCI_DEV(0, bus_unit_id, 0), io_base[0]);
|
||||
|
||||
ck804_early_clear_port(ck804_num, busn, io_base);
|
||||
}
|
||||
|
||||
static void sio_setup(void)
|
||||
{
|
||||
u32 dword;
|
||||
u8 byte;
|
||||
|
||||
/* Subject decoding */
|
||||
byte = pci_read_config8(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0x7b);
|
||||
byte |= 0x20;
|
||||
pci_write_config8(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0x7b, byte);
|
||||
|
||||
/* LPC Positive Decode 0 */
|
||||
dword = pci_read_config32(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0xa0);
|
||||
/* Serial 0, Serial 1 */
|
||||
dword |= (1 << 0) | (1 << 1);
|
||||
pci_write_config32(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0xa0, dword);
|
||||
}
|
||||
|
||||
static const uint8_t spd_addr[] = {
|
||||
// Node 0
|
||||
RC00, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
|
||||
// Node 1
|
||||
RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
|
||||
};
|
||||
|
||||
void activate_spd_rom(const struct mem_controller *ctrl)
|
||||
{
|
||||
printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id);
|
||||
if (ctrl->node_id == 0) {
|
||||
printk(BIOS_DEBUG, "enable_spd_node0()\n");
|
||||
ck804_control(ctrl_conf_enable_spd_node0, ARRAY_SIZE(ctrl_conf_enable_spd_node0), CK804_DEVN_BASE);
|
||||
}
|
||||
else if (ctrl->node_id == 1) {
|
||||
printk(BIOS_DEBUG, "enable_spd_node1()\n");
|
||||
ck804_control(ctrl_conf_enable_spd_node1, ARRAY_SIZE(ctrl_conf_enable_spd_node1), CK804_DEVN_BASE);
|
||||
}
|
||||
}
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
struct sys_info *sysinfo = get_sysinfo();
|
||||
|
||||
u32 bsp_apicid = 0, val, wants_reset;
|
||||
msr_t msr;
|
||||
|
||||
timestamp_init(timestamp_get());
|
||||
timestamp_add_now(TS_START_ROMSTAGE);
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
set_bsp_node_CHtExtNodeCfgEn();
|
||||
enumerate_ht_chain();
|
||||
sio_setup();
|
||||
}
|
||||
|
||||
post_code(0x30);
|
||||
|
||||
if (bist == 0)
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
|
||||
|
||||
post_code(0x32);
|
||||
|
||||
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
|
||||
if (CONFIG_MAX_PHYSICAL_CPUS != 2)
|
||||
printk(BIOS_WARNING, "CONFIG_MAX_PHYSICAL_CPUS is %d, but this is a dual socket board!\n", CONFIG_MAX_PHYSICAL_CPUS);
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
val = cpuid_eax(1);
|
||||
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
|
||||
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
|
||||
printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
|
||||
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
|
||||
|
||||
/* Setup sysinfo defaults */
|
||||
set_sysinfo_in_ram(0);
|
||||
|
||||
update_microcode(val);
|
||||
|
||||
post_code(0x33);
|
||||
|
||||
cpuSetAMDMSR(0);
|
||||
post_code(0x34);
|
||||
|
||||
amd_ht_init(sysinfo);
|
||||
post_code(0x35);
|
||||
|
||||
/* Setup nodes PCI space and start core 0 AP init. */
|
||||
finalize_node_setup(sysinfo);
|
||||
|
||||
/* Setup any mainboard PCI settings etc. */
|
||||
setup_mb_resource_map();
|
||||
post_code(0x36);
|
||||
|
||||
/* wait for all the APs core0 started by finalize_node_setup. */
|
||||
/* FIXME: A bunch of cores are going to start output to serial at once.
|
||||
* It would be nice to fix up prink spinlocks for ROM XIP mode.
|
||||
* I think it could be done by putting the spinlock flag in the cache
|
||||
* of the BSP located right after sysinfo.
|
||||
*/
|
||||
wait_all_core0_started();
|
||||
|
||||
if (CONFIG(SET_FIDVID)) {
|
||||
msr = rdmsr(MSR_COFVID_STS);
|
||||
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
|
||||
|
||||
post_code(0x39);
|
||||
|
||||
if (!warm_reset_detect(0)) { // BSP is node 0
|
||||
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
|
||||
} else {
|
||||
init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
|
||||
}
|
||||
|
||||
post_code(0x3A);
|
||||
|
||||
/* show final fid and vid */
|
||||
msr = rdmsr(MSR_COFVID_STS);
|
||||
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
if (CONFIG(LOGICAL_CPUS)) {
|
||||
/* Core0 on each node is configured. Now setup any additional cores. */
|
||||
printk(BIOS_DEBUG, "start_other_cores()\n");
|
||||
start_other_cores(bsp_apicid);
|
||||
post_code(0x37);
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
}
|
||||
|
||||
printk(BIOS_DEBUG, "set_ck804_base_unit_id()\n");
|
||||
ck804_control(ctrl_conf_fix_pci_numbering, ARRAY_SIZE(ctrl_conf_fix_pci_numbering), CK804_BOARD_BOOT_BASE_UNIT_UID);
|
||||
|
||||
post_code(0x38);
|
||||
|
||||
init_timer(); // Need to use TMICT to synconize FID/VID
|
||||
|
||||
wants_reset = ck804_early_setup_x();
|
||||
|
||||
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
|
||||
if (!warm_reset_detect(0)) {
|
||||
printk(BIOS_INFO, "...WARM RESET...\n\n\n");
|
||||
soft_reset();
|
||||
die("After soft_reset - shouldn't see this message!!!\n");
|
||||
}
|
||||
|
||||
if (wants_reset) {
|
||||
printk(BIOS_DEBUG, "ck804_early_setup_x wanted additional reset!\n");
|
||||
}
|
||||
|
||||
post_code(0x3B);
|
||||
|
||||
/* It's the time to set ctrl in sysinfo now; */
|
||||
printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
|
||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
||||
post_code(0x3D);
|
||||
|
||||
printk(BIOS_DEBUG, "enable_smbus()\n");
|
||||
enable_smbus();
|
||||
|
||||
#if 0
|
||||
/* FIXME
|
||||
* After the AMD K10 code has been converted to use
|
||||
* CONFIG(DEBUG_SMBUS) uncomment this block
|
||||
*/
|
||||
if (CONFIG(DEBUG_SMBUS)) {
|
||||
dump_spd_registers(&cpu[0]);
|
||||
dump_smbus_registers();
|
||||
}
|
||||
#endif
|
||||
|
||||
post_code(0x40);
|
||||
|
||||
raminit_amdmct(sysinfo);
|
||||
|
||||
cbmem_initialize_empty();
|
||||
post_code(0x41);
|
||||
|
||||
amdmct_cbmem_store_info(sysinfo);
|
||||
|
||||
printk(BIOS_DEBUG, "disable_spd()\n");
|
||||
ck804_control(ctrl_conf_disable_spd, ARRAY_SIZE(ctrl_conf_disable_spd), CK804_DEVN_BASE);
|
||||
|
||||
printk(BIOS_DEBUG, "enable_msi_mapping()\n");
|
||||
ck804_control(ctrl_conf_enable_msi_mapping, ARRAY_SIZE(ctrl_conf_enable_msi_mapping), CK804_DEVN_BASE);
|
||||
|
||||
/* Initialize GPIO */
|
||||
/* Access SuperIO GPI03 logical device */
|
||||
pnp_enter_conf_state(GPIO3_DEV);
|
||||
pnp_set_logical_device(GPIO3_DEV);
|
||||
/* Set GP37 (power LED) to output */
|
||||
pnp_write_config(GPIO3_DEV, 0xf0, 0x7f);
|
||||
/* Set GP37 (power LED) on */
|
||||
pnp_write_config(GPIO3_DEV, 0xf1, 0x80);
|
||||
/* Set pin 64 multiplex to GP37 */
|
||||
uint8_t cr2c = pnp_read_config(GPIO3_DEV, 0x2c);
|
||||
pnp_write_config(GPIO3_DEV, 0x2c, (cr2c & 0xf3) | 0x04);
|
||||
/* Restore default SuperIO access */
|
||||
pnp_exit_conf_state(GPIO3_DEV);
|
||||
}
|
||||
|
||||
/**
|
||||
* BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
|
||||
* Description:
|
||||
* This routine is called every time a non-coherent chain is processed.
|
||||
* BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
|
||||
* swap list. The first part of the list controls the BUID assignment and the
|
||||
* second part of the list provides the device to device linking. Device orientation
|
||||
* can be detected automatically, or explicitly. See documentation for more details.
|
||||
*
|
||||
* Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
|
||||
* based on each device's unit count.
|
||||
*
|
||||
* Parameters:
|
||||
* @param[in] node = The node on which this chain is located
|
||||
* @param[in] link = The link on the host for this chain
|
||||
* @param[out] List = supply a pointer to a list
|
||||
*/
|
||||
BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
@@ -1,69 +0,0 @@
|
||||
====================================================================================================
|
||||
SPD mux
|
||||
====================================================================================================
|
||||
|
||||
DIMM_A1 SDA signal traced to U6 pin 1
|
||||
Destructive testing of failed board (removal of U7 northbridge!) yielded the following information:
|
||||
U6 S0 <--> U7 W2
|
||||
U6 S1 <--> U7 W3
|
||||
|
||||
Proprietary BIOS enables the SPD during POST with:
|
||||
S0: LOW
|
||||
S1: LOW
|
||||
|
||||
then temporarily switches to:
|
||||
S0: LOW
|
||||
S1: HIGH
|
||||
|
||||
then switches to runtime mode with:
|
||||
S0: HIGH
|
||||
S1: LOW
|
||||
|
||||
After probing with a custom GPIO-flipping tool under Linux the following GPIO mappings were found:
|
||||
CK804 pin W2 <--> GPIO43
|
||||
CK804 pin W3 <--> GPIO44
|
||||
|
||||
====================================================================================================
|
||||
W83793 (U46)
|
||||
====================================================================================================
|
||||
|
||||
Sensor mappings:
|
||||
FRNT_FAN1: FAN3
|
||||
FRNT_FAN2: FAN4
|
||||
FRNT_FAN3: FAN5
|
||||
FRNT_FAN4: FAN6
|
||||
FRNT_FAN5: FAN9
|
||||
FRNT_FAN6: FAN10
|
||||
REAR_FAN1: FAN7
|
||||
REAR_FAN2: FAN8
|
||||
REAR_FAN3: FAN11
|
||||
REAR_FAN4: FAN12
|
||||
|
||||
====================================================================================================
|
||||
Other hardware
|
||||
====================================================================================================
|
||||
|
||||
Power LED (-) is connected to U15 (SuperIO) pin 64 via U4 pins 5,6 and a small MOSFET
|
||||
ID LED (-) is connected to a ??? via U4 pins 1,2,3,4 and U77 pins 5,6
|
||||
It appears that setting U15 (SuperIO) pin 88 LOW will override the ID LED and force it ON
|
||||
|
||||
RECOVERY2 middle pin is connected to U15 (SuperIO) pin 89
|
||||
Normal is HIGH, recovery is LOW.
|
||||
|
||||
PCIe slot WAKE# connects to U7 pin E23 (PCIE_WAKE#)
|
||||
|
||||
CPU_WARN1 is driven by (???) via a simple buffer (U13 pin 10)
|
||||
MEM_WARN1 is driven by U7 pin AD3 (CPUVDD_EN) via a simple buffer (U101 pin 3)
|
||||
|
||||
U7 pin AK3 is disconnected (routed to unpopulated capacitor/resistor)
|
||||
PU1 pin 37 (VDDPWRGD) drives U7 pin AJ4 (CPU_VLD)
|
||||
A small MOSFET directly above another small MOSFET directly above the right-hand edge of the PCIe slot drives U7 pin AK5 (HT_VLD)
|
||||
|
||||
When > Barcelona CPU installed on PCB rev 1.04G:
|
||||
U7 pin AK4 (MEM_VLD): HIGH
|
||||
PU1 pin 37: LOW
|
||||
U7 pin AK5: LOW
|
||||
|
||||
HyperTransport 1.2V supply appears to be generated by a linear regulator containing Q191 and downconverting the CK804 1.5V supply
|
||||
The enable pin appears to be tied to AUX_PANEL pin 1 (+5VSB) via a resistor
|
||||
Through two MOSFETs the HT supply enable pin is tied to U7 pin AE3 (HTVDD_EN)
|
||||
@@ -1,102 +0,0 @@
|
||||
if BOARD_ASUS_KGPE_D16
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS
|
||||
def_bool y
|
||||
select CPU_AMD_SOCKET_G34_NON_AGESA
|
||||
select DIMM_DDR3
|
||||
select DIMM_REGISTERED
|
||||
# select QRANK_DIMM_SUPPORT
|
||||
select DIMM_VOLTAGE_SET_SUPPORT
|
||||
select NORTHBRIDGE_AMD_AMDFAM10
|
||||
select SOUTHBRIDGE_AMD_SR5650
|
||||
select SOUTHBRIDGE_AMD_SB700
|
||||
select SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA
|
||||
select SOUTHBRIDGE_AMD_SUBTYPE_SP5100
|
||||
select SUPERIO_WINBOND_W83667HG_A
|
||||
select PARALLEL_CPU_INIT
|
||||
select HAVE_ROMSTAGE_CONSOLE_SPINLOCK
|
||||
select HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
|
||||
select HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_CMOS_DEFAULT
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_TABLES
|
||||
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
select LIFT_BSP_APIC_ID
|
||||
select BOARD_ROMSIZE_KB_2048
|
||||
select ENABLE_APIC_EXT_ID
|
||||
select SPI_FLASH
|
||||
select MAINBOARD_HAS_LPC_TPM
|
||||
select DRIVERS_I2C_W83795
|
||||
select DRIVERS_ASPEED_AST2050
|
||||
select MAINBOARD_FORCE_NATIVE_VGA_INIT
|
||||
select POWER_STATE_DEFAULT_ON_AFTER_FAILURE
|
||||
select IPMI_KCS
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default "asus/kgpe-d16"
|
||||
|
||||
config BOOTBLOCK_MAINBOARD_INIT
|
||||
string
|
||||
default "mainboard/asus/kgpe-d16/bootblock.c"
|
||||
|
||||
config DCACHE_RAM_BASE
|
||||
hex
|
||||
default 0xc2000
|
||||
|
||||
config DCACHE_RAM_SIZE
|
||||
hex
|
||||
default 0x1e000
|
||||
|
||||
config APIC_ID_OFFSET
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "KGPE-D16"
|
||||
|
||||
config HW_MEM_HOLE_SIZEK
|
||||
hex
|
||||
default 0x100000
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 32
|
||||
|
||||
# 2 (internal) processors per G34 socket
|
||||
config MAX_PHYSICAL_CPUS
|
||||
int
|
||||
default 4
|
||||
|
||||
config HT_CHAIN_UNITID_BASE
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
config HT_CHAIN_END_UNITID_BASE
|
||||
hex
|
||||
default 0x20
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 13
|
||||
|
||||
config SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD
|
||||
hex
|
||||
default 0x3f
|
||||
|
||||
config ONBOARD_VGA_IS_PRIMARY
|
||||
bool
|
||||
default y
|
||||
|
||||
config VGA_BIOS_ID
|
||||
string
|
||||
default "1a03,2000"
|
||||
|
||||
config MAX_REBOOT_CNT
|
||||
int
|
||||
default 10
|
||||
|
||||
endif # BOARD_ASUS_KGPE_D16
|
||||
@@ -1,2 +0,0 @@
|
||||
config BOARD_ASUS_KGPE_D16
|
||||
bool "KGPE-D16"
|
||||
@@ -1,16 +0,0 @@
|
||||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
|
||||
romstage-y += resourcemap.c
|
||||
|
||||
ramstage-y += get_bus_conf.c
|
||||
@@ -1,368 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Raptor Engineering
|
||||
* Copyright (C) 2009 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* Port 80 POST card debug */
|
||||
OperationRegion (DBG0, SystemIO, 0x80, One)
|
||||
Field (DBG0, ByteAcc, NoLock, Preserve) {
|
||||
DBG8, 8
|
||||
}
|
||||
|
||||
/* SuperIO control port */
|
||||
Name (SPIO, 0x2E)
|
||||
|
||||
/* SuperIO control map */
|
||||
OperationRegion (SPIM, SystemIO, SPIO, 0x02)
|
||||
Field (SPIM, ByteAcc, NoLock, Preserve) {
|
||||
INDX, 8,
|
||||
DATA, 8
|
||||
}
|
||||
|
||||
/* SuperIO control registers */
|
||||
IndexField (INDX, DATA, ByteAcc, NoLock, Preserve) {
|
||||
Offset (0x07),
|
||||
CR07, 8, /* Logical device number */
|
||||
Offset (0x2C),
|
||||
CR2C, 8, /* GPIO3 multiplexed pin selection */
|
||||
Offset (0x30),
|
||||
CR30, 8, /* Logical device activation control register */
|
||||
Offset (0xE0),
|
||||
CRE0, 8, /* Wake control register */
|
||||
Offset (0xE4),
|
||||
CRE4, 8, /* Standby power control register */
|
||||
Offset (0xE6),
|
||||
CRE6, 8, /* Mouse wake event configuration register */
|
||||
Offset (0xF1),
|
||||
CRF1, 8, /* GPIO3 data register */
|
||||
Offset (0xF3),
|
||||
CRF3, 8, /* SUSLED mode register */
|
||||
Offset (0xF6),
|
||||
CRF6, 8, /* SMI/PME event generation control register */
|
||||
Offset (0xF9),
|
||||
CRF9, 8, /* ACPI PME configuration register */
|
||||
}
|
||||
|
||||
/* Power Management I/O registers */
|
||||
OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
|
||||
Field(PIOR, ByteAcc, NoLock, Preserve) {
|
||||
PIOI, 0x00000008,
|
||||
PIOD, 0x00000008,
|
||||
}
|
||||
IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
|
||||
Offset(0x00), /* MiscControl */
|
||||
, 1,
|
||||
T1EE, 1,
|
||||
T2EE, 1,
|
||||
Offset(0x01), /* MiscStatus */
|
||||
, 1,
|
||||
T1E, 1,
|
||||
T2E, 1,
|
||||
Offset(0x04), /* SmiWakeUpEventEnable3 */
|
||||
, 7,
|
||||
SSEN, 1,
|
||||
Offset(0x07), /* SmiWakeUpEventStatus3 */
|
||||
, 7,
|
||||
CSSM, 1,
|
||||
Offset(0x10), /* AcpiEnable */
|
||||
, 6,
|
||||
PWDE, 1,
|
||||
Offset(0x1C), /* ProgramIoEnable */
|
||||
, 3,
|
||||
MKME, 1,
|
||||
IO3E, 1,
|
||||
IO2E, 1,
|
||||
IO1E, 1,
|
||||
IO0E, 1,
|
||||
Offset(0x1D), /* IOMonitorStatus */
|
||||
, 3,
|
||||
MKMS, 1,
|
||||
IO3S, 1,
|
||||
IO2S, 1,
|
||||
IO1S, 1,
|
||||
IO0S,1,
|
||||
Offset(0x20), /* AcpiPmEvtBlk */
|
||||
APEB, 16,
|
||||
Offset(0x36), /* GEvtLevelConfig */
|
||||
, 6,
|
||||
ELC6, 1,
|
||||
ELC7, 1,
|
||||
Offset(0x37), /* GPMLevelConfig0 */
|
||||
, 3,
|
||||
PLC0, 1,
|
||||
PLC1, 1,
|
||||
PLC2, 1,
|
||||
PLC3, 1,
|
||||
PLC8, 1,
|
||||
Offset(0x38), /* GPMLevelConfig1 */
|
||||
, 1,
|
||||
PLC4, 1,
|
||||
PLC5, 1,
|
||||
, 1,
|
||||
PLC6, 1,
|
||||
PLC7, 1,
|
||||
Offset(0x3B), /* PMEStatus1 */
|
||||
GP0S, 1,
|
||||
GM4S, 1,
|
||||
GM5S, 1,
|
||||
APS, 1,
|
||||
GM6S, 1,
|
||||
GM7S, 1,
|
||||
GP2S, 1,
|
||||
STSS, 1,
|
||||
Offset(0x55), /* SoftPciRst */
|
||||
SPRE, 1,
|
||||
, 1,
|
||||
, 1,
|
||||
PNAT, 1,
|
||||
PWMK, 1,
|
||||
PWNS, 1,
|
||||
|
||||
/* Offset(0x61), */ /* Options_1 */
|
||||
/* ,7, */
|
||||
/* R617,1, */
|
||||
|
||||
Offset(0x65), /* UsbPMControl */
|
||||
, 4,
|
||||
URRE, 1,
|
||||
, 2,
|
||||
BCDL, 1,
|
||||
Offset(0x68), /* MiscEnable68 */
|
||||
, 2,
|
||||
MAPC, 1,
|
||||
TMTE, 1,
|
||||
, 1,
|
||||
Offset(0x7C), /* MiscEnable7C */
|
||||
, 2,
|
||||
BLNK, 2,
|
||||
Offset(0x92), /* GEVENTIN */
|
||||
, 7,
|
||||
E7IS, 1,
|
||||
Offset(0x96), /* GPM98IN */
|
||||
G8IS, 1,
|
||||
G9IS, 1,
|
||||
Offset(0x9A), /* EnhanceControl */
|
||||
,7,
|
||||
HPDE, 1,
|
||||
Offset(0xA8), /* PIO7654Enable */
|
||||
IO4E, 1,
|
||||
IO5E, 1,
|
||||
IO6E, 1,
|
||||
IO7E, 1,
|
||||
Offset(0xA9), /* PIO7654Status */
|
||||
IO4S, 1,
|
||||
IO5S, 1,
|
||||
IO6S, 1,
|
||||
IO7S, 1,
|
||||
}
|
||||
|
||||
/* PM1 Event Block
|
||||
* First word is PM1_Status, Second word is PM1_Enable
|
||||
*/
|
||||
OperationRegion(P1EB, SystemIO, APEB, 0x04)
|
||||
Field(P1EB, ByteAcc, NoLock, Preserve) {
|
||||
TMST, 1,
|
||||
, 3,
|
||||
BMST, 1,
|
||||
GBST, 1,
|
||||
Offset(0x01),
|
||||
PBST, 1,
|
||||
, 1,
|
||||
RTST, 1,
|
||||
, 3,
|
||||
PWST, 1,
|
||||
SPWS, 1,
|
||||
Offset(0x02),
|
||||
TMEN, 1,
|
||||
, 4,
|
||||
GBEN, 1,
|
||||
Offset(0x03),
|
||||
PBEN, 1,
|
||||
, 1,
|
||||
RTEN, 1,
|
||||
, 3,
|
||||
PWDA, 1,
|
||||
}
|
||||
|
||||
/* Wake status package */
|
||||
Name(WKST,Package() {Zero, Zero})
|
||||
|
||||
/*
|
||||
* \_WAK System Wake method
|
||||
*
|
||||
* Entry:
|
||||
* Arg0=The value of the sleeping state S1=1, S2=2
|
||||
*
|
||||
* Exit:
|
||||
* Return package of 2 DWords
|
||||
* Dword 1 - Status
|
||||
* 0x00000000 wake succeeded
|
||||
* 0x00000001 Wake was signaled but failed due to lack of power
|
||||
* 0x00000002 Wake was signaled but failed due to thermal condition
|
||||
* Dword 2 - Power Supply state
|
||||
* if non-zero the effective S-state the power supply entered
|
||||
*/
|
||||
Method(\_WAK, 1) {
|
||||
Store (0x20, DBG8)
|
||||
|
||||
/* Set up LEDs */
|
||||
/* Set power LED to steady on */
|
||||
Store(0x0, BLNK)
|
||||
|
||||
/* Configure SuperIO for wake */
|
||||
/* Access SuperIO ACPI device */
|
||||
Store(0x87, INDX)
|
||||
Store(0x87, INDX)
|
||||
Store(0x0A, CR07)
|
||||
|
||||
if (LEqual(Arg0, One)) /* Resuming from power state S1 */
|
||||
{
|
||||
/* Deactivate the ACPI device */
|
||||
Store(Zero, CR30)
|
||||
|
||||
/* Disable PS/2 SMI/PME events */
|
||||
And(CRF6, 0xCF, CRF6)
|
||||
}
|
||||
if (Lor(LEqual(Arg0, 0x03), LEqual(Arg0, 0x04))) /* Resuming from power state S3 or S4 */
|
||||
{
|
||||
/* Disable PS/2 wake */
|
||||
And(CRE0, 0x1D, CRE0)
|
||||
And(CRE6, 0x7F, CRE6)
|
||||
}
|
||||
|
||||
/* Restore default SuperIO access */
|
||||
Store(0xAA, INDX)
|
||||
|
||||
Store (0x21, DBG8)
|
||||
|
||||
/* Re-enable HPET */
|
||||
Store(1, HPDE)
|
||||
|
||||
/* Restore PCIRST# so it resets USB */
|
||||
if (LEqual(Arg0, 3)){
|
||||
Store(1, URRE)
|
||||
}
|
||||
|
||||
/* Configure southbridge for wake */
|
||||
/* Arbitrarily clear PciExpWakeStatus */
|
||||
Store(PWST, Local1)
|
||||
Store(Local1, PWST)
|
||||
|
||||
Store (0x22, DBG8)
|
||||
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
|
||||
Return(WKST)
|
||||
}
|
||||
|
||||
/*
|
||||
* \_PTS - Prepare to Sleep method
|
||||
*
|
||||
* Entry:
|
||||
* Arg0=The value of the sleeping state S1=1, S2=2, etc
|
||||
*
|
||||
* Exit:
|
||||
* -none-
|
||||
*
|
||||
* The _PTS control method is executed at the beginning of the sleep process
|
||||
* for S1-S5. The sleeping value is passed to the _PTS control method. This
|
||||
* control method may be executed a relatively long time before entering the
|
||||
* sleep state and the OS may abort the operation without notification to
|
||||
* the ACPI driver. This method cannot modify the configuration or power
|
||||
* state of any device in the system.
|
||||
*/
|
||||
Method(\_PTS, 1) {
|
||||
Store (Arg0, DBG8)
|
||||
|
||||
/* Set up LEDs */
|
||||
if (LEqual(Arg0, One)) /* Power state S1 requested */
|
||||
{
|
||||
/* Set suspend LED to 0.25Hz toggle pulse with 50% duty cycle */
|
||||
Store(0x2, BLNK)
|
||||
}
|
||||
|
||||
/* Configure SuperIO for sleep */
|
||||
/* Access SuperIO ACPI device */
|
||||
Store(0x87, INDX)
|
||||
Store(0x87, INDX)
|
||||
Store(0x0A, CR07)
|
||||
|
||||
/* Disable PS/2 wakeup and connect PANSW_IN to PANSW_OUT */
|
||||
And(CRE0, 0x1F, CRE0)
|
||||
|
||||
if (LEqual(Arg0, One)) /* Power state S1 requested */
|
||||
{
|
||||
/* Activate the ACPI device */
|
||||
Store(One, CR30)
|
||||
|
||||
/* Disable SMI/PME events for:
|
||||
* LPT
|
||||
* FDC
|
||||
* UART
|
||||
*/
|
||||
Store(0x00, CRF6)
|
||||
|
||||
/* Enable PS/2 keyboard SMI/PME events */
|
||||
Or(CRF6, 0x10, CRF6)
|
||||
|
||||
/* Enable PS/2 keyboard wake */
|
||||
Or(CRE0, 0x40, CRE0)
|
||||
|
||||
/* Enable PS/2 mouse SMI/PME events */
|
||||
Or(CRF6, 0x20, CRF6)
|
||||
|
||||
/* Enable PS/2 mouse wake */
|
||||
Or(CRE0, 0x20, CRE0)
|
||||
} else {
|
||||
/* Enable PS/2 keyboard wake on any keypress */
|
||||
Or(CRE0, 0x41, CRE0)
|
||||
|
||||
/* Enable PS/2 mouse wake on any click */
|
||||
Or(CRE0, 0x22, CRE0)
|
||||
Or(CRE6, 0x80, CRE6)
|
||||
|
||||
if (LEqual(Arg0, 0x03)) /* Power state S3 requested */
|
||||
{
|
||||
/* Set VSBGATE# to provide standby power during S3 */
|
||||
Or(CRE4, 0x10, CRE4)
|
||||
}
|
||||
}
|
||||
|
||||
/* Restore default SuperIO access */
|
||||
Store(0xAA, INDX)
|
||||
|
||||
Store (0x10, DBG8)
|
||||
|
||||
/* Don't allow PCIRST# to reset USB */
|
||||
if (LEqual(Arg0, 3)){
|
||||
Store(0, URRE)
|
||||
}
|
||||
|
||||
/* Configure southbridge for sleep */
|
||||
/* Use bus clock for delay timebase */
|
||||
Store(0, BCDL)
|
||||
/* Defer APIC interrupts until first ACPI access */
|
||||
Store(One, MAPC)
|
||||
|
||||
/* On older chips, clear PciExpWakeDisEn */
|
||||
// if (LLessEqual(SBRI, 0x13)) {
|
||||
// Store(0, PWDE)
|
||||
// }
|
||||
|
||||
Store (0x11, DBG8)
|
||||
|
||||
/* Clear wake status structure. */
|
||||
Store(0, Index(WKST,0))
|
||||
Store(0, Index(WKST,1))
|
||||
}
|
||||
@@ -1,103 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
struct device *dev;
|
||||
u32 dword;
|
||||
u32 gsi_base = 0;
|
||||
uint32_t apicid_sp5100;
|
||||
uint32_t apicid_sr5650;
|
||||
/* create all subtables for processors */
|
||||
current = acpi_create_madt_lapics(current);
|
||||
|
||||
if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
|
||||
apicid_sp5100 = 0x0;
|
||||
else
|
||||
apicid_sp5100 = 0x20;
|
||||
apicid_sr5650 = apicid_sp5100 + 1;
|
||||
|
||||
/* Write SB700 IOAPIC, only one */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sp5100,
|
||||
IO_APIC_ADDR, gsi_base);
|
||||
/* IOAPIC on rs5690 */
|
||||
gsi_base += 24; /* SB700 has 24 IOAPIC entries. */
|
||||
dev = pcidev_on_root(0, 0);
|
||||
if (dev) {
|
||||
pci_write_config32(dev, 0xF8, 0x1);
|
||||
dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sr5650,
|
||||
dword, gsi_base);
|
||||
}
|
||||
|
||||
/* bus, source, gsirq, flags */
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 0, 2, 0);
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 9, 9, 0xf);
|
||||
|
||||
/* create all subtables for processors */
|
||||
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 0, 1);
|
||||
/* 1: LINT1 connect to NMI */
|
||||
|
||||
return current;
|
||||
}
|
||||
|
||||
unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current)
|
||||
{
|
||||
uint8_t *p;
|
||||
|
||||
uint32_t apicid_sp5100;
|
||||
uint32_t apicid_sr5650;
|
||||
|
||||
if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
|
||||
apicid_sp5100 = 0x0;
|
||||
else
|
||||
apicid_sp5100 = 0x20;
|
||||
apicid_sr5650 = apicid_sp5100 + 1;
|
||||
|
||||
/* Describe NB IOAPIC */
|
||||
p = (uint8_t *)current;
|
||||
p[0] = 0x48; /* Entry type */
|
||||
p[1] = 0; /* Device */
|
||||
p[2] = 0; /* Bus */
|
||||
p[3] = 0x0; /* Data */
|
||||
p[4] = apicid_sr5650; /* IOAPIC ID */
|
||||
p[5] = 0x1; /* Device 0 Function 1 */
|
||||
p[6] = 0x0; /* Northbridge bus */
|
||||
p[7] = 0x1; /* Variety */
|
||||
current += 8;
|
||||
|
||||
/* Describe SB IOAPIC */
|
||||
p = (uint8_t *)current;
|
||||
p[0] = 0x48; /* Entry type */
|
||||
p[1] = 0; /* Device */
|
||||
p[2] = 0; /* Bus */
|
||||
p[3] = 0xd7; /* Data */
|
||||
p[4] = apicid_sp5100; /* IOAPIC ID */
|
||||
p[5] = 0x14 << 3; /* Device 0x14 Function 0 */
|
||||
p[6] = 0x0; /* Southbridge bus */
|
||||
p[7] = 0x1; /* Variety */
|
||||
current += 8;
|
||||
|
||||
return current;
|
||||
}
|
||||
@@ -1,5 +0,0 @@
|
||||
Category: server
|
||||
ROM package: DIP-8
|
||||
ROM protocol: SPI
|
||||
ROM socketed: y
|
||||
Flashrom support: y
|
||||
@@ -1,52 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/pci_ops.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
|
||||
void bootblock_mainboard_init(void)
|
||||
{
|
||||
uint8_t recovery_enabled;
|
||||
unsigned char addr;
|
||||
unsigned char byte;
|
||||
|
||||
bootblock_northbridge_init();
|
||||
bootblock_southbridge_init();
|
||||
|
||||
/* Recovery jumper is connected to SP5100 GPIO61, and clears the GPIO when placed in the Recovery position */
|
||||
byte = pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x56);
|
||||
byte |= 0x1 << 4; /* Set GPIO61 to input mode */
|
||||
pci_io_write_config8(PCI_DEV(0, 0x14, 0), 0x56, byte);
|
||||
recovery_enabled = (!(pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x57) & 0x1));
|
||||
if (recovery_enabled) {
|
||||
#if CONFIG(USE_OPTION_TABLE)
|
||||
/* Clear NVRAM checksum */
|
||||
for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {
|
||||
cmos_write(0x0, addr);
|
||||
}
|
||||
|
||||
/* Set fallback boot */
|
||||
byte = cmos_read(RTC_BOOT_BYTE);
|
||||
byte &= 0xfc;
|
||||
cmos_write(byte, RTC_BOOT_BYTE);
|
||||
#else
|
||||
/* FIXME
|
||||
* Figure out how to recover if the option table is not available
|
||||
*/
|
||||
#endif
|
||||
}
|
||||
}
|
||||
@@ -1,30 +0,0 @@
|
||||
debug_level=Debug
|
||||
multi_core=Enable
|
||||
slow_cpu=off
|
||||
compute_unit_siblings=Enable
|
||||
iommu=Enable
|
||||
nmi=Disable
|
||||
hypertransport_speed_limit=Auto
|
||||
max_mem_clock=DDR3-1600
|
||||
minimum_memory_voltage=1.5V
|
||||
dimm_spd_checksum=Enforce
|
||||
ECC_memory=Enable
|
||||
ECC_redirection=Enable
|
||||
ecc_scrub_rate=1.28us
|
||||
interleave_chip_selects=Enable
|
||||
interleave_nodes=Disable
|
||||
interleave_memory_channels=Enable
|
||||
cpu_c_states=Enable
|
||||
cpu_cc6_state=Enable
|
||||
cpu_core_boost=Enable
|
||||
sata_ahci_mode=Enable
|
||||
sata_alpm=Disable
|
||||
maximum_p_state_limit=0xf
|
||||
probe_filter=Auto
|
||||
l3_cache_partitioning=Disable
|
||||
ieee1394_controller=Enable
|
||||
gart=Enable
|
||||
ehci_async_data_cache=Enable
|
||||
experimental_memory_speed_boost=Disable
|
||||
power_on_after_fail=On
|
||||
boot_option=Fallback
|
||||
@@ -1,150 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
## Copyright (C) 2007 AMD
|
||||
## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
entries
|
||||
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
393 3 r 0 unused
|
||||
#394 7 unused
|
||||
401 1 e 1 interleave_chip_selects
|
||||
402 1 e 1 interleave_nodes
|
||||
403 1 e 1 interleave_memory_channels
|
||||
404 4 e 8 max_mem_clock
|
||||
408 1 e 2 multi_core
|
||||
412 4 e 6 debug_level
|
||||
416 5 e 10 ecc_scrub_rate
|
||||
440 4 e 9 slow_cpu
|
||||
444 1 e 1 nmi
|
||||
445 1 e 1 gart
|
||||
446 2 e 3 power_on_after_fail
|
||||
456 1 e 1 ECC_memory
|
||||
457 1 e 1 ECC_redirection
|
||||
458 4 e 11 hypertransport_speed_limit
|
||||
462 2 e 12 minimum_memory_voltage
|
||||
464 1 e 2 compute_unit_siblings
|
||||
465 1 e 1 cpu_c_states
|
||||
466 1 e 1 cpu_cc6_state
|
||||
467 1 e 1 sata_ahci_mode
|
||||
468 1 e 1 sata_alpm
|
||||
#469 4 unused
|
||||
473 2 e 13 dimm_spd_checksum
|
||||
475 1 e 14 probe_filter
|
||||
476 1 e 1 l3_cache_partitioning
|
||||
477 1 e 1 ieee1394_controller
|
||||
478 1 e 1 iommu
|
||||
479 1 e 1 cpu_core_boost
|
||||
480 1 e 2 ehci_async_data_cache
|
||||
481 1 e 1 experimental_memory_speed_boost
|
||||
482 1 r 0 allow_spd_nvram_cache_restore
|
||||
483 4 h 0 maximum_p_state_limit
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
3 0 Off
|
||||
3 1 On
|
||||
3 2 Last
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
6 0 Emergency
|
||||
6 1 Alert
|
||||
6 2 Critical
|
||||
6 3 Error
|
||||
6 4 Warning
|
||||
6 5 Notice
|
||||
6 6 Information
|
||||
6 7 Debug
|
||||
6 8 Spew
|
||||
8 0 DDR3-1866
|
||||
8 1 DDR3-1600
|
||||
8 2 DDR3-1333
|
||||
8 3 DDR3-1066
|
||||
8 4 DDR3-800
|
||||
8 5 DDR3-667
|
||||
9 0 off
|
||||
9 1 87.5%
|
||||
9 2 75.0%
|
||||
9 3 62.5%
|
||||
9 4 50.0%
|
||||
9 5 37.5%
|
||||
9 6 25.0%
|
||||
9 7 12.5%
|
||||
10 0 Disabled
|
||||
10 1 40ns
|
||||
10 2 80ns
|
||||
10 3 160ns
|
||||
10 4 320ns
|
||||
10 5 640ns
|
||||
10 6 1.28us
|
||||
10 7 2.56us
|
||||
10 8 5.12us
|
||||
10 9 10.2us
|
||||
10 10 20.5us
|
||||
10 11 41us
|
||||
10 12 81.9us
|
||||
10 13 163.8us
|
||||
10 14 327.7us
|
||||
10 15 655.4us
|
||||
10 16 1.31ms
|
||||
10 17 2.62ms
|
||||
10 18 5.24ms
|
||||
10 19 10.49ms
|
||||
10 20 20.97ms
|
||||
10 21 42ms
|
||||
10 22 84ms
|
||||
11 0 Auto
|
||||
11 1 3.2GHz
|
||||
11 2 3.0GHz
|
||||
11 3 2.8GHz
|
||||
11 4 2.6GHz
|
||||
11 5 2.4GHz
|
||||
11 6 2.2GHz
|
||||
11 7 2.0GHz
|
||||
11 8 1.8GHz
|
||||
11 9 1.6GHz
|
||||
11 10 1.4GHz
|
||||
11 11 1.2GHz
|
||||
11 12 1.0GHz
|
||||
11 13 800MHz
|
||||
11 14 600MHz
|
||||
11 15 500MHz
|
||||
12 0 1.5V
|
||||
12 1 1.35V
|
||||
12 2 1.25V
|
||||
12 3 1.15V
|
||||
13 0 Enforce
|
||||
13 1 Ignore
|
||||
13 2 Override
|
||||
14 0 Disable
|
||||
14 1 Auto
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
@@ -1,259 +0,0 @@
|
||||
chip northbridge/amd/amdfam10/root_complex # Root complex
|
||||
device cpu_cluster 0 on # (L)APIC cluster
|
||||
chip cpu/amd/socket_F_1207 # CPU socket
|
||||
device lapic 0 on end # Local APIC of the CPU
|
||||
end
|
||||
end
|
||||
device domain 0 on # PCI domain
|
||||
subsystemid 0x1043 0x8163 inherit
|
||||
chip northbridge/amd/amdfam10 # Northbridge / RAM controller
|
||||
register "maximum_memory_capacity" = "0x4000000000" # 256GB
|
||||
device pci 18.0 on end # Link 0 == LDT 0
|
||||
device pci 18.0 on end # Link 1 == LDT 1
|
||||
device pci 18.0 on end # Link 2 == LDT 2
|
||||
device pci 18.0 on # Link 3 == LDT 3 [SB on link 3]
|
||||
chip southbridge/amd/sr5650 # Primary southbridge
|
||||
device pci 0.0 on end # HT Root Complex 0x9600
|
||||
device pci 0.1 on end # CLKCONFIG
|
||||
device pci 0.2 on end # IOMMU
|
||||
device pci 2.0 on # PCIE P2P bridge 0x9603 (GPP1 Port0)
|
||||
# Slot # PCI E 1 / PCI E 2
|
||||
end
|
||||
device pci 3.0 off end # PCIE P2P bridge 0x960b (GPP1 Port1)
|
||||
device pci 4.0 on # PCIE P2P bridge 0x9604 (GPP3a Port0)
|
||||
# PIKE SAS
|
||||
end
|
||||
device pci 5.0 off end # PCIE P2P bridge 0x9605 (GPP3a Port1)
|
||||
device pci 6.0 off end # PCIE P2P bridge 0x9606 (GPP3a Port2)
|
||||
device pci 7.0 off end # PCIE P2P bridge 0x9607 (GPP3a Port3)
|
||||
device pci 8.0 off end # NB/SB Link P2P bridge
|
||||
device pci 9.0 on # Bridge (GPP3a Port4)
|
||||
# Onboard # NIC A
|
||||
end
|
||||
device pci a.0 on # Bridge (GPP3a Port5)
|
||||
# Onboard # NIC B
|
||||
end
|
||||
device pci b.0 on # Bridge (GPP2 Port0)
|
||||
# Slot # PCI E 4
|
||||
end
|
||||
device pci c.0 on # Bridge (GPP2 Port1)
|
||||
# Slot # PCI E 5
|
||||
end
|
||||
device pci d.0 on # Bridge (GPP3b Port0)
|
||||
# Slot # PCI E 3
|
||||
end
|
||||
register "gpp1_configuration" = "0" # Configuration 16:0 default
|
||||
register "gpp2_configuration" = "1" # Configuration 8:8
|
||||
register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0
|
||||
register "port_enable" = "0x3f1c" # Enable all ports except 0, 1, 5, 6, and 7
|
||||
register "pcie_settling_time" = "1000000" # Allow PIKE to be detected / configured
|
||||
end
|
||||
chip southbridge/amd/sb700 # Secondary southbridge
|
||||
device pci 11.0 on end # SATA
|
||||
device pci 12.0 on end # USB
|
||||
device pci 12.1 on end # USB
|
||||
device pci 12.2 on end # USB
|
||||
device pci 13.0 on end # USB
|
||||
device pci 13.1 on end # USB
|
||||
device pci 13.2 on end # USB
|
||||
device pci 14.0 on # SM
|
||||
chip drivers/generic/generic # DIMM n-0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM n-0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM n-0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM n-0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM n-1-0-0
|
||||
device i2c 54 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM n-1-0-1
|
||||
device i2c 55 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM n-1-1-0
|
||||
device i2c 56 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM n-1-1-1
|
||||
device i2c 57 on end
|
||||
end
|
||||
chip drivers/i2c/w83795
|
||||
register "fanin_ctl1" = "0xff" # Enable monitoring of FANIN1 - FANIN8
|
||||
register "fanin_ctl2" = "0x00" # Connect FANIN11 - FANIN14 to alternate functions
|
||||
register "temp_ctl1" = "0x2a" # Enable monitoring of DTS, VSEN12, and VSEN13
|
||||
register "temp_ctl2" = "0x01" # Enable monitoring of TD1/TR1
|
||||
register "temp_dtse" = "0x03" # Enable DTS1 and DTS2
|
||||
register "volt_ctl1" = "0xff" # Enable monitoring of VSEN1 - VSEN8
|
||||
register "volt_ctl2" = "0xf7" # Enable monitoring of VSEN9 - VSEN11, 3VDD, 3VSB, and VBAT
|
||||
register "temp1_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp1)
|
||||
register "temp2_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp2)
|
||||
register "temp3_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp3)
|
||||
register "temp4_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp4)
|
||||
register "temp5_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp5)
|
||||
register "temp6_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp6)
|
||||
register "temp1_source_select" = "0x00" # Use TD1/TR1 as data source for Temp1
|
||||
register "temp2_source_select" = "0x00" # Use TD2/TR2 as data source for Temp2
|
||||
register "temp3_source_select" = "0x00" # Use TD3/TR3 as data source for Temp3
|
||||
register "temp4_source_select" = "0x00" # Use TD4/TR4 as data source for Temp4
|
||||
register "temp5_source_select" = "0x00" # Use TR5 as data source for Temp5
|
||||
register "temp6_source_select" = "0x00" # Use TR6 as data source for Temp6
|
||||
register "tr1_critical_temperature" = "85" # Set TD1/TR1 critical temperature to 85°C
|
||||
register "tr1_critical_hysteresis" = "80" # Set TD1/TR1 critical hysteresis temperature to 80°C
|
||||
register "tr1_warning_temperature" = "70" # Set TD1/TR1 warning temperature to 70°C
|
||||
register "tr1_warning_hysteresis" = "65" # Set TD1/TR1 warning hysteresis temperature to 65°C
|
||||
register "dts_critical_temperature" = "85" # Set DTS (CPU) critical temperature to 85°C
|
||||
register "dts_critical_hysteresis" = "80" # Set DTS (CPU) critical hysteresis temperature to 80°C
|
||||
register "dts_warning_temperature" = "70" # Set DTS (CPU) warning temperature to 70°C
|
||||
register "dts_warning_hysteresis" = "65" # Set DTS (CPU) warning hysteresis temperature to 65°C
|
||||
register "temp1_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C
|
||||
register "temp2_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C
|
||||
register "temp3_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C
|
||||
register "temp4_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C
|
||||
register "temp5_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C
|
||||
register "temp6_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C
|
||||
register "temp1_target_temperature" = "80" # Set Temp1 target temperature to 80°C
|
||||
register "temp2_target_temperature" = "80" # Set Temp1 target temperature to 80°C
|
||||
register "temp3_target_temperature" = "80" # Set Temp1 target temperature to 80°C
|
||||
register "temp4_target_temperature" = "80" # Set Temp1 target temperature to 80°C
|
||||
register "temp5_target_temperature" = "80" # Set Temp1 target temperature to 80°C
|
||||
register "temp6_target_temperature" = "80" # Set Temp1 target temperature to 80°C
|
||||
register "fan1_nonstop" = "7" # Set Fan 1 minimum speed
|
||||
register "fan2_nonstop" = "7" # Set Fan 2 minimum speed
|
||||
register "fan3_nonstop" = "7" # Set Fan 3 minimum speed
|
||||
register "fan4_nonstop" = "7" # Set Fan 4 minimum speed
|
||||
register "fan5_nonstop" = "7" # Set Fan 5 minimum speed
|
||||
register "fan6_nonstop" = "7" # Set Fan 6 minimum speed
|
||||
register "fan7_nonstop" = "7" # Set Fan 7 minimum speed
|
||||
register "fan8_nonstop" = "7" # Set Fan 8 minimum speed
|
||||
register "default_speed" = "100" # All fans to full speed on power up
|
||||
register "fan1_duty" = "100" # Fan 1 to full speed
|
||||
register "fan2_duty" = "100" # Fan 2 to full speed
|
||||
register "fan3_duty" = "100" # Fan 3 to full speed
|
||||
register "fan4_duty" = "100" # Fan 4 to full speed
|
||||
register "fan5_duty" = "100" # Fan 5 to full speed
|
||||
register "fan6_duty" = "100" # Fan 6 to full speed
|
||||
register "fan7_duty" = "100" # Fan 7 to full speed
|
||||
register "fan8_duty" = "100" # Fan 8 to full speed
|
||||
register "vcore1_high_limit_mv" = "1500" # VCORE1 (Node 0) high limit to 1.5V
|
||||
register "vcore1_low_limit_mv" = "900" # VCORE1 (Node 0) low limit to 0.9V
|
||||
register "vcore2_high_limit_mv" = "1500" # VCORE2 (Node 1) high limit to 1.5V
|
||||
register "vcore2_low_limit_mv" = "900" # VCORE2 (Node 1) low limit to 0.9V
|
||||
register "vsen3_high_limit_mv" = "1600" # VSEN1 (Node 0 RAM voltage) high limit to 1.6V
|
||||
register "vsen3_low_limit_mv" = "1100" # VSEN1 (Node 0 RAM voltage) low limit to 1.1V
|
||||
register "vsen4_high_limit_mv" = "1600" # VSEN2 (Node 1 RAM voltage) high limit to 1.6V
|
||||
register "vsen4_low_limit_mv" = "1100" # VSEN2 (Node 1 RAM voltage) low limit to 1.1V
|
||||
register "vsen5_high_limit_mv" = "1250" # VSEN5 (Node 0 HT link voltage) high limit to 1.25V
|
||||
register "vsen5_low_limit_mv" = "1150" # VSEN5 (Node 0 HT link voltage) low limit to 1.15V
|
||||
register "vsen6_high_limit_mv" = "1250" # VSEN6 (Node 1 HT link voltage) high limit to 1.25V
|
||||
register "vsen6_low_limit_mv" = "1150" # VSEN6 (Node 1 HT link voltage) low limit to 1.15V
|
||||
register "vsen7_high_limit_mv" = "1250" # VSEN7 (Northbridge core voltage) high limit to 1.25V
|
||||
register "vsen7_low_limit_mv" = "1050" # VSEN7 (Northbridge core voltage) low limit to 1.05V
|
||||
register "vsen8_high_limit_mv" = "1900" # VSEN8 (+1.8V) high limit to 1.9V
|
||||
register "vsen8_low_limit_mv" = "1700" # VSEN8 (+1.8V) low limit to 1.7V
|
||||
register "vsen9_high_limit_mv" = "1250" # VSEN9 (+1.2V) high limit to 1.25V
|
||||
register "vsen9_low_limit_mv" = "1150" # VSEN9 (+1.2V) low limit to 1.15V
|
||||
register "vsen10_high_limit_mv" = "1150" # VSEN10 (+1.1V) high limit to 1.15V
|
||||
register "vsen10_low_limit_mv" = "1050" # VSEN10 (+1.1V) low limit to 1.05V
|
||||
register "vsen11_high_limit_mv" = "1625" # VSEN11 (5VSB, scaling factor ~3.2) high limit to 5.2V
|
||||
register "vsen11_low_limit_mv" = "1500" # VSEN11 (5VSB, scaling factor ~3.2) low limit to 4.8V
|
||||
register "vsen12_high_limit_mv" = "1083" # VSEN12 (+12V, scaling factor ~12) high limit to 13V
|
||||
register "vsen12_low_limit_mv" = "917" # VSEN12 (+12V, scaling factor ~12) low limit to 11V
|
||||
register "vsen13_high_limit_mv" = "1625" # VSEN13 (+5V, scaling factor ~3.2) high limit to 5.2V
|
||||
register "vsen13_low_limit_mv" = "1500" # VSEN13 (+5V, scaling factor ~3.2) low limit to 4.8V
|
||||
register "vdd_high_limit_mv" = "3500" # 3VDD high limit to 3.5V
|
||||
register "vdd_low_limit_mv" = "3100" # 3VDD low limit to 3.1V
|
||||
register "vsb_high_limit_mv" = "3500" # 3VSB high limit to 3.5V
|
||||
register "vsb_low_limit_mv" = "3100" # 3VSB low limit to 3.1V
|
||||
register "vbat_high_limit_mv" = "3500" # VBAT (+3V) high limit to 3.5V
|
||||
register "vbat_low_limit_mv" = "2500" # VBAT (+3V) low limit to 2.5V
|
||||
register "smbus_aux" = "1" # Device located on auxiliary SMBUS controller
|
||||
device i2c 0x2f on end
|
||||
end
|
||||
end
|
||||
device pci 14.1 on end # IDE 0x439c
|
||||
device pci 14.2 on end # HDA 0x4383 (ASUS MIO add-on card)
|
||||
device pci 14.3 on # LPC 0x439d (SMBUS primary controller)
|
||||
chip superio/winbond/w83667hg-a # Super I/O
|
||||
device pnp 2e.0 off end # FDC; Not available on the KGPE-D16
|
||||
device pnp 2e.1 off end # LPT1; Not available on the KGPE-D16
|
||||
device pnp 2e.2 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 on # COM2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.5 on # PS/2 keyboard & mouse
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.106 off end # SPI: Not available on the KGPE-D16
|
||||
device pnp 2e.107 off end # GIPO6
|
||||
device pnp 2e.207 off end # GIPO7
|
||||
device pnp 2e.307 off end # GIPO8
|
||||
device pnp 2e.407 off end # GIPO9
|
||||
device pnp 2e.8 off end # WDT
|
||||
device pnp 2e.108 off end # GPIO 1
|
||||
device pnp 2e.9 off end # GPIO2
|
||||
device pnp 2e.109 off end # GPIO3
|
||||
device pnp 2e.209 off end # GPIO4
|
||||
device pnp 2e.309 off end # GPIO5
|
||||
device pnp 2e.a on end # ACPI
|
||||
device pnp 2e.b on # HW Monitor
|
||||
io 0x60 = 0x290
|
||||
# IRQ purposefully not assigned to prevent lockups
|
||||
end
|
||||
device pnp 2e.c off end # PECI
|
||||
device pnp 2e.d off end # VID_BUSSEL
|
||||
device pnp 2e.f off end # GPIO_PP_OD
|
||||
end
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 4e.0 on end # TPM module
|
||||
end
|
||||
chip drivers/ipmi # BMC KCS
|
||||
device pnp ca2.0 on end
|
||||
end
|
||||
end
|
||||
device pci 14.4 on # Bridge
|
||||
device pci 1.0 on end # VGA
|
||||
device pci 2.0 on end # FireWire
|
||||
device pci 3.0 on # Slot
|
||||
# Slot # PCI 0
|
||||
end
|
||||
end
|
||||
device pci 14.5 on end # USB OHCI2 0x4399
|
||||
end
|
||||
end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
device pci 18.4 on end
|
||||
device pci 18.5 on end
|
||||
device pci 19.0 on end # Socket 0 node 1
|
||||
device pci 19.1 on end
|
||||
device pci 19.2 on end
|
||||
device pci 19.3 on end
|
||||
device pci 19.4 on end
|
||||
device pci 19.5 on end
|
||||
device pci 1a.0 on end # Socket 1 node 0
|
||||
device pci 1a.1 on end
|
||||
device pci 1a.2 on end
|
||||
device pci 1a.3 on end
|
||||
device pci 1a.4 on end
|
||||
device pci 1a.5 on end
|
||||
device pci 1b.0 on end # Socket 1 node 1
|
||||
device pci 1b.1 on end
|
||||
device pci 1b.2 on end
|
||||
device pci 1b.3 on end
|
||||
device pci 1b.4 on end
|
||||
device pci 1b.5 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
@@ -1,809 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
* Copyright (C) 2005 - 2012 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
|
||||
* Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING: Sleep/Wake is a work in progress and is still somewhat flaky!
|
||||
* Everything else does to the best of my knowledge... (T.P. 01/26/2015)
|
||||
*/
|
||||
|
||||
/*
|
||||
* ISA portions taken from QEMU acpi-dsdt.dsl.
|
||||
*/
|
||||
|
||||
/*
|
||||
* PCI link routing templates taken from ck804.asl and modified for this board
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock (
|
||||
"DSDT.AML", /* Output filename */
|
||||
"DSDT", /* Signature */
|
||||
0x02, /* DSDT Revision, needs to be 2 or higher for 64bit */
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x00000001 /* OEM Revision */
|
||||
)
|
||||
{
|
||||
#include <northbridge/amd/amdfam10/amdfam10_util.asl>
|
||||
#include <southbridge/amd/sr5650/acpi/sr5650.asl>
|
||||
|
||||
/* Some global data */
|
||||
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
|
||||
Name(OSV, Ones) /* Assume nothing */
|
||||
Name(PICM, One) /* Assume APIC */
|
||||
|
||||
/* HPET enable */
|
||||
Name (HPTE, 0x1)
|
||||
|
||||
#include <southbridge/amd/common/acpi/sleepstates.asl>
|
||||
|
||||
/* The _PIC method is called by the OS to choose between interrupt
|
||||
* routing via the i8259 interrupt controller or the APIC.
|
||||
*
|
||||
* _PIC is called with a parameter of 0 for i8259 configuration and
|
||||
* with a parameter of 1 for Local Apic/IOAPIC configuration.
|
||||
*/
|
||||
Method (_PIC, 1, Serialized) {
|
||||
If (Arg0)
|
||||
{
|
||||
\_SB.CIRQ()
|
||||
}
|
||||
Store (Arg0, PICM)
|
||||
}
|
||||
|
||||
/* _PR CPU0 is dynamically supplied by SSDT */
|
||||
/* CPU objects and _PSS entries are dynamically supplied by SSDT */
|
||||
|
||||
Scope(\_GPE) { /* Start Scope GPE */
|
||||
/* General event 3 */
|
||||
Method(_L03) {
|
||||
/* Level-Triggered GPE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* General event 4 */
|
||||
Method(_L04) {
|
||||
/* Level-Triggered GPE */
|
||||
Notify (\_SB.PCI0.PBR0, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* Keyboard controller PME# */
|
||||
Method(_L08) {
|
||||
/* Level-Triggered GPE */
|
||||
Notify(\_SB.PCI0.LPC.PS2K, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.LPC.PS2M, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* USB controller PME# */
|
||||
Method(_L0B) {
|
||||
/* Level-Triggered GPE */
|
||||
Notify (\_SB.PCI0.USB0, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PCI0.USB1, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PCI0.USB2, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PCI0.USB3, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PCI0.USB4, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PCI0.USB5, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PCI0.USB6, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* GPIO0 or GEvent8 event */
|
||||
Method(_L18) {
|
||||
/* Level-Triggered GPE */
|
||||
Notify (\_SB.PCI0.PCE1, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PCI0.NICA, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PCI0.NICB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PCI0.PCE4, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PCI0.PCE5, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify (\_SB.PCI0.PCE3, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
} /* End Scope GPE */
|
||||
|
||||
/* Root of the bus hierarchy */
|
||||
Scope (\_SB)
|
||||
{
|
||||
/* Top southbridge PCI device (SR5690 + SP5100) */
|
||||
Device (PCI0)
|
||||
{
|
||||
/* BUS0 root bus */
|
||||
|
||||
Name (_HID, EisaId ("PNP0A08")) /* PCI-e root bus (SR5690) */
|
||||
Name (_CID, EisaId ("PNP0A03")) /* PCI root bus (SP5100) */
|
||||
Name (_ADR, 0x00180001)
|
||||
Name (_UID, 0x00)
|
||||
|
||||
Name (HCIN, 0x00) // HC1
|
||||
|
||||
Method (_BBN, 0, NotSerialized)
|
||||
{
|
||||
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
|
||||
}
|
||||
|
||||
/* Operating System Capabilities Method */
|
||||
Method(_OSC,4)
|
||||
{
|
||||
/* Let OS control everything */
|
||||
Return (Arg3)
|
||||
}
|
||||
|
||||
External (BUSN)
|
||||
External (MMIO)
|
||||
External (PCIO)
|
||||
External (SBLK)
|
||||
External (TOM1)
|
||||
External (HCLK)
|
||||
External (SBDN)
|
||||
External (HCDN)
|
||||
External (CBST)
|
||||
|
||||
/* PCI Routing Tables */
|
||||
Name (PR00, Package () {
|
||||
/* PIC */
|
||||
/* Top southbridge device (SR5690) */
|
||||
/* HT Link */
|
||||
Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 },
|
||||
|
||||
/* PCI-E Slot 1 (Bridge) */
|
||||
Package (0x04) { 0x0002FFFF, 0x00, LNKE, 0x00 },
|
||||
|
||||
/* NIC A (Bridge) */
|
||||
Package (0x04) { 0x0009FFFF, 0x00, LNKF, 0x00 },
|
||||
|
||||
/* NIC B (Bridge) */
|
||||
Package (0x04) { 0x000AFFFF, 0x00, LNKG, 0x00 },
|
||||
|
||||
/* PCI-E Slot 4 (Bridge) */
|
||||
Package (0x04) { 0x000BFFFF, 0x00, LNKG, 0x00 },
|
||||
|
||||
/* PCI-E Slot 5 (Bridge) */
|
||||
Package (0x04) { 0x000CFFFF, 0x00, LNKG, 0x00 },
|
||||
|
||||
/* PCI-E Slot 3 (Bridge) */
|
||||
Package (0x04) { 0x000DFFFF, 0x00, LNKG, 0x00 },
|
||||
|
||||
/* Bottom southbridge device (SP5100) */
|
||||
/* SATA 0 */
|
||||
Package (0x04) { 0x0011FFFF, 0x00, LNKG, 0x00 },
|
||||
|
||||
/* USB 0 */
|
||||
Package (0x04) { 0x0012FFFF, 0x00, LNKA, 0x00 },
|
||||
Package (0x04) { 0x0012FFFF, 0x01, LNKB, 0x00 },
|
||||
Package (0x04) { 0x0012FFFF, 0x02, LNKC, 0x00 },
|
||||
Package (0x04) { 0x0012FFFF, 0x03, LNKD, 0x00 },
|
||||
|
||||
/* USB 1 */
|
||||
Package (0x04) { 0x0013FFFF, 0x00, LNKC, 0x00 },
|
||||
Package (0x04) { 0x0013FFFF, 0x01, LNKD, 0x00 },
|
||||
Package (0x04) { 0x0013FFFF, 0x02, LNKA, 0x00 },
|
||||
Package (0x04) { 0x0013FFFF, 0x03, LNKB, 0x00 },
|
||||
|
||||
/* SMBUS / IDE / LPC / VGA / FireWire / PCI Slot 0 */
|
||||
Package (0x04) { 0x0014FFFF, 0x00, LNKA, 0x00 },
|
||||
Package (0x04) { 0x0014FFFF, 0x01, LNKB, 0x00 },
|
||||
Package (0x04) { 0x0014FFFF, 0x02, LNKC, 0x00 },
|
||||
Package (0x04) { 0x0014FFFF, 0x03, LNKD, 0x00 },
|
||||
})
|
||||
|
||||
Name (AR00, Package () {
|
||||
/* APIC */
|
||||
/* Top southbridge device (SR5690) */
|
||||
/* HT Link */
|
||||
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 55 },
|
||||
|
||||
/* PCI-E Slot 1 (Bridge) */
|
||||
Package (0x04) { 0x0002FFFF, 0x00, 0x00, 52 },
|
||||
|
||||
/* NIC A (Bridge) */
|
||||
Package (0x04) { 0x0009FFFF, 0x00, 0x00, 53 },
|
||||
|
||||
/* NIC B (Bridge) */
|
||||
Package (0x04) { 0x000AFFFF, 0x00, 0x00, 54 },
|
||||
|
||||
/* PCI-E Slot 4 (Bridge) */
|
||||
Package (0x04) { 0x000BFFFF, 0x00, 0x00, 54 },
|
||||
|
||||
/* PCI-E Slot 5 (Bridge) */
|
||||
Package (0x04) { 0x000CFFFF, 0x00, 0x00, 54 },
|
||||
|
||||
/* PCI-E Slot 3 (Bridge) */
|
||||
Package (0x04) { 0x000DFFFF, 0x00, 0x00, 54 },
|
||||
|
||||
/* Bottom southbridge device (SP5100) */
|
||||
/* SATA 0 */
|
||||
Package (0x04) { 0x0011FFFF, 0x00, 0x00, 22 },
|
||||
|
||||
/* USB 0 */
|
||||
Package (0x04) { 0x0012FFFF, 0x00, 0x00, 16 },
|
||||
Package (0x04) { 0x0012FFFF, 0x01, 0x00, 17 },
|
||||
Package (0x04) { 0x0012FFFF, 0x02, 0x00, 18 },
|
||||
Package (0x04) { 0x0012FFFF, 0x03, 0x00, 19 },
|
||||
|
||||
/* USB 1 */
|
||||
Package (0x04) { 0x0013FFFF, 0x00, 0x00, 18 },
|
||||
Package (0x04) { 0x0013FFFF, 0x01, 0x00, 19 },
|
||||
Package (0x04) { 0x0013FFFF, 0x02, 0x00, 16 },
|
||||
Package (0x04) { 0x0013FFFF, 0x03, 0x00, 17 },
|
||||
|
||||
/* SMBUS / IDE / LPC / VGA / FireWire / PCI Slot 0 */
|
||||
Package (0x04) { 0x0014FFFF, 0x00, 0x00, 16 },
|
||||
Package (0x04) { 0x0014FFFF, 0x01, 0x00, 17 },
|
||||
Package (0x04) { 0x0014FFFF, 0x02, 0x00, 18 },
|
||||
Package (0x04) { 0x0014FFFF, 0x03, 0x00, 19 },
|
||||
})
|
||||
|
||||
Name (PR01, Package () {
|
||||
/* PIC */
|
||||
Package (0x04) { 0x1FFFF, 0x00, LNKF, 0x00 },
|
||||
Package (0x04) { 0x2FFFF, 0x00, LNKE, 0x00 },
|
||||
Package (0x04) { 0x3FFFF, 0x00, LNKG, 0x00 },
|
||||
Package (0x04) { 0x3FFFF, 0x01, LNKH, 0x00 },
|
||||
Package (0x04) { 0x3FFFF, 0x02, LNKE, 0x00 },
|
||||
Package (0x04) { 0x3FFFF, 0x03, LNKF, 0x00 },
|
||||
})
|
||||
|
||||
Name (AR01, Package () {
|
||||
/* APIC */
|
||||
Package (0x04) { 0x1FFFF, 0x00, 0x00, 21 },
|
||||
Package (0x04) { 0x2FFFF, 0x00, 0x00, 20 },
|
||||
Package (0x04) { 0x3FFFF, 0x00, 0x00, 22 },
|
||||
Package (0x04) { 0x3FFFF, 0x01, 0x00, 23 },
|
||||
Package (0x04) { 0x3FFFF, 0x02, 0x00, 20 },
|
||||
Package (0x04) { 0x3FFFF, 0x03, 0x00, 21 },
|
||||
})
|
||||
|
||||
Name (PR02, Package () {
|
||||
/* PIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 },
|
||||
})
|
||||
|
||||
Name (AR02, Package () {
|
||||
/* APIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, 0x00, 24 },
|
||||
Package (0x04) { 0xFFFF, 0x01, 0x00, 25 },
|
||||
Package (0x04) { 0xFFFF, 0x02, 0x00, 26 },
|
||||
Package (0x04) { 0xFFFF, 0x03, 0x00, 27 },
|
||||
})
|
||||
|
||||
Name (PR03, Package () {
|
||||
/* PIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, LNKE, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x01, LNKF, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x02, LNKG, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x03, LNKH, 0x00 },
|
||||
})
|
||||
|
||||
Name (AR03, Package () {
|
||||
/* APIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, 0x00, 44 },
|
||||
Package (0x04) { 0xFFFF, 0x01, 0x00, 45 },
|
||||
Package (0x04) { 0xFFFF, 0x02, 0x00, 46 },
|
||||
Package (0x04) { 0xFFFF, 0x03, 0x00, 47 },
|
||||
})
|
||||
|
||||
Name (PR04, Package () {
|
||||
/* PIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 },
|
||||
})
|
||||
|
||||
Name (AR04, Package () {
|
||||
/* APIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, 0x00, 48 },
|
||||
Package (0x04) { 0xFFFF, 0x01, 0x00, 49 },
|
||||
Package (0x04) { 0xFFFF, 0x02, 0x00, 50 },
|
||||
Package (0x04) { 0xFFFF, 0x03, 0x00, 51 },
|
||||
})
|
||||
|
||||
Name (PR05, Package () {
|
||||
/* PIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, LNKH, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x01, LNKE, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x02, LNKF, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x03, LNKG, 0x00 },
|
||||
})
|
||||
|
||||
Name (AR05, Package () {
|
||||
/* APIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, 0x00, 47 },
|
||||
Package (0x04) { 0xFFFF, 0x01, 0x00, 44 },
|
||||
Package (0x04) { 0xFFFF, 0x02, 0x00, 45 },
|
||||
Package (0x04) { 0xFFFF, 0x03, 0x00, 46 },
|
||||
})
|
||||
|
||||
Name (PR06, Package () {
|
||||
/* PIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 },
|
||||
})
|
||||
|
||||
Name (AR06, Package () {
|
||||
/* APIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, 0x00, 32 },
|
||||
Package (0x04) { 0xFFFF, 0x01, 0x00, 33 },
|
||||
Package (0x04) { 0xFFFF, 0x02, 0x00, 34 },
|
||||
Package (0x04) { 0xFFFF, 0x03, 0x00, 35 },
|
||||
})
|
||||
|
||||
Name (PR07, Package () {
|
||||
/* PIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, LNKE, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x01, LNKF, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x02, LNKG, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x03, LNKH, 0x00 },
|
||||
})
|
||||
|
||||
Name (AR07, Package () {
|
||||
/* APIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, 0x00, 36 },
|
||||
Package (0x04) { 0xFFFF, 0x01, 0x00, 37 },
|
||||
Package (0x04) { 0xFFFF, 0x02, 0x00, 38 },
|
||||
Package (0x04) { 0xFFFF, 0x03, 0x00, 39 },
|
||||
})
|
||||
|
||||
Name (PR08, Package () {
|
||||
/* PIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 },
|
||||
Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 },
|
||||
})
|
||||
|
||||
Name (AR08, Package () {
|
||||
/* APIC */
|
||||
Package (0x04) { 0xFFFF, 0x00, 0x00, 40 },
|
||||
Package (0x04) { 0xFFFF, 0x01, 0x00, 41 },
|
||||
Package (0x04) { 0xFFFF, 0x02, 0x00, 42 },
|
||||
Package (0x04) { 0xFFFF, 0x03, 0x00, 43 },
|
||||
})
|
||||
|
||||
/* PCI Resource Tables */
|
||||
|
||||
/* PCI Resource Settings Access */
|
||||
Method (_CRS, 0, Serialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16,
|
||||
0x0CF8, // Address Range Minimum
|
||||
0x0CF8, // Address Range Maximum
|
||||
0x01, // Address Alignment
|
||||
0x08, // Address Length
|
||||
)
|
||||
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
0x0000, // Address Space Granularity
|
||||
0x0000, // Address Range Minimum
|
||||
0x0CF7, // Address Range Maximum
|
||||
0x0000, // Address Translation Offset
|
||||
0x0CF8, // Address Length
|
||||
,, , TypeStatic)
|
||||
})
|
||||
/* Methods below use SSDT to get actual MMIO regs
|
||||
The IO ports are from 0xd00, optionally an VGA,
|
||||
otherwise the info from MMIO is used.
|
||||
\_SB.GXXX(node, link)
|
||||
*/
|
||||
Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
|
||||
Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
|
||||
Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
|
||||
Return (Local3)
|
||||
}
|
||||
|
||||
/* PCI Routing Table Access */
|
||||
Method (_PRT, 0, NotSerialized) {
|
||||
If (PICM) {
|
||||
Return (AR00)
|
||||
} Else {
|
||||
Return (PR00)
|
||||
}
|
||||
}
|
||||
|
||||
/* 0:11.0 SP5100 SATA 0 */
|
||||
Device(SAT0)
|
||||
{
|
||||
Name (_ADR, 0x00110000) // _ADR: Address
|
||||
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
||||
#include <southbridge/amd/sb700/acpi/sata.asl>
|
||||
}
|
||||
|
||||
/* 0:12.0 SP5100 USB 0 */
|
||||
Device (USB0)
|
||||
{
|
||||
Name (_ADR, 0x00120000) // _ADR: Address
|
||||
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
|
||||
/* 0:12.1 SP5100 USB 1 */
|
||||
Device (USB1)
|
||||
{
|
||||
Name (_ADR, 0x00120001) // _ADR: Address
|
||||
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
|
||||
/* 0:12.2 SP5100 USB 2 */
|
||||
Device (USB2)
|
||||
{
|
||||
Name (_ADR, 0x00120002) // _ADR: Address
|
||||
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
|
||||
/* 0:13.0 SP5100 USB 3 */
|
||||
Device (USB3)
|
||||
{
|
||||
Name (_ADR, 0x00130000) // _ADR: Address
|
||||
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
|
||||
/* 0:13.1 SP5100 USB 4 */
|
||||
Device (USB4)
|
||||
{
|
||||
Name (_ADR, 0x00130001) // _ADR: Address
|
||||
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
|
||||
/* 0:13.2 SP5100 USB 5 */
|
||||
Device (USB5)
|
||||
{
|
||||
Name (_ADR, 0x00130002) // _ADR: Address
|
||||
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
|
||||
/* 0:14.1 SP5100 IDE Controller */
|
||||
Device (IDEC)
|
||||
{
|
||||
Name (_ADR, 0x00140001) // _ADR: Address
|
||||
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
||||
#include <southbridge/amd/sb700/acpi/ide.asl>
|
||||
}
|
||||
|
||||
/* 0:14.3 SP5100 LPC */
|
||||
Device (LPC) {
|
||||
Name (_HID, EisaId ("PNP0A05"))
|
||||
Name (_ADR, 0x00140003)
|
||||
|
||||
/* Real Time Clock Device */
|
||||
Device(RTC0) {
|
||||
Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
|
||||
Name(BUF0, ResourceTemplate() {
|
||||
IO(Decode16, 0x0070, 0x0070, 0x01, 0x02)
|
||||
})
|
||||
Name(BUF1, ResourceTemplate() {
|
||||
IRQNoFlags() { 8 }
|
||||
IO(Decode16, 0x0070, 0x0070, 0x01, 0x02)
|
||||
})
|
||||
Method(_CRS, 0) {
|
||||
If(HPTE) {
|
||||
Return(BUF0)
|
||||
}
|
||||
Return(BUF1)
|
||||
}
|
||||
}
|
||||
|
||||
Device(TMR) { /* Timer */
|
||||
Name(_HID,EISAID("PNP0100")) /* System Timer */
|
||||
Name(BUF0, ResourceTemplate() {
|
||||
IO(Decode16, 0x0040, 0x0040, 0x01, 0x04)
|
||||
})
|
||||
Name(BUF1, ResourceTemplate() {
|
||||
IRQNoFlags() { 0 }
|
||||
IO(Decode16, 0x0040, 0x0040, 0x01, 0x04)
|
||||
})
|
||||
Method(_CRS, 0) {
|
||||
If(HPTE) {
|
||||
Return(BUF0)
|
||||
}
|
||||
Return(BUF1)
|
||||
}
|
||||
}
|
||||
|
||||
Device(SPKR) { /* Speaker */
|
||||
Name(_HID,EISAID("PNP0800")) /* AT style speaker */
|
||||
Name(_CRS, ResourceTemplate() {
|
||||
IO(Decode16, 0x0061, 0x0061, 0, 1)
|
||||
})
|
||||
}
|
||||
|
||||
Device(PIC) {
|
||||
Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
|
||||
Name(_CRS, ResourceTemplate() {
|
||||
IRQNoFlags() { 2 }
|
||||
IO(Decode16,0x0020, 0x0020, 0, 2)
|
||||
IO(Decode16,0x00A0, 0x00A0, 0, 2)
|
||||
})
|
||||
}
|
||||
|
||||
Device(MAD) { /* 8257 DMA */
|
||||
Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
|
||||
Name(_CRS, ResourceTemplate() {
|
||||
DMA(Compatibility,BusMaster,Transfer8){4}
|
||||
IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
|
||||
IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
|
||||
IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
|
||||
IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
|
||||
IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
|
||||
IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
|
||||
}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
|
||||
}
|
||||
|
||||
Device(COPR) {
|
||||
Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
|
||||
Name(_CRS, ResourceTemplate() {
|
||||
IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
|
||||
IRQNoFlags(){13}
|
||||
})
|
||||
}
|
||||
|
||||
#include <superio/winbond/w83667hg-a/ps2_controller.asl>
|
||||
|
||||
/* UART 1 */
|
||||
Device (URT1)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART
|
||||
Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0f) // Always enable
|
||||
}
|
||||
Name (_PRS, ResourceTemplate() {
|
||||
StartDependentFn(0, 1) {
|
||||
IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
|
||||
IRQNoFlags() { 4 }
|
||||
} EndDependentFn()
|
||||
})
|
||||
Method (_CRS, 0)
|
||||
{
|
||||
Return(ResourceTemplate() {
|
||||
IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
|
||||
IRQNoFlags() { 4 }
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
/* UART 2 */
|
||||
Device (URT2)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART
|
||||
Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0f) // Always enable
|
||||
}
|
||||
Name (_PRS, ResourceTemplate() {
|
||||
StartDependentFn(0, 1) {
|
||||
IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
|
||||
IRQNoFlags() { 3 }
|
||||
} EndDependentFn()
|
||||
})
|
||||
Method (_CRS, 0)
|
||||
{
|
||||
Return(ResourceTemplate() {
|
||||
IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
|
||||
IRQNoFlags() { 3 }
|
||||
})
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* High Precision Event Timer */
|
||||
Device (HPET)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0103"))
|
||||
Name (CRS, ResourceTemplate ()
|
||||
{
|
||||
Memory32Fixed(ReadOnly, 0xFED00000, 0x00000400)
|
||||
})
|
||||
Method (_STA, 0)
|
||||
{
|
||||
If(HPTE) {
|
||||
Return (0x0F)
|
||||
}
|
||||
Return (0x0)
|
||||
}
|
||||
Method(_CRS, 0)
|
||||
{
|
||||
Return(CRS)
|
||||
}
|
||||
}
|
||||
|
||||
/* 0:14.4 PCI Bridge */
|
||||
Device (PBR0)
|
||||
{
|
||||
Name (_ADR, 0x00140004) // _ADR: Address
|
||||
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
|
||||
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
||||
{
|
||||
If (PICM) {
|
||||
Return (AR01)
|
||||
} Else {
|
||||
Return (PR01)
|
||||
}
|
||||
}
|
||||
Device (SLT1)
|
||||
{
|
||||
Name (_ADR, 0xFFFF) // _ADR: Address
|
||||
Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
}
|
||||
|
||||
/* 0:14.5 SP5100 USB 6 */
|
||||
Device (USB6)
|
||||
{
|
||||
Name (_ADR, 0x00140005) // _ADR: Address
|
||||
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
|
||||
/* 2:00.0 PCIe x16 */
|
||||
Device (PCE1)
|
||||
{
|
||||
Name (_ADR, 0x00020000) // _ADR: Address
|
||||
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
|
||||
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
||||
{
|
||||
If (PICM) {
|
||||
Return (AR02)
|
||||
} Else {
|
||||
Return (PR02)
|
||||
}
|
||||
}
|
||||
Device (SLT1)
|
||||
{
|
||||
Name (_ADR, 0xFFFF) // _ADR: Address
|
||||
Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
}
|
||||
|
||||
/* 1:00.0 PIKE */
|
||||
Device (PIKE)
|
||||
{
|
||||
Name (_ADR, 0x00040000) // _ADR: Address
|
||||
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
|
||||
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
||||
{
|
||||
If (PICM) {
|
||||
Return (AR03)
|
||||
} Else {
|
||||
Return (PR03)
|
||||
}
|
||||
}
|
||||
Device (SLT1)
|
||||
{
|
||||
Name (_ADR, 0xFFFF) // _ADR: Address
|
||||
Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
}
|
||||
|
||||
/* 3:00.0 PCIe NIC A */
|
||||
Device (NICA)
|
||||
{
|
||||
Name (_ADR, 0x00090000) // _ADR: Address
|
||||
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
|
||||
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
||||
{
|
||||
If (PICM) {
|
||||
Return (AR04)
|
||||
} Else {
|
||||
Return (PR04)
|
||||
}
|
||||
}
|
||||
Device (BDC1)
|
||||
{
|
||||
Name (_ADR, Zero) // _ADR: Address
|
||||
}
|
||||
}
|
||||
|
||||
/* 4:00.0 PCIe NIC B */
|
||||
Device (NICB)
|
||||
{
|
||||
Name (_ADR, 0x000A0000) // _ADR: Address
|
||||
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
|
||||
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
||||
{
|
||||
If (PICM) {
|
||||
Return (AR05)
|
||||
} Else {
|
||||
Return (PR05)
|
||||
}
|
||||
}
|
||||
Device (BDC2)
|
||||
{
|
||||
Name (_ADR, Zero) // _ADR: Address
|
||||
}
|
||||
}
|
||||
|
||||
/* 5:00.0 PCIe x16 */
|
||||
Device (PCE4)
|
||||
{
|
||||
Name (_ADR, 0x000B0000) // _ADR: Address
|
||||
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
|
||||
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
||||
{
|
||||
If (PICM) {
|
||||
Return (AR06)
|
||||
} Else {
|
||||
Return (PR06)
|
||||
}
|
||||
}
|
||||
Device (SLT1)
|
||||
{
|
||||
Name (_ADR, 0xFFFF) // _ADR: Address
|
||||
Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
}
|
||||
|
||||
/* 6:00.0 PCIe x16 */
|
||||
Device (PCE5)
|
||||
{
|
||||
Name (_ADR, 0x000C0000) // _ADR: Address
|
||||
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
|
||||
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
||||
{
|
||||
If (PICM) {
|
||||
Return (AR07)
|
||||
} Else {
|
||||
Return (PR07)
|
||||
}
|
||||
}
|
||||
Device (SLT1)
|
||||
{
|
||||
Name (_ADR, 0xFFFF) // _ADR: Address
|
||||
Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
}
|
||||
|
||||
/* 7:00.0 PCIe x16 */
|
||||
Device (PCE3)
|
||||
{
|
||||
Name (_ADR, 0x000D0000) // _ADR: Address
|
||||
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
|
||||
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
||||
{
|
||||
If (PICM) {
|
||||
Return (AR08)
|
||||
} Else {
|
||||
Return (PR08)
|
||||
}
|
||||
}
|
||||
Device (SLT1)
|
||||
{
|
||||
Name (_ADR, 0xFFFF) // _ADR: Address
|
||||
Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Device (PWRB) { /* Start Power button device */
|
||||
Name(_HID, EISAID("PNP0C0C"))
|
||||
Name(_UID, 0xAA)
|
||||
Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
|
||||
Name(_STA, 0x0B) /* sata is invisible */
|
||||
}
|
||||
}
|
||||
|
||||
#include "acpi/pm_ctrl.asl"
|
||||
|
||||
}
|
||||
@@ -1,30 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/pci.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <cpu/amd/multicore.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
void get_bus_conf(void)
|
||||
{
|
||||
get_default_pci1234(1);
|
||||
|
||||
sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
|
||||
|
||||
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
|
||||
}
|
||||
@@ -1,122 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2015 Raptor Engineering
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
/* Free irqs are 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15 */
|
||||
#define IRQBM ((1 << 3)|(1 << 4)|(1 << 5)|(1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 12)|(1 << 14)|(1 << 15))
|
||||
|
||||
#define LNKA 1
|
||||
#define LNKB 2
|
||||
#define LNKC 3
|
||||
#define LNKD 4
|
||||
|
||||
/*
|
||||
* For simplicity map LNK[E-H] to LNK[A-D].
|
||||
* This also means we are 82C596 compatible.
|
||||
* Needs 0:11.0 0x46[4] set to 0.
|
||||
*/
|
||||
#define LNKE 1
|
||||
#define LNKF 2
|
||||
#define LNKG 3
|
||||
#define LNKH 4
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
|
||||
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
|
||||
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
|
||||
u8 slot, u8 rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
u32 slot_num;
|
||||
u8 *v;
|
||||
|
||||
u8 sum = 0;
|
||||
int i;
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be between 0xf0000 & 0x100000 */
|
||||
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (u8 *) (addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
/* Where the interrupt router resides */
|
||||
pirq->rtr_bus = pirq_router_bus;
|
||||
pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
pirq->rtr_vendor = PCI_VENDOR_ID_ATI;
|
||||
pirq->rtr_device = PCI_DEVICE_ID_ATI_SB700_PCI;
|
||||
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *)(&pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
|
||||
/* pci bridge */
|
||||
write_pirq_info(pirq_info, pirq_router_bus,
|
||||
PCI_DEVFN(0x14, 4), LNKA, IRQBM, LNKB,
|
||||
IRQBM, LNKC, IRQBM, LNKD, IRQBM, 0, 0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "done.\n");
|
||||
|
||||
return (unsigned long)pirq_info;
|
||||
}
|
||||
@@ -1,114 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/mmio.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <southbridge/amd/sb700/sb700.h>
|
||||
#include <southbridge/amd/sr5650/cmn.h>
|
||||
|
||||
void set_pcie_reset(void)
|
||||
{
|
||||
struct device *pcie_core_dev;
|
||||
|
||||
pcie_core_dev = pcidev_on_root(0, 0);
|
||||
set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828);
|
||||
set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x00000028);
|
||||
}
|
||||
|
||||
void set_pcie_dereset(void)
|
||||
{
|
||||
struct device *pcie_core_dev;
|
||||
|
||||
pcie_core_dev = pcidev_on_root(0, 0);
|
||||
set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F);
|
||||
set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x0000006F);
|
||||
}
|
||||
|
||||
/*************************************************
|
||||
* enable the dedicated function in kgpe-d16 board.
|
||||
* This function is called earlier than sr5650_enable.
|
||||
*************************************************/
|
||||
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
printk(BIOS_INFO, "Mainboard KGPE-D16 Enable. dev=0x%p\n", dev);
|
||||
|
||||
msr_t msr, msr2;
|
||||
|
||||
/* TOP_MEM: the top of DRAM below 4G */
|
||||
msr = rdmsr(TOP_MEM);
|
||||
printk
|
||||
(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
|
||||
__func__, msr.lo, msr.hi);
|
||||
|
||||
/* TOP_MEM2: the top of DRAM above 4G */
|
||||
msr2 = rdmsr(TOP_MEM2);
|
||||
printk
|
||||
(BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
|
||||
__func__, msr2.lo, msr2.hi);
|
||||
|
||||
set_pcie_dereset();
|
||||
/* get_ide_dma66(); */
|
||||
}
|
||||
|
||||
/* override the default SATA PHY setup */
|
||||
void sb7xx_51xx_setup_sata_phys(struct device *dev)
|
||||
{
|
||||
/* RPR7.6.1 Program the PHY Global Control to 0x2C00 */
|
||||
pci_write_config16(dev, 0x86, 0x2c00);
|
||||
|
||||
/* RPR7.6.2 SATA GENI PHY ports setting */
|
||||
pci_write_config32(dev, 0x88, 0x01b48016);
|
||||
pci_write_config32(dev, 0x8c, 0x01b48016);
|
||||
pci_write_config32(dev, 0x90, 0x01b48016);
|
||||
pci_write_config32(dev, 0x94, 0x01b48016);
|
||||
pci_write_config32(dev, 0x98, 0x01b48016);
|
||||
pci_write_config32(dev, 0x9c, 0x01b48016);
|
||||
|
||||
/* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */
|
||||
pci_write_config16(dev, 0xa0, 0xa07a);
|
||||
pci_write_config16(dev, 0xa2, 0xa07a);
|
||||
pci_write_config16(dev, 0xa4, 0xa07a);
|
||||
pci_write_config16(dev, 0xa6, 0xa07a);
|
||||
pci_write_config16(dev, 0xa8, 0xa07a);
|
||||
pci_write_config16(dev, 0xaa, 0xa07a);
|
||||
}
|
||||
|
||||
/* override the default SATA port setup */
|
||||
void sb7xx_51xx_setup_sata_port_indication(void *sata_bar5)
|
||||
{
|
||||
uint32_t dword;
|
||||
|
||||
/* RPR7.9 Program Port Indication Registers */
|
||||
dword = read32(sata_bar5 + 0xf8);
|
||||
dword &= ~(0x3f << 12); /* All ports are iSATA */
|
||||
dword &= ~0x3f;
|
||||
write32(sata_bar5 + 0xf8, dword);
|
||||
|
||||
dword = read32(sata_bar5 + 0xfc);
|
||||
dword &= ~(0x1 << 20); /* No eSATA ports are present */
|
||||
write32(sata_bar5 + 0xfc, dword);
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
@@ -1,219 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2015 Raptor Engineering
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <stdint.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
u32 apicid_sp5100;
|
||||
u32 apicid_sr5650;
|
||||
struct device *dev;
|
||||
uint8_t sp5100_bus_number;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
|
||||
apicid_sp5100 = 0x0;
|
||||
else
|
||||
apicid_sp5100 = 0x20;
|
||||
apicid_sr5650 = apicid_sp5100 + 1;
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
{
|
||||
uint32_t *dword_ptr;
|
||||
uint32_t dword;
|
||||
uint16_t word;
|
||||
uint8_t byte;
|
||||
|
||||
sp5100_bus_number = 0; //bus_sp5100[0]; TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0.
|
||||
|
||||
dev = dev_find_slot(sp5100_bus_number, PCI_DEVFN(0x14, 0));
|
||||
if (dev) {
|
||||
dword_ptr = (u32 *)(pci_read_config32(dev, 0x74) & 0xfffffff0);
|
||||
smp_write_ioapic(mc, apicid_sp5100, 0x11, dword_ptr);
|
||||
|
||||
/* Initialize interrupt mapping */
|
||||
/* USB 1 & 2 */
|
||||
word = pci_read_config16(dev, 0xbe);
|
||||
word &= ~0x3f3f;
|
||||
word |= 0x0; /* 0: INTA, ...., 7: INTH */
|
||||
word |= (0x1 << 3); /* 0: INTA, ...., 7: INTH */
|
||||
word |= (0x2 << 8); /* 0: INTA, ...., 7: INTH */
|
||||
word |= (0x3 << 11); /* 0: INTA, ...., 7: INTH */
|
||||
pci_write_config16(dev, 0xbe, word);
|
||||
|
||||
/* USB 3 */
|
||||
byte = pci_read_config8(dev, 0x63);
|
||||
byte &= 0xf8;
|
||||
byte |= (0x2 << 4); /* 0: INTA, ...., 7: INTH */
|
||||
pci_write_config8(dev, 0x63, byte);
|
||||
|
||||
dword = pci_read_config32(dev, 0xac);
|
||||
|
||||
/* SATA */
|
||||
dword &= ~(7 << 26);
|
||||
dword |= (0x6 << 26); /* 0: INTA, ...., 7: INTH */
|
||||
|
||||
/* Hide IDE */
|
||||
dword &= ~(0x00080000);
|
||||
|
||||
/* dword_ptr |= 1 << 22; PIC and APIC co exists */
|
||||
pci_write_config32(dev, 0xac, dword);
|
||||
|
||||
/*
|
||||
* 00:12.0: PROG SATA : INT F
|
||||
* 00:13.0: INTA USB_0
|
||||
* 00:13.1: INTB USB_1
|
||||
* 00:13.2: INTC USB_2
|
||||
* 00:13.3: INTD USB_3
|
||||
* 00:13.4: INTC USB_4
|
||||
* 00:13.5: INTD USB2
|
||||
* 00:14.1: INTA IDE
|
||||
* 00:14.2: Prog HDA : INT E
|
||||
* 00:14.5: INTB ACI
|
||||
* 00:14.6: INTB MCI
|
||||
*/
|
||||
}
|
||||
dev = pcidev_on_root(0, 0);
|
||||
if (dev) {
|
||||
pci_write_config32(dev, 0xF8, 0x1);
|
||||
dword_ptr = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
|
||||
smp_write_ioapic(mc, apicid_sr5650, 0x11, dword_ptr);
|
||||
}
|
||||
}
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0);
|
||||
|
||||
/* SR5650 devices */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((0)<<2)|(2)), apicid_sr5650, 31); /* Device 0 Function 2 (LNKA, APIC pin 31) */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((2)<<2)|(0)), apicid_sr5650, 28); /* Device 2 (LNKE, APIC pin 28) */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((4)<<2)|(0)), apicid_sr5650, 28); /* Device 4 (LNKF, APIC pin 28) */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((9)<<2)|(0)), apicid_sr5650, 29); /* Device 9 (LNKG, APIC pin 29) */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((10)<<2)|(0)), apicid_sr5650, 30); /* Device 10 (LNKG, APIC pin 30) */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((11)<<2)|(0)), apicid_sr5650, 30); /* Device 11 (LNKG, APIC pin 30) */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sr5650, 30); /* Device 12 (LNKG, APIC pin 30) */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 30); /* Device 13 (LNKG, APIC pin 30)) */
|
||||
|
||||
dev = pcidev_on_root(0x2, 0);
|
||||
if (dev && dev->enabled) {
|
||||
uint8_t bus_pci = dev->link_list->secondary;
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x2)|(0)), apicid_sr5650, 0); /* card behind dev2 */
|
||||
}
|
||||
dev = pcidev_on_root(0x4, 0);
|
||||
if (dev && dev->enabled) {
|
||||
uint8_t bus_pci = dev->link_list->secondary;
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x4)|(0)), apicid_sr5650, 0); /* PIKE */
|
||||
}
|
||||
dev = pcidev_on_root(0x9, 0);
|
||||
if (dev && dev->enabled) {
|
||||
uint8_t bus_pci = dev->link_list->secondary;
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x9)|(0)), apicid_sr5650, 23); /* NIC A */
|
||||
}
|
||||
dev = pcidev_on_root(0xa, 0);
|
||||
if (dev && dev->enabled) {
|
||||
uint8_t bus_pci = dev->link_list->secondary;
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xa)|(0)), apicid_sr5650, 24); /* NIC B */
|
||||
}
|
||||
dev = pcidev_on_root(0xb, 0);
|
||||
if (dev && dev->enabled) {
|
||||
uint8_t bus_pci = dev->link_list->secondary;
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xb)|(0)), apicid_sr5650, 0); /* card behind dev11 */
|
||||
}
|
||||
dev = pcidev_on_root(0xc, 0);
|
||||
if (dev && dev->enabled) {
|
||||
uint8_t bus_pci = dev->link_list->secondary;
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xc)|(0)), apicid_sr5650, 0); /* card behind dev12 */
|
||||
}
|
||||
dev = pcidev_on_root(0xd, 0);
|
||||
if (dev && dev->enabled) {
|
||||
uint8_t bus_pci = dev->link_list->secondary;
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xd)|(0)), apicid_sr5650, 0); /* card behind dev13 */
|
||||
}
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, interrupt_signal, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(interrupt_signal)), apicid_sp5100, (pin))
|
||||
|
||||
/* USB1 */
|
||||
PCI_INT(sp5100_bus_number, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */
|
||||
PCI_INT(sp5100_bus_number, 0x12, 0x1, 0x11); /* OHCI1 Port 3~5 */
|
||||
|
||||
/* USB2 */
|
||||
PCI_INT(sp5100_bus_number, 0x13, 0x0, 0x12); /* OHCI0 Port 6~8 */
|
||||
PCI_INT(sp5100_bus_number, 0x13, 0x1, 0x13); /* EHCI Port 6~11 */
|
||||
|
||||
/* USB3 */
|
||||
PCI_INT(sp5100_bus_number, 0x14, 0x3, 0x12); /* OHCI0 Port 12~13 */
|
||||
|
||||
/* SATA */
|
||||
PCI_INT(sp5100_bus_number, 0x11, 0x0, 0x16); /* 6, INTG */
|
||||
|
||||
/* PCI slots */
|
||||
dev = pcidev_on_root(0x14, 4);
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
|
||||
/* PCI_SLOT 0. */
|
||||
PCI_INT(bus_pci, 0x1, 0x0, 0x15);
|
||||
PCI_INT(bus_pci, 0x1, 0x1, 0x16);
|
||||
PCI_INT(bus_pci, 0x1, 0x2, 0x17);
|
||||
PCI_INT(bus_pci, 0x1, 0x3, 0x14);
|
||||
|
||||
/* PCI_SLOT 1. */
|
||||
PCI_INT(bus_pci, 0x2, 0x0, 0x14);
|
||||
PCI_INT(bus_pci, 0x2, 0x1, 0x15);
|
||||
PCI_INT(bus_pci, 0x2, 0x2, 0x16);
|
||||
PCI_INT(bus_pci, 0x2, 0x3, 0x17);
|
||||
|
||||
/* PCI_SLOT 2. */
|
||||
PCI_INT(bus_pci, 0x3, 0x0, 0x16);
|
||||
PCI_INT(bus_pci, 0x3, 0x1, 0x17);
|
||||
PCI_INT(bus_pci, 0x3, 0x2, 0x14);
|
||||
PCI_INT(bus_pci, 0x3, 0x3, 0x15);
|
||||
}
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
@@ -1,553 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
*
|
||||
* Copyright (C) 2007 AMD
|
||||
* Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <commonlib/helpers.h>
|
||||
#include <northbridge/amd/amdfam10/amdfam10.h>
|
||||
|
||||
void setup_mb_resource_map(void)
|
||||
{
|
||||
static const unsigned int fam15h_register_values[] = {
|
||||
/* Careful set limit registers before base registers which contain the enables */
|
||||
/* DRAM Limit i Registers
|
||||
* F1:0x44 i = 0
|
||||
* F1:0x4C i = 1
|
||||
* F1:0x54 i = 2
|
||||
* F1:0x5C i = 3
|
||||
* F1:0x64 i = 4
|
||||
* F1:0x6C i = 5
|
||||
* F1:0x74 i = 6
|
||||
* F1:0x7C i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 3] Reserved
|
||||
* [10: 8] Interleave select
|
||||
* specifies the values of A[14:12] to use with interleave enable.
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Limit Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40 bit address
|
||||
* that define the end of the DRAM region.
|
||||
*/
|
||||
// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000,
|
||||
ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001,
|
||||
ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002,
|
||||
ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003,
|
||||
ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004,
|
||||
ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005,
|
||||
ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006,
|
||||
ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
|
||||
|
||||
/* DRAM Base i Registers
|
||||
* F1:0x40 i = 0
|
||||
* F1:0x48 i = 1
|
||||
* F1:0x50 i = 2
|
||||
* F1:0x58 i = 3
|
||||
* F1:0x60 i = 4
|
||||
* F1:0x68 i = 5
|
||||
* F1:0x70 i = 6
|
||||
* F1:0x78 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 7: 2] Reserved
|
||||
* [10: 8] Interleave Enable
|
||||
* 000 = No interleave
|
||||
* 001 = Interleave on A[12] (2 nodes)
|
||||
* 010 = reserved
|
||||
* 011 = Interleave on A[12] and A[14] (4 nodes)
|
||||
* 100 = reserved
|
||||
* 101 = reserved
|
||||
* 110 = reserved
|
||||
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Base Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40-bit address
|
||||
* that define the start of the DRAM region.
|
||||
*/
|
||||
// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
* F1:0x8C i = 1
|
||||
* F1:0x94 i = 2
|
||||
* F1:0x9C i = 3
|
||||
* F1:0xA4 i = 4
|
||||
* F1:0xAC i = 5
|
||||
* F1:0xB4 i = 6
|
||||
* F1:0xBC i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Link 3
|
||||
* [ 6: 6] Reserved
|
||||
* [ 7: 7] Non-Posted
|
||||
* 0 = CPU writes may be posted
|
||||
* 1 = CPU writes must be non-posted
|
||||
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
|
||||
* This field defines the upp address bits of a 40-bit address that
|
||||
* defines the end of a memory-mapped I/O region n
|
||||
*/
|
||||
ADDRMAP_REG(0x84), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x8C), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x94), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x9C), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xA4), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xAC), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xBC), 0x00000048, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Base i Registers
|
||||
* F1:0x80 i = 0
|
||||
* F1:0x88 i = 1
|
||||
* F1:0x90 i = 2
|
||||
* F1:0x98 i = 3
|
||||
* F1:0xA0 i = 4
|
||||
* F1:0xA8 i = 5
|
||||
* F1:0xB0 i = 6
|
||||
* F1:0xB8 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Cpu Disable
|
||||
* 0 = Cpu can use this I/O range
|
||||
* 1 = Cpu requests do not use this I/O range
|
||||
* [ 3: 3] Lock
|
||||
* 0 = base/limit registers i are read/write
|
||||
* 1 = base/limit registers i are read-only
|
||||
* [ 7: 4] Reserved
|
||||
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
|
||||
* This field defines the upper address bits of a 40bit address
|
||||
* that defines the start of memory-mapped I/O region i
|
||||
*/
|
||||
ADDRMAP_REG(0x80), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x88), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x90), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x98), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xB8), 0x000000f0, 0x00000000,
|
||||
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
* F1:0xCC i = 1
|
||||
* F1:0xD4 i = 2
|
||||
* F1:0xDC i = 3
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Link 3
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Limit Address i
|
||||
* This field defines the end of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> AMD SR5690 */
|
||||
ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000,
|
||||
ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000,
|
||||
ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
|
||||
|
||||
/* PCI I/O Base i Registers
|
||||
* F1:0xC0 i = 0
|
||||
* F1:0xC8 i = 1
|
||||
* F1:0xD0 i = 2
|
||||
* F1:0xD8 i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 3: 2] Reserved
|
||||
* [ 4: 4] VGA Enable
|
||||
* 0 = VGA matches Disabled
|
||||
* 1 = matches all address < 64K and where A[9:0] is in the
|
||||
* range 3B0-3BB or 3C0-3DF independent of the base & limit registers
|
||||
* [ 5: 5] ISA Enable
|
||||
* 0 = ISA matches Disabled
|
||||
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
|
||||
* from matching agains this base/limit pair
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Base i
|
||||
* This field defines the start of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001013,
|
||||
ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000,
|
||||
ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000,
|
||||
ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
|
||||
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
* F1:0xE8 i = 2
|
||||
* F1:0xEC i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Device Number Compare Enable
|
||||
* 0 = The ranges are based on bus number
|
||||
* 1 = The ranges are ranges of devices on bus 0
|
||||
* [ 3: 3] Reserved
|
||||
* [ 6: 4] Destination Node
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 7] Reserved
|
||||
* [ 9: 8] Destination Link
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 - Link 3
|
||||
* [15:10] Reserved
|
||||
* [23:16] Bus Number Base i
|
||||
* This field defines the lowest bus number in configuration region i
|
||||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration region i
|
||||
*/
|
||||
ADDRMAP_REG(0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> AMD SR5690 */
|
||||
ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000,
|
||||
ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000,
|
||||
ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
|
||||
|
||||
};
|
||||
|
||||
static const unsigned int fam10h_register_values[] = {
|
||||
/* Careful set limit registers before base registers which contain the enables */
|
||||
/* DRAM Limit i Registers
|
||||
* F1:0x44 i = 0
|
||||
* F1:0x4C i = 1
|
||||
* F1:0x54 i = 2
|
||||
* F1:0x5C i = 3
|
||||
* F1:0x64 i = 4
|
||||
* F1:0x6C i = 5
|
||||
* F1:0x74 i = 6
|
||||
* F1:0x7C i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 3] Reserved
|
||||
* [10: 8] Interleave select
|
||||
* specifies the values of A[14:12] to use with interleave enable.
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Limit Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40 bit address
|
||||
* that define the end of the DRAM region.
|
||||
*/
|
||||
// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000,
|
||||
ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001,
|
||||
ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002,
|
||||
ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003,
|
||||
ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004,
|
||||
ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005,
|
||||
ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006,
|
||||
ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
|
||||
|
||||
/* DRAM Base i Registers
|
||||
* F1:0x40 i = 0
|
||||
* F1:0x48 i = 1
|
||||
* F1:0x50 i = 2
|
||||
* F1:0x58 i = 3
|
||||
* F1:0x60 i = 4
|
||||
* F1:0x68 i = 5
|
||||
* F1:0x70 i = 6
|
||||
* F1:0x78 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 7: 2] Reserved
|
||||
* [10: 8] Interleave Enable
|
||||
* 000 = No interleave
|
||||
* 001 = Interleave on A[12] (2 nodes)
|
||||
* 010 = reserved
|
||||
* 011 = Interleave on A[12] and A[14] (4 nodes)
|
||||
* 100 = reserved
|
||||
* 101 = reserved
|
||||
* 110 = reserved
|
||||
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Base Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40-bit address
|
||||
* that define the start of the DRAM region.
|
||||
*/
|
||||
// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
* F1:0x8C i = 1
|
||||
* F1:0x94 i = 2
|
||||
* F1:0x9C i = 3
|
||||
* F1:0xA4 i = 4
|
||||
* F1:0xAC i = 5
|
||||
* F1:0xB4 i = 6
|
||||
* F1:0xBC i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Link 3
|
||||
* [ 6: 6] Reserved
|
||||
* [ 7: 7] Non-Posted
|
||||
* 0 = CPU writes may be posted
|
||||
* 1 = CPU writes must be non-posted
|
||||
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
|
||||
* This field defines the upp address bits of a 40-bit address that
|
||||
* defines the end of a memory-mapped I/O region n
|
||||
*/
|
||||
ADDRMAP_REG(0x84), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x8C), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x94), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x9C), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xA4), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xAC), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xBC), 0x00000048, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Base i Registers
|
||||
* F1:0x80 i = 0
|
||||
* F1:0x88 i = 1
|
||||
* F1:0x90 i = 2
|
||||
* F1:0x98 i = 3
|
||||
* F1:0xA0 i = 4
|
||||
* F1:0xA8 i = 5
|
||||
* F1:0xB0 i = 6
|
||||
* F1:0xB8 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Cpu Disable
|
||||
* 0 = Cpu can use this I/O range
|
||||
* 1 = Cpu requests do not use this I/O range
|
||||
* [ 3: 3] Lock
|
||||
* 0 = base/limit registers i are read/write
|
||||
* 1 = base/limit registers i are read-only
|
||||
* [ 7: 4] Reserved
|
||||
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
|
||||
* This field defines the upper address bits of a 40bit address
|
||||
* that defines the start of memory-mapped I/O region i
|
||||
*/
|
||||
ADDRMAP_REG(0x80), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x88), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x90), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x98), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xB8), 0x000000f0, 0x00000000,
|
||||
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
* F1:0xCC i = 1
|
||||
* F1:0xD4 i = 2
|
||||
* F1:0xDC i = 3
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Link 3
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Limit Address i
|
||||
* This field defines the end of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00fff110, /* link 3 of CPU 0 --> AMD SR5690 */
|
||||
ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000,
|
||||
ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000,
|
||||
ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
|
||||
|
||||
/* PCI I/O Base i Registers
|
||||
* F1:0xC0 i = 0
|
||||
* F1:0xC8 i = 1
|
||||
* F1:0xD0 i = 2
|
||||
* F1:0xD8 i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 3: 2] Reserved
|
||||
* [ 4: 4] VGA Enable
|
||||
* 0 = VGA matches Disabled
|
||||
* 1 = matches all address < 64K and where A[9:0] is in the
|
||||
* range 3B0-3BB or 3C0-3DF independent of the base & limit registers
|
||||
* [ 5: 5] ISA Enable
|
||||
* 0 = ISA matches Disabled
|
||||
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
|
||||
* from matching agains this base/limit pair
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Base i
|
||||
* This field defines the start of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001013,
|
||||
ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000,
|
||||
ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000,
|
||||
ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
|
||||
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
* F1:0xE8 i = 2
|
||||
* F1:0xEC i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Device Number Compare Enable
|
||||
* 0 = The ranges are based on bus number
|
||||
* 1 = The ranges are ranges of devices on bus 0
|
||||
* [ 3: 3] Reserved
|
||||
* [ 6: 4] Destination Node
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 7] Reserved
|
||||
* [ 9: 8] Destination Link
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 - Link 3
|
||||
* [15:10] Reserved
|
||||
* [23:16] Bus Number Base i
|
||||
* This field defines the lowest bus number in configuration region i
|
||||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration region i
|
||||
*/
|
||||
ADDRMAP_REG(0xE0), 0x0000FC88, 0x05000303, /* link 3 of CPU 0 --> AMD SR5690 */
|
||||
ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000,
|
||||
ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000,
|
||||
ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
|
||||
|
||||
};
|
||||
|
||||
int max;
|
||||
uint8_t fam15h = 0;
|
||||
uint32_t family;
|
||||
|
||||
family = cpuid_eax(0x80000001);
|
||||
family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
|
||||
|
||||
if (family >= 0x6f)
|
||||
/* Family 15h or later */
|
||||
fam15h = 1;
|
||||
|
||||
if (fam15h) {
|
||||
max = ARRAY_SIZE(fam15h_register_values);
|
||||
setup_resource_map(fam15h_register_values, max);
|
||||
} else {
|
||||
max = ARRAY_SIZE(fam10h_register_values);
|
||||
setup_resource_map(fam10h_register_values, max);
|
||||
}
|
||||
}
|
||||
@@ -1,720 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 - 2017 Raptor Engineering, LLC
|
||||
*
|
||||
* Copyright (C) 2007 AMD
|
||||
* Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/mmio.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <console/console.h>
|
||||
#include <romstage_handoff.h>
|
||||
#include <timestamp.h>
|
||||
#include <spd.h>
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
#include <delay.h>
|
||||
#include <superio/winbond/common/winbond.h>
|
||||
#include <superio/winbond/w83667hg-a/w83667hg-a.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include <cpu/amd/car.h>
|
||||
#include <cpu/amd/msr.h>
|
||||
#include <smp/spinlock.h>
|
||||
#include <southbridge/amd/common/reset.h>
|
||||
#include <southbridge/amd/sb700/sb700.h>
|
||||
#include <southbridge/amd/sb700/smbus.h>
|
||||
#include <southbridge/amd/sr5650/sr5650.h>
|
||||
#include <northbridge/amd/amdfam10/raminit.h>
|
||||
#include <northbridge/amd/amdht/ht_wrapper.h>
|
||||
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
|
||||
#include <arch/early_variables.h>
|
||||
#include <cbmem.h>
|
||||
#include <types.h>
|
||||
|
||||
#include "cpu/amd/quadcore/quadcore.c"
|
||||
|
||||
#define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
|
||||
#define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2)
|
||||
|
||||
int spd_read_byte(unsigned int device, unsigned int address);
|
||||
|
||||
int spd_read_byte(unsigned int device, unsigned int address)
|
||||
{
|
||||
return do_smbus_read_byte(SMBUS_AUX_IO_BASE, device, address);
|
||||
}
|
||||
|
||||
/*
|
||||
* ASUS KGPE-D16 specific SPD enable/disable magic.
|
||||
*
|
||||
* Setting SP5100 GPIOs 59 and 60 controls an SPI mux with four settings:
|
||||
* 0: Disabled
|
||||
* 1: Normal SPI access
|
||||
* 2: CPU0 SPD
|
||||
* 3: CPU1 SPD
|
||||
*
|
||||
* Disable SPD access after RAM init to allow access to standard SMBus/I2C offsets
|
||||
* which is required e.g. by lm-sensors.
|
||||
*/
|
||||
|
||||
/* Relevant GPIO register information is available in the
|
||||
* AMD SP5100 Register Reference Guide rev. 3.03, page 130
|
||||
*/
|
||||
static void switch_spd_mux(uint8_t channel)
|
||||
{
|
||||
uint8_t byte;
|
||||
|
||||
byte = pci_read_config8(PCI_DEV(0, 0x14, 0), 0x54);
|
||||
byte &= ~0xc; /* Clear SPD mux GPIOs */
|
||||
byte &= ~0xc0; /* Enable SPD mux GPIO output drivers */
|
||||
byte |= (channel << 2) & 0xc; /* Set SPD mux GPIOs */
|
||||
pci_write_config8(PCI_DEV(0, 0x14, 0), 0x54, byte);
|
||||
|
||||
/* Temporary AST PCI mapping */
|
||||
const uint32_t memory_base = 0xfc000000;
|
||||
const uint32_t memory_limit = 0xfc800000;
|
||||
|
||||
#define TEMP_PCI_BUS 0x2
|
||||
/* Save S100 PCI bridge settings */
|
||||
uint16_t prev_sec_cfg = pci_read_config16(PCI_DEV(0, 0x14, 4),
|
||||
PCI_COMMAND);
|
||||
uint8_t prev_sec_bus = pci_read_config8(PCI_DEV(0, 0x14, 4),
|
||||
PCI_SECONDARY_BUS);
|
||||
uint8_t prev_sec_sub_bus = pci_read_config8(PCI_DEV(0, 0x14, 4),
|
||||
PCI_SUBORDINATE_BUS);
|
||||
uint16_t prev_sec_mem_base = pci_read_config16(PCI_DEV(0, 0x14, 4),
|
||||
PCI_MEMORY_BASE);
|
||||
uint16_t prev_sec_mem_limit = pci_read_config16(PCI_DEV(0, 0x14, 4),
|
||||
PCI_MEMORY_LIMIT);
|
||||
/* Temporarily enable the SP5100 PCI bridge */
|
||||
pci_write_config8(PCI_DEV(0, 0x14, 4), PCI_SECONDARY_BUS, TEMP_PCI_BUS);
|
||||
pci_write_config8(PCI_DEV(0, 0x14, 4), PCI_SUBORDINATE_BUS, 0xff);
|
||||
pci_write_config16(PCI_DEV(0, 0x14, 4), PCI_MEMORY_BASE,
|
||||
(memory_base >> 20));
|
||||
pci_write_config16(PCI_DEV(0, 0x14, 4), PCI_MEMORY_LIMIT,
|
||||
(memory_limit >> 20));
|
||||
pci_write_config16(PCI_DEV(0, 0x14, 4), PCI_COMMAND,
|
||||
PCI_COMMAND_MEMORY);
|
||||
|
||||
/* Temporarily enable AST BAR1 */
|
||||
uint16_t prev_ast_cmd = pci_read_config16(PCI_DEV(TEMP_PCI_BUS, 0x1, 0),
|
||||
PCI_COMMAND);
|
||||
uint16_t prev_ast_sts = pci_read_config16(PCI_DEV(TEMP_PCI_BUS, 0x1, 0),
|
||||
PCI_STATUS);
|
||||
uint32_t prev_ast_bar1 = pci_read_config32(
|
||||
PCI_DEV(TEMP_PCI_BUS, 0x1, 0), PCI_BASE_ADDRESS_1);
|
||||
pci_write_config32(PCI_DEV(TEMP_PCI_BUS, 0x1, 0), PCI_BASE_ADDRESS_1,
|
||||
memory_base);
|
||||
pci_write_config16(PCI_DEV(TEMP_PCI_BUS, 0x1, 0), PCI_COMMAND,
|
||||
PCI_COMMAND_MEMORY);
|
||||
pci_write_config16(PCI_DEV(TEMP_PCI_BUS, 0x1, 0), PCI_STATUS,
|
||||
PCI_STATUS_CAP_LIST | PCI_STATUS_DEVSEL_MEDIUM);
|
||||
|
||||
/* Use the P2A bridge to set ASpeed SPD mux GPIOs to the same values as the SP5100 */
|
||||
void* ast_bar1 = (void*)memory_base;
|
||||
/* Enable access to GPIO controller */
|
||||
write32(ast_bar1 + 0xf004, 0x1e780000);
|
||||
write32(ast_bar1 + 0xf000, 0x1);
|
||||
/* Enable SPD mux GPIO output drivers */
|
||||
write32(ast_bar1 + 0x10024, read32(ast_bar1 + 0x10024) | 0x3000);
|
||||
/* Set SPD mux GPIOs */
|
||||
write32(ast_bar1 + 0x10020, (read32(ast_bar1 + 0x10020) & ~0x3000)
|
||||
| ((channel & 0x3) << 12));
|
||||
write32(ast_bar1 + 0xf000, 0x0);
|
||||
|
||||
/* Deconfigure AST BAR1 */
|
||||
pci_write_config16(PCI_DEV(TEMP_PCI_BUS, 0x1, 0), PCI_COMMAND,
|
||||
prev_ast_cmd);
|
||||
pci_write_config16(PCI_DEV(TEMP_PCI_BUS, 0x1, 0), PCI_STATUS,
|
||||
prev_ast_sts);
|
||||
pci_write_config32(PCI_DEV(TEMP_PCI_BUS, 0x1, 0), PCI_BASE_ADDRESS_1,
|
||||
prev_ast_bar1);
|
||||
|
||||
/* Deconfigure SP5100 PCI bridge */
|
||||
pci_write_config16(PCI_DEV(0, 0x14, 4), PCI_COMMAND, prev_sec_cfg);
|
||||
pci_write_config16(PCI_DEV(0, 0x14, 4), PCI_MEMORY_LIMIT,
|
||||
prev_sec_mem_limit);
|
||||
pci_write_config16(PCI_DEV(0, 0x14, 4), PCI_MEMORY_BASE,
|
||||
prev_sec_mem_base);
|
||||
pci_write_config8(PCI_DEV(0, 0x14, 4), PCI_SUBORDINATE_BUS,
|
||||
prev_sec_sub_bus);
|
||||
pci_write_config8(PCI_DEV(0, 0x14, 4), PCI_SECONDARY_BUS, prev_sec_bus);
|
||||
}
|
||||
|
||||
static const uint8_t spd_addr_fam15[] = {
|
||||
// Socket 0 Node 0 ("Node 0")
|
||||
RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
|
||||
// Socket 0 Node 1 ("Node 1")
|
||||
RC00, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0,
|
||||
// Socket 1 Node 0 ("Node 2")
|
||||
RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
|
||||
// Socket 1 Node 1 ("Node 3")
|
||||
RC01, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0,
|
||||
};
|
||||
|
||||
static const uint8_t spd_addr_fam10[] = {
|
||||
// Socket 0 Node 0 ("Node 0")
|
||||
RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
|
||||
// Socket 0 Node 1 ("Node 1")
|
||||
RC00, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0,
|
||||
// Socket 1 Node 1 ("Node 2")
|
||||
RC01, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0,
|
||||
// Socket 1 Node 0 ("Node 3")
|
||||
RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
|
||||
};
|
||||
|
||||
void activate_spd_rom(const struct mem_controller *ctrl)
|
||||
{
|
||||
struct sys_info *sysinfo = get_sysinfo();
|
||||
printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id);
|
||||
if (ctrl->node_id == 0) {
|
||||
printk(BIOS_DEBUG, "enable_spd_node0()\n");
|
||||
switch_spd_mux(0x2);
|
||||
} else if (ctrl->node_id == 1) {
|
||||
printk(BIOS_DEBUG, "enable_spd_node1()\n");
|
||||
switch_spd_mux((is_fam15h() || (sysinfo->nodes <= 2))?0x2:0x3);
|
||||
} else if (ctrl->node_id == 2) {
|
||||
printk(BIOS_DEBUG, "enable_spd_node2()\n");
|
||||
switch_spd_mux((is_fam15h() || (sysinfo->nodes <= 2))?0x3:0x2);
|
||||
} else if (ctrl->node_id == 3) {
|
||||
printk(BIOS_DEBUG, "enable_spd_node3()\n");
|
||||
switch_spd_mux(0x3);
|
||||
}
|
||||
}
|
||||
|
||||
/* Voltages are specified by index
|
||||
* Valid indices for this platform are:
|
||||
* 0: 1.5V
|
||||
* 1: 1.35V
|
||||
* 2: 1.25V
|
||||
* 3: 1.15V
|
||||
*/
|
||||
static void set_ddr3_voltage(uint8_t node, uint8_t index) {
|
||||
uint8_t byte;
|
||||
uint8_t value = 0;
|
||||
|
||||
if (index == 0)
|
||||
value = 0x0;
|
||||
else if (index == 1)
|
||||
value = 0x1;
|
||||
else if (index == 2)
|
||||
value = 0x4;
|
||||
else if (index == 3)
|
||||
value = 0x5;
|
||||
if (node == 1)
|
||||
value <<= 1;
|
||||
|
||||
/* Set GPIOs */
|
||||
byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0xd1);
|
||||
if (node == 0)
|
||||
byte &= ~0x5;
|
||||
if (node == 1)
|
||||
byte &= ~0xa;
|
||||
byte |= value;
|
||||
pci_write_config8(PCI_DEV(0, 0x14, 3), 0xd1, byte);
|
||||
|
||||
/* Enable GPIO output drivers */
|
||||
byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0xd0);
|
||||
byte &= 0x0f;
|
||||
pci_write_config8(PCI_DEV(0, 0x14, 3), 0xd0, byte);
|
||||
|
||||
printk(BIOS_DEBUG, "Node %02d DIMM voltage set to index %02x\n", node, index);
|
||||
}
|
||||
|
||||
void DIMMSetVoltages(struct MCTStatStruc *pMCTstat,
|
||||
struct DCTStatStruc *pDCTstatA) {
|
||||
/* This mainboard allows the DIMM voltage to be set per-socket.
|
||||
* Therefore, for each socket, iterate over all DIMMs to find the
|
||||
* lowest supported voltage common to all DIMMs on that socket.
|
||||
*/
|
||||
uint8_t nvram;
|
||||
uint8_t dimm;
|
||||
uint8_t node;
|
||||
uint8_t socket;
|
||||
uint8_t allowed_voltages = 0xf; /* The mainboard VRMs allow 1.15V, 1.25V, 1.35V, and 1.5V */
|
||||
uint8_t socket_allowed_voltages = allowed_voltages;
|
||||
uint32_t set_voltage = 0;
|
||||
|
||||
if (get_option(&nvram, "minimum_memory_voltage") == CB_SUCCESS) {
|
||||
switch (nvram) {
|
||||
case 2:
|
||||
allowed_voltages = 0x7; /* Allow 1.25V, 1.35V, and 1.5V */
|
||||
break;
|
||||
case 1:
|
||||
allowed_voltages = 0x3; /* Allow 1.35V and 1.5V */
|
||||
break;
|
||||
case 0:
|
||||
default:
|
||||
allowed_voltages = 0x1; /* Allow 1.5V only */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
|
||||
socket = node / 2;
|
||||
struct DCTStatStruc *pDCTstat;
|
||||
pDCTstat = pDCTstatA + node;
|
||||
|
||||
/* reset socket_allowed_voltages before processing each socket */
|
||||
if (!(node % 2))
|
||||
socket_allowed_voltages = allowed_voltages;
|
||||
|
||||
if (pDCTstat->NodePresent) {
|
||||
for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) {
|
||||
if (pDCTstat->DIMMValid & (1 << dimm)) {
|
||||
socket_allowed_voltages &= pDCTstat->DimmSupportedVoltages[dimm];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* set voltage per socket after processing last contained node */
|
||||
if (pDCTstat->NodePresent && (node % 2)) {
|
||||
/* Set voltages */
|
||||
if (socket_allowed_voltages & 0x8) {
|
||||
set_voltage = 0x8;
|
||||
set_ddr3_voltage(socket, 3);
|
||||
} else if (socket_allowed_voltages & 0x4) {
|
||||
set_voltage = 0x4;
|
||||
set_ddr3_voltage(socket, 2);
|
||||
} else if (socket_allowed_voltages & 0x2) {
|
||||
set_voltage = 0x2;
|
||||
set_ddr3_voltage(socket, 1);
|
||||
} else {
|
||||
set_voltage = 0x1;
|
||||
set_ddr3_voltage(socket, 0);
|
||||
}
|
||||
|
||||
/* Save final DIMM voltages for MCT and SMBIOS use */
|
||||
if (pDCTstat->NodePresent) {
|
||||
for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) {
|
||||
pDCTstat->DimmConfiguredVoltage[dimm] = set_voltage;
|
||||
}
|
||||
}
|
||||
pDCTstat = pDCTstatA + (node - 1);
|
||||
if (pDCTstat->NodePresent) {
|
||||
for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) {
|
||||
pDCTstat->DimmConfiguredVoltage[dimm] = set_voltage;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Allow the DDR supply voltages to settle */
|
||||
udelay(100000);
|
||||
}
|
||||
|
||||
static void set_peripheral_control_lines(void) {
|
||||
uint8_t byte;
|
||||
uint8_t nvram;
|
||||
uint8_t enable_ieee1394;
|
||||
|
||||
enable_ieee1394 = 1;
|
||||
|
||||
if (get_option(&nvram, "ieee1394_controller") == CB_SUCCESS)
|
||||
enable_ieee1394 = nvram & 0x1;
|
||||
|
||||
if (enable_ieee1394) {
|
||||
/* Enable PCICLK5 (onboard FireWire device) */
|
||||
outb(0x41, 0xcd6);
|
||||
outb(0x02, 0xcd7);
|
||||
} else {
|
||||
/* Disable PCICLK5 (onboard FireWire device) */
|
||||
outb(0x41, 0xcd6);
|
||||
outb(0x00, 0xcd7);
|
||||
}
|
||||
|
||||
/* Enable the RTC AltCentury register */
|
||||
outb(0x41, 0xcd6);
|
||||
byte = inb(0xcd7);
|
||||
byte |= 0x10;
|
||||
outb(byte, 0xcd7);
|
||||
}
|
||||
|
||||
#ifdef TEST_MEMORY
|
||||
static void execute_memory_test(void)
|
||||
{
|
||||
/* Test DRAM functionality */
|
||||
uint32_t i;
|
||||
uint32_t v;
|
||||
uint32_t w;
|
||||
uint32_t x;
|
||||
uint32_t y;
|
||||
uint32_t z;
|
||||
uint32_t *dataptr;
|
||||
uint32_t readback;
|
||||
uint32_t start = 0x300000;
|
||||
printk(BIOS_DEBUG, "Writing test pattern 1 to memory...\n");
|
||||
for (i = 0; i < 0x1000000; i = i + 8) {
|
||||
dataptr = (void *)(start + i);
|
||||
*dataptr = 0x55555555;
|
||||
dataptr = (void *)(start + i + 4);
|
||||
*dataptr = 0xaaaaaaaa;
|
||||
}
|
||||
printk(BIOS_DEBUG, "Done!\n");
|
||||
printk(BIOS_DEBUG, "Testing memory...\n");
|
||||
for (i = 0; i < 0x1000000; i = i + 8) {
|
||||
dataptr = (void *)(start + i);
|
||||
readback = *dataptr;
|
||||
if (readback != 0x55555555)
|
||||
printk(BIOS_DEBUG, "%p: INCORRECT VALUE %08x (should have been %08x)\n", dataptr, readback, 0x55555555);
|
||||
dataptr = (void *)(start + i + 4);
|
||||
readback = *dataptr;
|
||||
if (readback != 0xaaaaaaaa)
|
||||
printk(BIOS_DEBUG, "%p: INCORRECT VALUE %08x (should have been %08x)\n", dataptr, readback, 0xaaaaaaaa);
|
||||
}
|
||||
printk(BIOS_DEBUG, "Done!\n");
|
||||
printk(BIOS_DEBUG, "Writing test pattern 2 to memory...\n");
|
||||
/* Set up the PRNG seeds for initial write */
|
||||
w = 0x55555555;
|
||||
x = 0xaaaaaaaa;
|
||||
y = 0x12345678;
|
||||
z = 0x87654321;
|
||||
for (i = 0; i < 0x1000000; i = i + 4) {
|
||||
/* Use Xorshift as a PRNG to stress test the bus */
|
||||
v = x;
|
||||
v ^= v << 11;
|
||||
v ^= v >> 8;
|
||||
x = y;
|
||||
y = z;
|
||||
z = w;
|
||||
w ^= w >> 19;
|
||||
w ^= v;
|
||||
dataptr = (void *)(start + i);
|
||||
*dataptr = w;
|
||||
}
|
||||
printk(BIOS_DEBUG, "Done!\n");
|
||||
printk(BIOS_DEBUG, "Testing memory...\n");
|
||||
/* Reset the PRNG seeds for readback */
|
||||
w = 0x55555555;
|
||||
x = 0xaaaaaaaa;
|
||||
y = 0x12345678;
|
||||
z = 0x87654321;
|
||||
for (i = 0; i < 0x1000000; i = i + 4) {
|
||||
/* Use Xorshift as a PRNG to stress test the bus */
|
||||
v = x;
|
||||
v ^= v << 11;
|
||||
v ^= v >> 8;
|
||||
x = y;
|
||||
y = z;
|
||||
z = w;
|
||||
w ^= w >> 19;
|
||||
w ^= v;
|
||||
dataptr = (void *)(start + i);
|
||||
readback = *dataptr;
|
||||
if (readback != w)
|
||||
printk(BIOS_DEBUG, "%p: INCORRECT VALUE %08x (should have been %08x)\n", dataptr, readback, w);
|
||||
}
|
||||
printk(BIOS_DEBUG, "Done!\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
static spinlock_t printk_spinlock CAR_GLOBAL;
|
||||
|
||||
spinlock_t *romstage_console_lock(void)
|
||||
{
|
||||
return car_get_var_ptr(&printk_spinlock);
|
||||
}
|
||||
|
||||
void initialize_romstage_console_lock(void)
|
||||
{
|
||||
spin_unlock(romstage_console_lock());
|
||||
}
|
||||
|
||||
static spinlock_t nvram_cbfs_spinlock CAR_GLOBAL;
|
||||
|
||||
spinlock_t *romstage_nvram_cbfs_lock(void)
|
||||
{
|
||||
return car_get_var_ptr(&nvram_cbfs_spinlock);
|
||||
}
|
||||
|
||||
void initialize_romstage_nvram_cbfs_lock(void)
|
||||
{
|
||||
spin_unlock(romstage_nvram_cbfs_lock());
|
||||
}
|
||||
|
||||
static spinlock_t microcode_cbfs_spinlock CAR_GLOBAL;
|
||||
|
||||
spinlock_t *romstage_microcode_cbfs_lock(void)
|
||||
{
|
||||
return car_get_var_ptr(µcode_cbfs_spinlock);
|
||||
}
|
||||
|
||||
void initialize_romstage_microcode_cbfs_lock(void)
|
||||
{
|
||||
spin_unlock(romstage_microcode_cbfs_lock());
|
||||
}
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
uint32_t esp;
|
||||
__asm__ volatile (
|
||||
"movl %%esp, %0"
|
||||
: "=r" (esp)
|
||||
);
|
||||
|
||||
struct sys_info *sysinfo = get_sysinfo();
|
||||
|
||||
/* Limit the maximum HT speed to 2.6GHz to prevent lockups
|
||||
* due to HT CPU <--> CPU wiring not being validated to 3.2GHz
|
||||
*/
|
||||
sysinfo->ht_link_cfg.ht_speed_limit = 2600;
|
||||
|
||||
uint32_t bsp_apicid = 0, val;
|
||||
uint8_t byte;
|
||||
uint8_t power_on_reset = 0;
|
||||
msr_t msr;
|
||||
|
||||
int s3resume = acpi_is_wakeup_s3();
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
/* Initial timestamp */
|
||||
timestamp_init(timestamp_get());
|
||||
timestamp_add_now(TS_START_ROMSTAGE);
|
||||
|
||||
/* Initialize the printk, nvram CBFS, and microcode CBFS spinlocks */
|
||||
initialize_romstage_console_lock();
|
||||
initialize_romstage_nvram_cbfs_lock();
|
||||
initialize_romstage_microcode_cbfs_lock();
|
||||
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
set_bsp_node_CHtExtNodeCfgEn();
|
||||
enumerate_ht_chain();
|
||||
|
||||
/* SR56x0 pcie bridges block pci_locate_device() before pcie training.
|
||||
* disable all pcie bridges on SR56x0 to work around it
|
||||
*/
|
||||
sr5650_disable_pcie_bridge();
|
||||
|
||||
/* Initialize southbridge */
|
||||
sb7xx_51xx_pci_port80();
|
||||
|
||||
/* Configure secondary serial port pin mux */
|
||||
winbond_set_pinmux(SERIAL_1_DEV, 0x2a, W83667HG_SPI_PINMUX_GPIO4_SERIAL_B_MASK, W83667HG_SPI_PINMUX_SERIAL_B);
|
||||
|
||||
/* Initialize early serial */
|
||||
winbond_enable_serial(SERIAL_0_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
|
||||
/* Disable LPC legacy DMA support to prevent lockup */
|
||||
byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0x78);
|
||||
byte &= ~(1 << 0);
|
||||
pci_write_config8(PCI_DEV(0, 0x14, 3), 0x78, byte);
|
||||
}
|
||||
|
||||
printk(BIOS_SPEW, "Initial stack pointer: %08x\n", esp);
|
||||
|
||||
post_code(0x30);
|
||||
|
||||
if (bist == 0)
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
|
||||
|
||||
post_code(0x32);
|
||||
|
||||
enable_sr5650_dev8();
|
||||
sb7xx_51xx_lpc_init();
|
||||
|
||||
if (CONFIG_MAX_PHYSICAL_CPUS != 4)
|
||||
printk(BIOS_WARNING, "CONFIG_MAX_PHYSICAL_CPUS is %d, but this is a dual socket AMD G34 board!\n", CONFIG_MAX_PHYSICAL_CPUS);
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
val = cpuid_eax(1);
|
||||
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
|
||||
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
|
||||
printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
|
||||
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
|
||||
|
||||
/* Setup sysinfo defaults */
|
||||
set_sysinfo_in_ram(0);
|
||||
|
||||
if (!sb7xx_51xx_decode_last_reset())
|
||||
power_on_reset = 1;
|
||||
|
||||
initialize_mca(1, power_on_reset);
|
||||
update_microcode(val);
|
||||
|
||||
post_code(0x33);
|
||||
|
||||
cpuSetAMDMSR(0);
|
||||
post_code(0x34);
|
||||
|
||||
amd_ht_init(sysinfo);
|
||||
amd_ht_fixup(sysinfo);
|
||||
post_code(0x35);
|
||||
|
||||
/* Setup nodes PCI space and start core 0 AP init. */
|
||||
finalize_node_setup(sysinfo);
|
||||
|
||||
/* Setup any mainboard PCI settings etc. */
|
||||
setup_mb_resource_map();
|
||||
initialize_mca(0, power_on_reset);
|
||||
post_code(0x36);
|
||||
|
||||
/* Wait for all the APs core0 started by finalize_node_setup. */
|
||||
wait_all_core0_started();
|
||||
|
||||
/* run _early_setup before soft-reset. */
|
||||
sr5650_early_setup();
|
||||
sb7xx_51xx_early_setup();
|
||||
|
||||
if (CONFIG(LOGICAL_CPUS)) {
|
||||
/* Core0 on each node is configured. Now setup any additional cores. */
|
||||
printk(BIOS_DEBUG, "start_other_cores()\n");
|
||||
start_other_cores(bsp_apicid);
|
||||
post_code(0x37);
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
}
|
||||
|
||||
if (CONFIG(SET_FIDVID)) {
|
||||
msr = rdmsr(MSR_COFVID_STS);
|
||||
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
|
||||
|
||||
/* FIXME: The sb fid change may survive the warm reset and only need to be done once */
|
||||
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
|
||||
|
||||
post_code(0x39);
|
||||
|
||||
#if CONFIG(SET_FIDVID)
|
||||
if (!warm_reset_detect(0)) { // BSP is node 0
|
||||
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
|
||||
} else {
|
||||
init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
|
||||
}
|
||||
#endif
|
||||
|
||||
post_code(0x3A);
|
||||
|
||||
/* show final fid and vid */
|
||||
msr = rdmsr(MSR_COFVID_STS);
|
||||
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
post_code(0x38);
|
||||
|
||||
init_timer(); // Need to use TMICT to synconize FID/VID
|
||||
|
||||
sr5650_htinit();
|
||||
|
||||
/* Reset for HT, FIDVID, PLL and errata changes to take effect. */
|
||||
if (!warm_reset_detect(0)) {
|
||||
printk(BIOS_INFO, "...WARM RESET...\n\n\n");
|
||||
soft_reset();
|
||||
die("After soft_reset - shouldn't see this message!!!\n");
|
||||
}
|
||||
|
||||
sr5650_htinit_dect_and_enable_isochronous_link();
|
||||
|
||||
/* Set default DDR memory voltage
|
||||
* This will be overridden later during RAM initialization
|
||||
*/
|
||||
set_lpc_sticky_ctl(1); /* Retain LPC/IMC GPIO configuration during S3 sleep */
|
||||
if (!s3resume) { /* Avoid supply voltage glitches while the DIMMs are retaining data */
|
||||
set_ddr3_voltage(0, 0); /* Node 0 */
|
||||
set_ddr3_voltage(1, 0); /* Node 1 */
|
||||
}
|
||||
|
||||
/* Set up peripheral control lines */
|
||||
set_peripheral_control_lines();
|
||||
|
||||
post_code(0x3B);
|
||||
|
||||
/* Wait for all APs to be stopped, otherwise RAM initialization may hang */
|
||||
if (CONFIG(LOGICAL_CPUS))
|
||||
wait_all_other_cores_stopped(bsp_apicid);
|
||||
|
||||
/* It's the time to set ctrl in sysinfo now; */
|
||||
printk(BIOS_DEBUG, "fill_mem_ctrl() detected %d nodes\n", sysinfo->nodes);
|
||||
if (is_fam15h())
|
||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr_fam15);
|
||||
else
|
||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr_fam10);
|
||||
post_code(0x3D);
|
||||
|
||||
#if 0
|
||||
/* FIXME
|
||||
* After the AMD K10 code has been converted to use
|
||||
* CONFIG(DEBUG_SMBUS) uncomment this block
|
||||
*/
|
||||
if (CONFIG(DEBUG_SMBUS)) {
|
||||
dump_spd_registers(&cpu[0]);
|
||||
dump_smbus_registers();
|
||||
}
|
||||
#endif
|
||||
|
||||
post_code(0x40);
|
||||
|
||||
raminit_amdmct(sysinfo);
|
||||
|
||||
#ifdef TEST_MEMORY
|
||||
execute_memory_test();
|
||||
#endif
|
||||
|
||||
if (s3resume)
|
||||
cbmem_initialize();
|
||||
else
|
||||
cbmem_initialize_empty();
|
||||
|
||||
romstage_handoff_init(s3resume);
|
||||
|
||||
post_code(0x41);
|
||||
|
||||
amdmct_cbmem_store_info(sysinfo);
|
||||
|
||||
printk(BIOS_DEBUG, "disable_spd()\n");
|
||||
switch_spd_mux(0x1);
|
||||
|
||||
sr5650_before_pci_init();
|
||||
sb7xx_51xx_before_pci_init();
|
||||
|
||||
/* Configure SP5100 GPIOs to match vendor settings */
|
||||
pci_write_config16(PCI_DEV(0, 0x14, 0), 0x50, 0x0170);
|
||||
pci_write_config16(PCI_DEV(0, 0x14, 0), 0x54, 0x0707);
|
||||
pci_write_config16(PCI_DEV(0, 0x14, 0), 0x56, 0x0bb0);
|
||||
pci_write_config16(PCI_DEV(0, 0x14, 0), 0x5a, 0x0ff0);
|
||||
}
|
||||
|
||||
/**
|
||||
* BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
|
||||
* Description:
|
||||
* This routine is called every time a non-coherent chain is processed.
|
||||
* BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
|
||||
* swap list. The first part of the list controls the BUID assignment and the
|
||||
* second part of the list provides the device to device linking. Device orientation
|
||||
* can be detected automatically, or explicitly. See documentation for more details.
|
||||
*
|
||||
* Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
|
||||
* based on each device's unit count.
|
||||
*
|
||||
* Parameters:
|
||||
* @param[in] node = The node on which this chain is located
|
||||
* @param[in] link = The link on the host for this chain
|
||||
* @param[out] List = supply a pointer to a list
|
||||
*/
|
||||
BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
|
||||
{
|
||||
/* Force BUID to 0 */
|
||||
static const u8 swaplist[] = {0, 0, 0xFF, 0, 0xFF};
|
||||
if ((is_fam15h() && (node == 0) && (link == 1)) /* Family 15h BSP SB link */
|
||||
|| (!is_fam15h() && (node == 0) && (link == 3))) { /* Family 10h BSP SB link */
|
||||
*List = swaplist;
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -1,46 +0,0 @@
|
||||
====================================================================================================
|
||||
SPD mux
|
||||
====================================================================================================
|
||||
SP5100
|
||||
GPIO 60 GPIO 59
|
||||
Disabled 0 0
|
||||
Normal operation 0 1
|
||||
CPU 0 SPD 1 0
|
||||
CPU 1 SPD 1 1
|
||||
|
||||
====================================================================================================
|
||||
W83795
|
||||
====================================================================================================
|
||||
|
||||
Sensor mappings:
|
||||
CPU_FAN1: FAN1
|
||||
CPU_FAN2: FAN2
|
||||
FRNT_FAN1: FAN3
|
||||
FRNT_FAN2: FAN4
|
||||
FRNT_FAN3: FAN5
|
||||
FRNT_FAN4: FAN6
|
||||
FRNT_FAN5: FAN7
|
||||
REAR_FAN1: FAN8
|
||||
|
||||
====================================================================================================
|
||||
Other hardware
|
||||
====================================================================================================
|
||||
|
||||
RECOVERY1 middle pin is connected to southbridge (AMD SP5100) GPIO 61
|
||||
Normal is HIGH, recovery is LOW.
|
||||
|
||||
+12VSB is generated using a charge pump attached to pin 7 of PU24 (APW7145).
|
||||
|
||||
The +12VSB standby voltage to each bank of DIMMs is switched by a bank of small FETs located close to each RAM power regulator control chip.
|
||||
The +12V primary voltage (lower left pin of the FET placed on the upper left of the control chip of the second node) is also connected to the 232GE located near the PCI slot.
|
||||
|
||||
The control line running to the gates of the +12VSB control FETs is connected to the +5VSB power for the USB ports.
|
||||
That line in turn is connected to +5VSB via the lone P06P03G PMOS transistor on the reverse side of the board, near the center on the lower half.
|
||||
The gate of that transistor is connected via a resistor to the source of the P06P03G PMOS transistor located adjacent to the unpopulated SMA clock header.
|
||||
The gate of that transistor is connected directly to the drain of the small FET directly below it.
|
||||
After that, there's a cascade of small FETs and resistors in that region, eventually leading to SuperIO pin 81.
|
||||
|
||||
SuperIO pin 81 (VSBGATE#) enables the standby voltage rails when set LOW.
|
||||
VSBGATE# is reset on every assertion of PWRGOOD.
|
||||
|
||||
Setting SuperIO LDN 9 CRF4 bits 1 or 0 (or both) to 0 disables NICB.
|
||||
@@ -1,53 +0,0 @@
|
||||
if BOARD_ASUS_M4A78_EM
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS
|
||||
def_bool y
|
||||
select CPU_AMD_SOCKET_AM3
|
||||
select DIMM_DDR2
|
||||
select NORTHBRIDGE_AMD_AMDFAM10
|
||||
select SOUTHBRIDGE_AMD_RS780
|
||||
select SOUTHBRIDGE_AMD_SB700
|
||||
select SUPERIO_ITE_IT8712F
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
select LIFT_BSP_APIC_ID
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_1024
|
||||
select ENABLE_APIC_EXT_ID
|
||||
select GFXUMA
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default asus/m4a78-em
|
||||
|
||||
config APIC_ID_OFFSET
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "M4A78-EM"
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 8
|
||||
|
||||
config MAX_PHYSICAL_CPUS
|
||||
int
|
||||
default 2
|
||||
|
||||
config HT_CHAIN_END_UNITID_BASE
|
||||
hex
|
||||
default 0x1
|
||||
|
||||
config HT_CHAIN_UNITID_BASE
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 18
|
||||
|
||||
endif
|
||||
@@ -1,2 +0,0 @@
|
||||
config BOARD_ASUS_M4A78_EM
|
||||
bool "M4A78-EM"
|
||||
@@ -1,16 +0,0 @@
|
||||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
|
||||
romstage-y += resourcemap.c
|
||||
|
||||
ramstage-y += get_bus_conf.c
|
||||
@@ -1,80 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* This file defines the processor and performance state capability
|
||||
* for each core in the system. It is included into the DSDT for each
|
||||
* core. It assumes that each core of the system has the same performance
|
||||
* characteristics.
|
||||
*/
|
||||
/*
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001)
|
||||
{
|
||||
Scope (\_PR) {
|
||||
Device (CPU0) {
|
||||
Name (_HID, "ACPI0007")
|
||||
Name (_UID, 0)
|
||||
#include "cpstate.asl"
|
||||
}
|
||||
Device (CPU1) {
|
||||
Name (_HID, "ACPI0007")
|
||||
Name (_UID, 1)
|
||||
#include "cpstate.asl"
|
||||
}
|
||||
Device (CPU2) {
|
||||
Name (_HID, "ACPI0007")
|
||||
Name (_UID, 2)
|
||||
#include "cpstate.asl"
|
||||
}
|
||||
Device (CPU3) {
|
||||
Name (_HID, "ACPI0007")
|
||||
Name (_UID, 3)
|
||||
#include "cpstate.asl"
|
||||
}
|
||||
}
|
||||
*/
|
||||
/* P-state support: The maximum number of P-states supported by the */
|
||||
/* CPUs we'll use is 6. */
|
||||
/* Get from AMI BIOS. */
|
||||
Name(_PSS, Package(){
|
||||
Package ()
|
||||
{
|
||||
0x00000AF0,
|
||||
0x0000BF81,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000000,
|
||||
0x00000000
|
||||
},
|
||||
|
||||
Package ()
|
||||
{
|
||||
0x00000578,
|
||||
0x000076F2,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000001,
|
||||
0x00000001
|
||||
}
|
||||
})
|
||||
|
||||
Name(_PCT, Package(){
|
||||
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
|
||||
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
|
||||
})
|
||||
|
||||
Method(_PPC, 0){
|
||||
Return(0)
|
||||
}
|
||||
@@ -1,240 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
Scope (_SB) {
|
||||
Device(PCI0) {
|
||||
Device(IDEC) {
|
||||
Name(_ADR, 0x00140001)
|
||||
#include "ide.asl"
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
/* Some timing tables */
|
||||
Name(UDTT, Package(){ /* Udma timing table */
|
||||
120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
|
||||
})
|
||||
|
||||
Name(MDTT, Package(){ /* MWDma timing table */
|
||||
480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
|
||||
})
|
||||
|
||||
Name(POTT, Package(){ /* Pio timing table */
|
||||
600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
|
||||
})
|
||||
|
||||
/* Some timing register value tables */
|
||||
Name(MDRT, Package(){ /* MWDma timing register table */
|
||||
0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
|
||||
})
|
||||
|
||||
Name(PORT, Package(){
|
||||
0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
|
||||
})
|
||||
|
||||
OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
|
||||
Field(ICRG, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
PPTS, 8, /* Primary PIO Slave Timing */
|
||||
PPTM, 8, /* Primary PIO Master Timing */
|
||||
OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
|
||||
PMTM, 8, /* Primary MWDMA Master Timing */
|
||||
OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
|
||||
OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
|
||||
PPSM, 4, /* Primary PIO slave Mode */
|
||||
OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
|
||||
OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
|
||||
PDSM, 4, /* Primary UltraDMA Mode */
|
||||
}
|
||||
|
||||
Method(GTTM, 1) /* get total time*/
|
||||
{
|
||||
Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
|
||||
Increment(Local0)
|
||||
Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
|
||||
Increment(Local1)
|
||||
Return(Multiply(30, Add(Local0, Local1)))
|
||||
}
|
||||
|
||||
Device(PRID)
|
||||
{
|
||||
Name (_ADR, Zero)
|
||||
Method(_GTM, 0)
|
||||
{
|
||||
NAME(OTBF, Buffer(20) { /* out buffer */
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
|
||||
CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
|
||||
CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
|
||||
CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
|
||||
CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
|
||||
|
||||
/* Just return if the channel is disabled */
|
||||
If(And(PPCR, 0x01)) { /* primary PIO control */
|
||||
Return(OTBF)
|
||||
}
|
||||
|
||||
/* Always tell them independent timing available and IOChannelReady used on both drives */
|
||||
Or(BFFG, 0x1A, BFFG)
|
||||
|
||||
Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
|
||||
Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
|
||||
|
||||
If(And(PDCR, 0x01)) { /* It's under UDMA mode */
|
||||
Or(BFFG, 0x01, BFFG)
|
||||
Store(DerefOf(Index(UDTT, PDMM)), DSD0)
|
||||
}
|
||||
Else {
|
||||
Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
|
||||
}
|
||||
|
||||
If(And(PDCR, 0x02)) { /* It's under UDMA mode */
|
||||
Or(BFFG, 0x04, BFFG)
|
||||
Store(DerefOf(Index(UDTT, PDSM)), DSD1)
|
||||
}
|
||||
Else {
|
||||
Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
|
||||
}
|
||||
|
||||
Return(OTBF) /* out buffer */
|
||||
} /* End Method(_GTM) */
|
||||
|
||||
Method(_STM, 3, NotSerialized)
|
||||
{
|
||||
NAME(INBF, Buffer(20) { /* in buffer */
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
|
||||
CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
|
||||
CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
|
||||
CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
|
||||
CreateDwordField(INBF, 16, BFFG) /*buffer flag */
|
||||
|
||||
Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
|
||||
Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
|
||||
Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
|
||||
|
||||
Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
|
||||
Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
|
||||
|
||||
If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
|
||||
Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 7, PDMM,)
|
||||
Or(PDCR, 0x01, PDCR)
|
||||
}
|
||||
Else {
|
||||
If(LNotEqual(DSD0, 0xFFFFFFFF)) {
|
||||
Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
|
||||
Store(DerefOf(Index(MDRT, Local0)), PMTM)
|
||||
}
|
||||
}
|
||||
|
||||
If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
|
||||
Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 7, PDSM,)
|
||||
Or(PDCR, 0x02, PDCR)
|
||||
}
|
||||
Else {
|
||||
If(LNotEqual(DSD1, 0xFFFFFFFF)) {
|
||||
Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
|
||||
Store(DerefOf(Index(MDRT, Local0)), PMTS)
|
||||
}
|
||||
}
|
||||
/* Return(INBF) */
|
||||
} /*End Method(_STM) */
|
||||
Device(MST)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_GTF) {
|
||||
Name(CMBF, Buffer(21) {
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
|
||||
})
|
||||
CreateByteField(CMBF, 1, POMD)
|
||||
CreateByteField(CMBF, 8, DMMD)
|
||||
CreateByteField(CMBF, 5, CMDA)
|
||||
CreateByteField(CMBF, 12, CMDB)
|
||||
CreateByteField(CMBF, 19, CMDC)
|
||||
|
||||
Store(0xA0, CMDA)
|
||||
Store(0xA0, CMDB)
|
||||
Store(0xA0, CMDC)
|
||||
|
||||
Or(PPMM, 0x08, POMD)
|
||||
|
||||
If(And(PDCR, 0x01)) {
|
||||
Or(PDMM, 0x40, DMMD)
|
||||
}
|
||||
Else {
|
||||
Store(Match
|
||||
(MDTT, MLE, GTTM(PMTM),
|
||||
MTR, 0, 0), Local0)
|
||||
If(LLess(Local0, 3)) {
|
||||
Or(0x20, Local0, DMMD)
|
||||
}
|
||||
}
|
||||
Return(CMBF)
|
||||
}
|
||||
} /* End Device(MST) */
|
||||
|
||||
Device(SLAV)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_GTF) {
|
||||
Name(CMBF, Buffer(21) {
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
|
||||
})
|
||||
CreateByteField(CMBF, 1, POMD)
|
||||
CreateByteField(CMBF, 8, DMMD)
|
||||
CreateByteField(CMBF, 5, CMDA)
|
||||
CreateByteField(CMBF, 12, CMDB)
|
||||
CreateByteField(CMBF, 19, CMDC)
|
||||
|
||||
Store(0xB0, CMDA)
|
||||
Store(0xB0, CMDB)
|
||||
Store(0xB0, CMDC)
|
||||
|
||||
Or(PPSM, 0x08, POMD)
|
||||
|
||||
If(And(PDCR, 0x02)) {
|
||||
Or(PDSM, 0x40, DMMD)
|
||||
}
|
||||
Else {
|
||||
Store(Match
|
||||
(MDTT, MLE, GTTM(PMTS),
|
||||
MTR, 0, 0), Local0)
|
||||
If(LLess(Local0, 3)) {
|
||||
Or(0x20, Local0, DMMD)
|
||||
}
|
||||
}
|
||||
Return(CMBF)
|
||||
}
|
||||
} /* End Device(SLAV) */
|
||||
}
|
||||
@@ -1,297 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
|
||||
)
|
||||
{
|
||||
#include "routing.asl"
|
||||
}
|
||||
*/
|
||||
|
||||
/* Routing is in System Bus scope */
|
||||
Scope(\_SB) {
|
||||
Name(PR0, Package(){
|
||||
/* NB devices */
|
||||
/* Bus 0, Dev 0 - RS780 Host Controller */
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
|
||||
Package(){0x0002FFFF, 0, INTC, 0 },
|
||||
Package(){0x0002FFFF, 1, INTD, 0 },
|
||||
Package(){0x0002FFFF, 2, INTA, 0 },
|
||||
Package(){0x0002FFFF, 3, INTB, 0 },
|
||||
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
|
||||
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||
Package(){0x0004FFFF, 0, INTA, 0 },
|
||||
Package(){0x0004FFFF, 1, INTB, 0 },
|
||||
Package(){0x0004FFFF, 2, INTC, 0 },
|
||||
Package(){0x0004FFFF, 3, INTD, 0 },
|
||||
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||
/* Package(){0x0005FFFF, 0, INTB, 0 }, */
|
||||
/* Package(){0x0005FFFF, 1, INTC, 0 }, */
|
||||
/* Package(){0x0005FFFF, 2, INTD, 0 }, */
|
||||
/* Package(){0x0005FFFF, 3, INTA, 0 }, */
|
||||
/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
|
||||
Package(){0x0006FFFF, 0, INTC, 0 },
|
||||
Package(){0x0006FFFF, 1, INTD, 0 },
|
||||
Package(){0x0006FFFF, 2, INTA, 0 },
|
||||
Package(){0x0006FFFF, 3, INTB, 0 },
|
||||
/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
|
||||
Package(){0x0007FFFF, 0, INTD, 0 },
|
||||
Package(){0x0007FFFF, 1, INTA, 0 },
|
||||
Package(){0x0007FFFF, 2, INTB, 0 },
|
||||
Package(){0x0007FFFF, 3, INTC, 0 },
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
/* SB devices */
|
||||
/* Bus 0, Dev 17 - SATA controller #2 */
|
||||
/* Bus 0, Dev 18 - SATA controller #1 */
|
||||
Package(){0x0011FFFF, 1, INTA, 0 },
|
||||
|
||||
/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
|
||||
Package(){0x0012FFFF, 0, INTA, 0 },
|
||||
Package(){0x0012FFFF, 1, INTB, 0 },
|
||||
Package(){0x0013FFFF, 0, INTA, 0 },
|
||||
Package(){0x0013FFFF, 1, INTB, 0 },
|
||||
Package(){0x0014FFFF, 2, INTA, 0 },
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */
|
||||
Package(){0x0014FFFF, 0, INTA, 0 },
|
||||
Package(){0x0014FFFF, 1, INTB, 0 },
|
||||
Package(){0x0014FFFF, 2, INTC, 0 },
|
||||
Package(){0x0014FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APR0, Package(){
|
||||
/* NB devices in APIC mode */
|
||||
/* Bus 0, Dev 0 - RS780 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
/* Package(){0x0001FFFF, 0, 0, 18 }, */
|
||||
/* Package(){0x0001FFFF, 1, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
|
||||
Package(){0x0002FFFF, 0, 0, 18 },
|
||||
/* Package(){0x0002FFFF, 1, 0, 19 }, */
|
||||
/* Package(){0x0002FFFF, 2, 0, 16 }, */
|
||||
/* Package(){0x0002FFFF, 3, 0, 17 }, */
|
||||
|
||||
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
|
||||
Package(){0x0003FFFF, 0, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||
Package(){0x0004FFFF, 0, 0, 16 },
|
||||
/* Package(){0x0004FFFF, 1, 0, 17 }, */
|
||||
/* Package(){0x0004FFFF, 2, 0, 18 }, */
|
||||
/* Package(){0x0004FFFF, 3, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||
/* Package(){0x0005FFFF, 0, 0, 17 }, */
|
||||
/* Package(){0x0005FFFF, 1, 0, 18 }, */
|
||||
/* Package(){0x0005FFFF, 2, 0, 19 }, */
|
||||
/* Package(){0x0005FFFF, 3, 0, 16 }, */
|
||||
|
||||
/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
|
||||
/* Package(){0x0006FFFF, 0, 0, 18 }, */
|
||||
/* Package(){0x0006FFFF, 1, 0, 19 }, */
|
||||
/* Package(){0x0006FFFF, 2, 0, 16 }, */
|
||||
/* Package(){0x0006FFFF, 3, 0, 17 }, */
|
||||
|
||||
/* Bus 0, Dev 7 - PCIe Bridge for network card */
|
||||
/* Package(){0x0007FFFF, 0, 0, 19 }, */
|
||||
/* Package(){0x0007FFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x0007FFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x0007FFFF, 3, 0, 18 }, */
|
||||
|
||||
/* Bus 0, Dev 9 - PCIe Bridge for network card */
|
||||
Package(){0x0009FFFF, 0, 0, 17 },
|
||||
/* Package(){0x0009FFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x0009FFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x0009FFFF, 3, 0, 18 }, */
|
||||
/* Bus 0, Dev A - PCIe Bridge for network card */
|
||||
Package(){0x000AFFFF, 0, 0, 18 },
|
||||
/* Package(){0x000AFFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x000AFFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x000AFFFF, 3, 0, 18 }, */
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
/* SB devices in APIC mode */
|
||||
/* Bus 0, Dev 17 - SATA controller #2 */
|
||||
/* Bus 0, Dev 18 - SATA controller #1 */
|
||||
Package(){0x0011FFFF, 0, 0, 22 },
|
||||
|
||||
/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
|
||||
Package(){0x0012FFFF, 0, 0, 16 },
|
||||
Package(){0x0012FFFF, 1, 0, 17 },
|
||||
Package(){0x0013FFFF, 0, 0, 18 },
|
||||
Package(){0x0013FFFF, 1, 0, 19 },
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
/* Package(){0x00130004, 2, 0, 18 }, */
|
||||
/* Package(){0x00130005, 3, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
Package(){0x0014FFFF, 1, 0, 17 },
|
||||
Package(){0x0014FFFF, 2, 0, 18 },
|
||||
Package(){0x0014FFFF, 3, 0, 19 },
|
||||
/* Package(){0x00140004, 2, 0, 18 }, */
|
||||
/* Package(){0x00140004, 3, 0, 19 }, */
|
||||
/* Package(){0x00140005, 1, 0, 17 }, */
|
||||
/* Package(){0x00140006, 1, 0, 17 }, */
|
||||
})
|
||||
|
||||
Name(PR1, Package(){
|
||||
/* Internal graphics - RS780 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, INTA, 0 },
|
||||
Package(){0x0005FFFF, 1, INTB, 0 },
|
||||
Package(){0x0005FFFF, 2, INTC, 0 },
|
||||
Package(){0x0005FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APR1, Package(){
|
||||
/* Internal graphics - RS780 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, 0, 18 },
|
||||
Package(){0x0005FFFF, 1, 0, 19 },
|
||||
/* Package(){0x0005FFFF, 2, 0, 20 }, */
|
||||
/* Package(){0x0005FFFF, 3, 0, 17 }, */
|
||||
})
|
||||
|
||||
Name(PS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
|
||||
Name(APS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, 0, 16 },
|
||||
Package(){0x0000FFFF, 1, 0, 17 },
|
||||
Package(){0x0000FFFF, 2, 0, 18 },
|
||||
Package(){0x0000FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PS5, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 5 */
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
|
||||
Name(APS5, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 5 */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
|
||||
Name(PS6, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 6 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
|
||||
Name(APS6, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 6 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS7, Package(){
|
||||
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
|
||||
Name(APS7, Package(){
|
||||
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
|
||||
Package(){0x0000FFFF, 0, 0, 19 },
|
||||
Package(){0x0000FFFF, 1, 0, 16 },
|
||||
Package(){0x0000FFFF, 2, 0, 17 },
|
||||
Package(){0x0000FFFF, 3, 0, 18 },
|
||||
})
|
||||
Name(PS9, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 9 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
|
||||
Name(APS9, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 9 */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
Name(PSa, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
|
||||
Name(APSa, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PCIB, Package(){
|
||||
/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
|
||||
Package(){0x0005FFFF, 0, 0, 0x14 },
|
||||
Package(){0x0005FFFF, 1, 0, 0x15 },
|
||||
Package(){0x0005FFFF, 2, 0, 0x16 },
|
||||
Package(){0x0005FFFF, 3, 0, 0x17 },
|
||||
Package(){0x0006FFFF, 0, 0, 0x15 },
|
||||
Package(){0x0006FFFF, 1, 0, 0x16 },
|
||||
Package(){0x0006FFFF, 2, 0, 0x17 },
|
||||
Package(){0x0006FFFF, 3, 0, 0x14 },
|
||||
Package(){0x0007FFFF, 0, 0, 0x16 },
|
||||
Package(){0x0007FFFF, 1, 0, 0x17 },
|
||||
Package(){0x0007FFFF, 2, 0, 0x14 },
|
||||
Package(){0x0007FFFF, 3, 0, 0x15 },
|
||||
})
|
||||
}
|
||||
@@ -1,145 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
|
||||
/*
|
||||
Scope (_SB) {
|
||||
Device(PCI0) {
|
||||
Device(SATA) {
|
||||
Name(_ADR, 0x00110000)
|
||||
#include "sata.asl"
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
Name(STTM, Buffer(20) {
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x1f, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
/* Start by clearing the PhyRdyChg bits */
|
||||
Method(_INI) {
|
||||
\_GPE._L1F()
|
||||
}
|
||||
|
||||
Device(PMRY)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(PMST) {
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P0IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
}/* end of PMST */
|
||||
|
||||
Device(PSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P1IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of PSLA */
|
||||
} /* end of PMRY */
|
||||
|
||||
|
||||
Device(SEDY)
|
||||
{
|
||||
Name(_ADR, 1) /* IDE Scondary Channel */
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(SMST)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P2IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SMST */
|
||||
|
||||
Device(SSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P3IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SSLA */
|
||||
} /* end of SEDY */
|
||||
|
||||
/* SATA Hot Plug Support */
|
||||
Scope(\_GPE) {
|
||||
Method(_L1F,0x0,NotSerialized) {
|
||||
if (\_SB.P0PR) {
|
||||
if (LGreater(\_SB.P0IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P0PR)
|
||||
}
|
||||
|
||||
if (\_SB.P1PR) {
|
||||
if (LGreater(\_SB.P1IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P1PR)
|
||||
}
|
||||
|
||||
if (\_SB.P2PR) {
|
||||
if (LGreater(\_SB.P2IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P2PR)
|
||||
}
|
||||
|
||||
if (\_SB.P3PR) {
|
||||
if (LGreater(\_SB.P3IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P3PR)
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1,158 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
/*
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
|
||||
)
|
||||
{
|
||||
#include "usb.asl"
|
||||
}
|
||||
*/
|
||||
Method(UCOC, 0) {
|
||||
Sleep(20)
|
||||
Store(0x13,CMTI)
|
||||
Store(0,GPSL)
|
||||
}
|
||||
|
||||
/* USB Port 0 overcurrent uses Gpm 0 */
|
||||
If(LLessEqual(UOM0,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L13) {
|
||||
UCOC()
|
||||
if(LEqual(GPB0,PLC0)) {
|
||||
Not(PLC0,PLC0)
|
||||
Store(PLC0, \_SB.PT0D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 1 overcurrent uses Gpm 1 */
|
||||
If (LLessEqual(UOM1,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L14) {
|
||||
UCOC()
|
||||
if (LEqual(GPB1,PLC1)) {
|
||||
Not(PLC1,PLC1)
|
||||
Store(PLC1, \_SB.PT1D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 2 overcurrent uses Gpm 2 */
|
||||
If (LLessEqual(UOM2,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L15) {
|
||||
UCOC()
|
||||
if (LEqual(GPB2,PLC2)) {
|
||||
Not(PLC2,PLC2)
|
||||
Store(PLC2, \_SB.PT2D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 3 overcurrent uses Gpm 3 */
|
||||
If (LLessEqual(UOM3,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L16) {
|
||||
UCOC()
|
||||
if (LEqual(GPB3,PLC3)) {
|
||||
Not(PLC3,PLC3)
|
||||
Store(PLC3, \_SB.PT3D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 4 overcurrent uses Gpm 4 */
|
||||
If (LLessEqual(UOM4,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L19) {
|
||||
UCOC()
|
||||
if (LEqual(GPB4,PLC4)) {
|
||||
Not(PLC4,PLC4)
|
||||
Store(PLC4, \_SB.PT4D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 5 overcurrent uses Gpm 5 */
|
||||
If (LLessEqual(UOM5,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L1A) {
|
||||
UCOC()
|
||||
if (LEqual(GPB5,PLC5)) {
|
||||
Not(PLC5,PLC5)
|
||||
Store(PLC5, \_SB.PT5D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 6 overcurrent uses Gpm 6 */
|
||||
If (LLessEqual(UOM6,9)) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1C) { */
|
||||
Method (_L06) {
|
||||
UCOC()
|
||||
if (LEqual(GPB6,PLC6)) {
|
||||
Not(PLC6,PLC6)
|
||||
Store(PLC6, \_SB.PT6D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 7 overcurrent uses Gpm 7 */
|
||||
If (LLessEqual(UOM7,9)) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1D) { */
|
||||
Method (_L07) {
|
||||
UCOC()
|
||||
if (LEqual(GPB7,PLC7)) {
|
||||
Not(PLC7,PLC7)
|
||||
Store(PLC7, \_SB.PT7D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 8 overcurrent uses Gpm 8 */
|
||||
If (LLessEqual(UOM8,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L17) {
|
||||
if (LEqual(G8IS,PLC8)) {
|
||||
Not(PLC8,PLC8)
|
||||
Store(PLC8, \_SB.PT8D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 9 overcurrent uses Gpm 9 */
|
||||
If (LLessEqual(UOM9,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L0E) {
|
||||
if (LEqual(G9IS,0)) {
|
||||
Store(1,\_SB.PT9D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1,44 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
/* create all subtables for processors */
|
||||
current = acpi_create_madt_lapics(current);
|
||||
|
||||
/* Write SB700 IOAPIC, only one */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
|
||||
IO_APIC_ADDR, 0);
|
||||
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 0, 2, 0);
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 9, 9, 0xF);
|
||||
/* 0: mean bus 0--->ISA */
|
||||
/* 0: PIC 0 */
|
||||
/* 2: APIC 2 */
|
||||
/* 5 mean: 0101 --> Edge-triggered, Active high */
|
||||
|
||||
/* create all subtables for processors */
|
||||
/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
|
||||
/* 1: LINT1 connect to NMI */
|
||||
|
||||
return current;
|
||||
}
|
||||
@@ -1,7 +0,0 @@
|
||||
Category: desktop
|
||||
Board URL: http://www.asus.com/Motherboards/AMD_AM2Plus/M4A78EM/
|
||||
ROM package: DIP8
|
||||
ROM protocol: SPI
|
||||
ROM socketed: y
|
||||
Flashrom support: y
|
||||
Release year: 2009
|
||||
@@ -1,52 +0,0 @@
|
||||
entries
|
||||
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
#392 3 r 0 unused
|
||||
395 1 e 1 hw_scrubber
|
||||
396 1 e 1 interleave_chip_selects
|
||||
397 2 e 8 max_mem_clock
|
||||
399 1 e 2 multi_core
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
440 4 e 9 slow_cpu
|
||||
444 1 e 1 nmi
|
||||
445 1 e 1 gart
|
||||
456 1 e 1 ECC_memory
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
6 5 Notice
|
||||
6 6 Info
|
||||
6 7 Debug
|
||||
6 8 Spew
|
||||
8 0 400Mhz
|
||||
8 1 333Mhz
|
||||
8 2 266Mhz
|
||||
8 3 200Mhz
|
||||
9 0 off
|
||||
9 1 87.5%
|
||||
9 2 75.0%
|
||||
9 3 62.5%
|
||||
9 4 50.0%
|
||||
9 5 37.5%
|
||||
9 6 25.0%
|
||||
9 7 12.5%
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
@@ -1,106 +0,0 @@
|
||||
chip northbridge/amd/amdfam10/root_complex
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_AM3 #L1 and DDR2
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device domain 0 on
|
||||
subsystemid 0x1043 0x83f1 inherit
|
||||
chip northbridge/amd/amdfam10
|
||||
device pci 18.0 on # northbridge
|
||||
chip southbridge/amd/rs780
|
||||
device pci 0.0 on end # HT 0x9600
|
||||
device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
|
||||
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
|
||||
device pci 3.0 on end # PCIE P2P bridge 0x960b
|
||||
device pci 4.0 on end # PCIE P2P bridge 0x9604
|
||||
device pci 5.0 off end # PCIE P2P bridge 0x9605
|
||||
device pci 6.0 off end # PCIE P2P bridge 0x9606
|
||||
device pci 7.0 off end # PCIE P2P bridge 0x9607
|
||||
device pci 8.0 off end # NB/SB Link P2P bridge
|
||||
device pci 9.0 on end #
|
||||
device pci a.0 on end # bridge to RTL8112 PCI Express Gigabit Ethernet
|
||||
register "gppsb_configuration" = "1" # Configuration B
|
||||
register "gpp_configuration" = "3" # Configuration D default
|
||||
register "port_enable" = "0x6fc"
|
||||
register "gfx_dev2_dev3" = "1"
|
||||
register "gfx_dual_slot" = "2"
|
||||
|
||||
register "gfx_lane_reversal" = "0"
|
||||
register "gfx_tmds" = "0"
|
||||
register "gfx_compliance" = "0"
|
||||
register "gfx_reconfiguration" = "1"
|
||||
register "gfx_link_width" = "0"
|
||||
end
|
||||
chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus
|
||||
device pci 11.0 on end # SATA
|
||||
device pci 12.0 on end # USB
|
||||
device pci 12.1 on end # USB
|
||||
device pci 12.2 on end # USB
|
||||
device pci 13.0 on end # USB
|
||||
device pci 13.1 on end # USB
|
||||
device pci 13.2 on end # USB
|
||||
device pci 14.0 on # SM
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
end # SM
|
||||
device pci 14.1 on end # IDE 0x439c
|
||||
device pci 14.2 on end # HDA 0x4383
|
||||
device pci 14.3 on # LPC 0x439d
|
||||
chip superio/ite/it8712f
|
||||
device pnp 2e.0 off end # Floppy
|
||||
device pnp 2e.1 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.2 off # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.3 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.4 off end # Environment Controller
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.6 on # Mouse
|
||||
irq 0x70 = 12
|
||||
end
|
||||
device pnp 2e.7 off # GPIO, must be closed for unresolved reason.
|
||||
end
|
||||
device pnp 2e.8 off # MIDI
|
||||
end
|
||||
device pnp 2e.9 off # GAME
|
||||
end
|
||||
device pnp 2e.a off end # CIR
|
||||
end #superio
|
||||
end #LPC
|
||||
device pci 14.4 on end # PCI to PCI Bridge [1002:4384]
|
||||
device pci 14.5 on end # USB 2
|
||||
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
|
||||
end #southbridge/amd/sb700
|
||||
end # device pci 18.0
|
||||
|
||||
device pci 18.0 on end
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
device pci 18.4 on end
|
||||
end # chip northbridge
|
||||
end #domain
|
||||
end # northbridge/amd/amdfam10/root_complex
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,44 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/pci.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <cpu/amd/multicore.h>
|
||||
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
/* Global variables for MB layouts and these will be shared by irqtable mptable
|
||||
* and acpi_tables busnum is default.
|
||||
*/
|
||||
u32 apicid_sb700;
|
||||
|
||||
void get_bus_conf(void)
|
||||
{
|
||||
u32 apicid_base;
|
||||
|
||||
get_default_pci1234(1);
|
||||
|
||||
sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
|
||||
|
||||
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
if (CONFIG(LOGICAL_CPUS))
|
||||
apicid_base = get_apicid_base(1);
|
||||
else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
apicid_sb700 = apicid_base + 0;
|
||||
}
|
||||
@@ -1,60 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Juhana Helovuo <juhe@iki.fi>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
static const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
|
||||
0x00, /* Interrupt router bus */
|
||||
(0x14 << 3) | 0x3, /* Interrupt router dev */
|
||||
0, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1002, /* Vendor */
|
||||
0x439d, /* Device */
|
||||
0, /* Miniport */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0xca, /* Checksum (has to be set to some value that
|
||||
* would give 0 after the sum of all bytes
|
||||
* for this structure (including checksum).
|
||||
*/
|
||||
{
|
||||
/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x01, (0x05 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
|
||||
{0x00, (0x02 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
|
||||
{0x00, (0x03 << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0},
|
||||
{0x00, (0x04 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
|
||||
{0x00, (0x05 << 3) | 0x0, {{0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}}, 0x0, 0x0},
|
||||
{0x00, (0x06 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
|
||||
{0x00, (0x07 << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0},
|
||||
{0x00, (0x09 << 3) | 0x0, {{0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}}, 0x0, 0x0},
|
||||
{0x00, (0x0a << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
|
||||
{0x02, (0x00 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0xa, 0x0},
|
||||
{0x00, (0x0b << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0},
|
||||
{0x00, (0x0c << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
|
||||
{0x00, (0x14 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
|
||||
{0x00, (0x12 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
|
||||
{0x00, (0x13 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
|
||||
{0x00, (0x11 << 3) | 0x0, {{0x0c, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
|
||||
{0x03, (0x06 << 3) | 0x0, {{0x0a, 0xdc90}, {0x0b, 0xdc90}, {0x0c, 0xdc90}, {0x0d, 0xdc90}}, 0xd, 0x0},
|
||||
{0x03, (0x07 << 3) | 0x0, {{0x0b, 0xdc90}, {0x0c, 0xdc90}, {0x0d, 0xdc90}, {0x0a, 0xdc90}}, 0xe, 0x0},
|
||||
}
|
||||
};
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
|
||||
}
|
||||
@@ -1,116 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <southbridge/amd/sb700/sb700.h>
|
||||
#include <southbridge/amd/sb700/smbus.h>
|
||||
#include <southbridge/amd/rs780/rs780.h>
|
||||
|
||||
void set_pcie_dereset(void)
|
||||
{
|
||||
u8 byte;
|
||||
u16 word;
|
||||
struct device *sm_dev;
|
||||
/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
|
||||
/* set 0 to bit2 :disable GPM8 as AZ_RST output */
|
||||
byte = pm_ioread(0x8d);
|
||||
byte &= ~((1 << 1) | (1 << 2));
|
||||
pm_iowrite(0x8d, byte);
|
||||
|
||||
/* set the GPM8 and GPM9 output enable and the value to 1 */
|
||||
byte = pm_ioread(0x94);
|
||||
byte &= ~((1 << 2) | (1 << 3));
|
||||
byte |= ((1 << 0) | (1 << 1));
|
||||
pm_iowrite(0x94, byte);
|
||||
|
||||
/* set the GPIO65 output enable and the value is 1 */
|
||||
sm_dev = pcidev_on_root(0x14, 0);
|
||||
word = pci_read_config16(sm_dev, 0x7e);
|
||||
word |= (1 << 0);
|
||||
word &= ~(1 << 4);
|
||||
pci_write_config16(sm_dev, 0x7e, word);
|
||||
}
|
||||
|
||||
void set_pcie_reset(void)
|
||||
{
|
||||
u8 byte;
|
||||
u16 word;
|
||||
struct device *sm_dev;
|
||||
|
||||
/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
|
||||
/* set 0 to bit2 :disable GPM8 as AZ_RST output */
|
||||
byte = pm_ioread(0x8d);
|
||||
byte &= ~((1 << 1) | (1 << 2));
|
||||
pm_iowrite(0x8d, byte);
|
||||
|
||||
/* set the GPM8 and GPM9 output enable and the value to 0 */
|
||||
byte = pm_ioread(0x94);
|
||||
byte &= ~((1 << 2) | (1 << 3));
|
||||
byte &= ~((1 << 0) | (1 << 1));
|
||||
pm_iowrite(0x94, byte);
|
||||
|
||||
/* set the GPIO65 output enable and the value is 0 */
|
||||
sm_dev = pcidev_on_root(0x14, 0);
|
||||
word = pci_read_config16(sm_dev, 0x7e);
|
||||
word &= ~(1 << 0);
|
||||
word &= ~(1 << 4);
|
||||
pci_write_config16(sm_dev, 0x7e, word);
|
||||
}
|
||||
|
||||
/*
|
||||
* justify the dev3 is exist or not
|
||||
* NOTE: This just copied from AMD Tilapia code.
|
||||
* It is completely unknown if it will work at all for this board.
|
||||
*/
|
||||
int is_dev3_present(void)
|
||||
{
|
||||
u16 word;
|
||||
struct device *sm_dev;
|
||||
|
||||
/* access the smbus extended register */
|
||||
sm_dev = pcidev_on_root(0x14, 0);
|
||||
|
||||
/* put the GPIO68 output to tristate */
|
||||
word = pci_read_config16(sm_dev, 0x7e);
|
||||
word |= 1 << 6;
|
||||
pci_write_config16(sm_dev, 0x7e,word);
|
||||
|
||||
/* read the GPIO68 input status */
|
||||
word = pci_read_config16(sm_dev, 0x7e);
|
||||
|
||||
return !(word & (1 << 10));
|
||||
}
|
||||
|
||||
|
||||
/*************************************************
|
||||
* enable the dedicated function in this board.
|
||||
* This function called early than rs780_enable.
|
||||
*************************************************/
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev);
|
||||
|
||||
set_pcie_dereset();
|
||||
/* get_ide_dma66(); */
|
||||
/* set_thermal_config(); */
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
@@ -1,103 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <stdint.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
|
||||
extern u32 apicid_sb700;
|
||||
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
{
|
||||
struct device *dev;
|
||||
u32 dword;
|
||||
u8 byte;
|
||||
|
||||
dev =
|
||||
dev_find_slot(pirq_router_bus,
|
||||
PCI_DEVFN(0x14, 0));
|
||||
if (dev) {
|
||||
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
|
||||
smp_write_ioapic(mc, apicid_sb700,
|
||||
0x11,(void *) dword);
|
||||
|
||||
/* Initialize interrupt mapping */
|
||||
/* aza */
|
||||
byte = pci_read_config8(dev, 0x63);
|
||||
byte &= 0xf8;
|
||||
byte |= 0; /* 0: INTA, ...., 7: INTH */
|
||||
pci_write_config8(dev, 0x63, byte);
|
||||
|
||||
/* SATA */
|
||||
dword = pci_read_config32(dev, 0xac);
|
||||
dword &= ~(7 << 26);
|
||||
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
|
||||
/* dword |= 1 << 22; PIC and APIC co exists */
|
||||
pci_write_config32(dev, 0xac, dword);
|
||||
|
||||
/*
|
||||
* 00:12.0: PROG SATA : INT F
|
||||
* 00:13.0: INTA USB_0
|
||||
* 00:13.1: INTB USB_1
|
||||
* 00:13.2: INTC USB_2
|
||||
* 00:13.3: INTD USB_3
|
||||
* 00:13.4: INTC USB_4
|
||||
* 00:13.5: INTD USB2
|
||||
* 00:14.1: INTA IDE
|
||||
* 00:14.2: Prog HDA : INT E
|
||||
* 00:14.5: INTB ACI
|
||||
* 00:14.6: INTB MCI
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
@@ -1,279 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#include <commonlib/helpers.h>
|
||||
#include <northbridge/amd/amdfam10/amdfam10.h>
|
||||
|
||||
void setup_mb_resource_map(void)
|
||||
{
|
||||
static const unsigned int register_values[] = {
|
||||
/* Careful set limit registers before base registers which contain the enables */
|
||||
/* DRAM Limit i Registers
|
||||
* F1:0x44 i = 0
|
||||
* F1:0x4C i = 1
|
||||
* F1:0x54 i = 2
|
||||
* F1:0x5C i = 3
|
||||
* F1:0x64 i = 4
|
||||
* F1:0x6C i = 5
|
||||
* F1:0x74 i = 6
|
||||
* F1:0x7C i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 3] Reserved
|
||||
* [10: 8] Interleave select
|
||||
* specifies the values of A[14:12] to use with interleave enable.
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Limit Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40 bit address
|
||||
* that define the end of the DRAM region.
|
||||
*/
|
||||
// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
|
||||
ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001,
|
||||
ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002,
|
||||
ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003,
|
||||
ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004,
|
||||
ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005,
|
||||
ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006,
|
||||
ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
|
||||
/* DRAM Base i Registers
|
||||
* F1:0x40 i = 0
|
||||
* F1:0x48 i = 1
|
||||
* F1:0x50 i = 2
|
||||
* F1:0x58 i = 3
|
||||
* F1:0x60 i = 4
|
||||
* F1:0x68 i = 5
|
||||
* F1:0x70 i = 6
|
||||
* F1:0x78 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 7: 2] Reserved
|
||||
* [10: 8] Interleave Enable
|
||||
* 000 = No interleave
|
||||
* 001 = Interleave on A[12] (2 nodes)
|
||||
* 010 = reserved
|
||||
* 011 = Interleave on A[12] and A[14] (4 nodes)
|
||||
* 100 = reserved
|
||||
* 101 = reserved
|
||||
* 110 = reserved
|
||||
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
|
||||
* [15:11] Reserved
|
||||
* [13:16] DRAM Base Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40-bit address
|
||||
* that define the start of the DRAM region.
|
||||
*/
|
||||
// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
|
||||
ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
* F1:0x8C i = 1
|
||||
* F1:0x94 i = 2
|
||||
* F1:0x9C i = 3
|
||||
* F1:0xA4 i = 4
|
||||
* F1:0xAC i = 5
|
||||
* F1:0xB4 i = 6
|
||||
* F1:0xBC i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Reserved
|
||||
* [ 6: 6] Reserved
|
||||
* [ 7: 7] Non-Posted
|
||||
* 0 = CPU writes may be posted
|
||||
* 1 = CPU writes must be non-posted
|
||||
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
|
||||
* This field defines the upp address bits of a 40-bit address that
|
||||
* defines the end of a memory-mapped I/O region n
|
||||
*/
|
||||
ADDRMAP_REG(0x84), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x8C), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x94), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x9C), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xA4), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xAC), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
|
||||
// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
|
||||
|
||||
/* Memory-Mapped I/O Base i Registers
|
||||
* F1:0x80 i = 0
|
||||
* F1:0x88 i = 1
|
||||
* F1:0x90 i = 2
|
||||
* F1:0x98 i = 3
|
||||
* F1:0xA0 i = 4
|
||||
* F1:0xA8 i = 5
|
||||
* F1:0xB0 i = 6
|
||||
* F1:0xB8 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Cpu Disable
|
||||
* 0 = Cpu can use this I/O range
|
||||
* 1 = Cpu requests do not use this I/O range
|
||||
* [ 3: 3] Lock
|
||||
* 0 = base/limit registers i are read/write
|
||||
* 1 = base/limit registers i are read-only
|
||||
* [ 7: 4] Reserved
|
||||
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
|
||||
* This field defines the upper address bits of a 40bit address
|
||||
* that defines the start of memory-mapped I/O region i
|
||||
*/
|
||||
ADDRMAP_REG(0x80), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x88), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x90), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x98), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
|
||||
// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
|
||||
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
* F1:0xCC i = 1
|
||||
* F1:0xD4 i = 2
|
||||
* F1:0xDC i = 3
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = reserved
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Limit Address i
|
||||
* This field defines the end of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000,
|
||||
ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000,
|
||||
ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000,
|
||||
ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
|
||||
|
||||
/* PCI I/O Base i Registers
|
||||
* F1:0xC0 i = 0
|
||||
* F1:0xC8 i = 1
|
||||
* F1:0xD0 i = 2
|
||||
* F1:0xD8 i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 3: 2] Reserved
|
||||
* [ 4: 4] VGA Enable
|
||||
* 0 = VGA matches Disabled
|
||||
* 1 = matches all address < 64K and where A[9:0] is in the
|
||||
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
|
||||
* [ 5: 5] ISA Enable
|
||||
* 0 = ISA matches Disabled
|
||||
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
|
||||
* from matching agains this base/limit pair
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Base i
|
||||
* This field defines the start of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003,
|
||||
ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000,
|
||||
ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000,
|
||||
ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
|
||||
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
* F1:0xE8 i = 2
|
||||
* F1:0xEC i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Device Number Compare Enable
|
||||
* 0 = The ranges are based on bus number
|
||||
* 1 = The ranges are ranges of devices on bus 0
|
||||
* [ 3: 3] Reserved
|
||||
* [ 6: 4] Destination Node
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 7] Reserved
|
||||
* [ 9: 8] Destination Link
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 - Reserved
|
||||
* [15:10] Reserved
|
||||
* [23:16] Bus Number Base i
|
||||
* This field defines the lowest bus number in configuration region i
|
||||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration regin i
|
||||
*/
|
||||
// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
|
||||
ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000,
|
||||
ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000,
|
||||
ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
|
||||
};
|
||||
|
||||
int max;
|
||||
max = ARRAY_SIZE(register_values);
|
||||
setup_resource_map(register_values, max);
|
||||
}
|
||||
@@ -1,227 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
//#define SYSTEM_TYPE 0 /* SERVER */
|
||||
#define SYSTEM_TYPE 1 /* DESKTOP */
|
||||
//#define SYSTEM_TYPE 2 /* MOBILE */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <console/console.h>
|
||||
#include <timestamp.h>
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include <superio/ite/common/ite.h>
|
||||
#include <superio/ite/it8712f/it8712f.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <cpu/amd/car.h>
|
||||
#include <cpu/amd/msr.h>
|
||||
#include <southbridge/amd/common/reset.h>
|
||||
#include <southbridge/amd/sb700/sb700.h>
|
||||
#include <southbridge/amd/sb700/smbus.h>
|
||||
#include <northbridge/amd/amdfam10/raminit.h>
|
||||
#include <northbridge/amd/amdht/ht_wrapper.h>
|
||||
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
|
||||
#include <arch/early_variables.h>
|
||||
#include <cbmem.h>
|
||||
#include <spd.h>
|
||||
#include <southbridge/amd/rs780/rs780.h>
|
||||
|
||||
#include "cpu/amd/quadcore/quadcore.c"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
|
||||
#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
|
||||
|
||||
int spd_read_byte(unsigned int device, unsigned int address);
|
||||
|
||||
|
||||
int spd_read_byte(u32 device, u32 address)
|
||||
{
|
||||
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
|
||||
}
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
struct sys_info *sysinfo = get_sysinfo();
|
||||
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
|
||||
u32 bsp_apicid = 0, val;
|
||||
msr_t msr;
|
||||
|
||||
timestamp_init(timestamp_get());
|
||||
timestamp_add_now(TS_START_ROMSTAGE);
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
/* mov bsp to bus 0xff when > 8 nodes */
|
||||
set_bsp_node_CHtExtNodeCfgEn();
|
||||
enumerate_ht_chain();
|
||||
sb7xx_51xx_pci_port80();
|
||||
}
|
||||
|
||||
post_code(0x30);
|
||||
|
||||
if (bist == 0) {
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
|
||||
/* All cores run this but the BSP(node0,core0) is the only core that returns. */
|
||||
}
|
||||
|
||||
post_code(0x32);
|
||||
|
||||
enable_rs780_dev8();
|
||||
sb7xx_51xx_lpc_init();
|
||||
|
||||
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
ite_kill_watchdog(GPIO_DEV);
|
||||
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
// Load MPB
|
||||
val = cpuid_eax(1);
|
||||
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
|
||||
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
|
||||
printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
|
||||
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
|
||||
|
||||
/* Setup sysinfo defaults */
|
||||
set_sysinfo_in_ram(0);
|
||||
|
||||
update_microcode(val);
|
||||
|
||||
post_code(0x33);
|
||||
|
||||
cpuSetAMDMSR(0);
|
||||
post_code(0x34);
|
||||
|
||||
amd_ht_init(sysinfo);
|
||||
post_code(0x35);
|
||||
|
||||
/* Setup nodes PCI space and start core 0 AP init. */
|
||||
finalize_node_setup(sysinfo);
|
||||
|
||||
/* Setup any mainboard PCI settings etc. */
|
||||
setup_mb_resource_map();
|
||||
post_code(0x36);
|
||||
|
||||
/* wait for all the APs core0 started by finalize_node_setup. */
|
||||
/* FIXME: A bunch of cores are going to start output to serial at once.
|
||||
It would be nice to fixup prink spinlocks for ROM XIP mode.
|
||||
I think it could be done by putting the spinlock flag in the cache
|
||||
of the BSP located right after sysinfo.
|
||||
*/
|
||||
wait_all_core0_started();
|
||||
|
||||
#if CONFIG(LOGICAL_CPUS)
|
||||
/* Core0 on each node is configured. Now setup any additional cores. */
|
||||
printk(BIOS_DEBUG, "start_other_cores()\n");
|
||||
start_other_cores(bsp_apicid);
|
||||
post_code(0x37);
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
#endif
|
||||
|
||||
post_code(0x38);
|
||||
|
||||
/* run _early_setup before soft-reset. */
|
||||
rs780_early_setup();
|
||||
sb7xx_51xx_early_setup();
|
||||
|
||||
#if CONFIG(SET_FIDVID)
|
||||
msr = rdmsr(MSR_COFVID_STS);
|
||||
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
|
||||
|
||||
/* FIXME: The sb fid change may survive the warm reset and only
|
||||
need to be done once.*/
|
||||
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
|
||||
|
||||
post_code(0x39);
|
||||
|
||||
if (!warm_reset_detect(0)) { // BSP is node 0
|
||||
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
|
||||
} else {
|
||||
init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
|
||||
}
|
||||
|
||||
post_code(0x3A);
|
||||
|
||||
/* show final fid and vid */
|
||||
msr = rdmsr(MSR_COFVID_STS);
|
||||
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
|
||||
#endif
|
||||
|
||||
rs780_htinit();
|
||||
|
||||
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
|
||||
if (!warm_reset_detect(0)) {
|
||||
printk(BIOS_INFO, "...WARM RESET...\n\n\n");
|
||||
soft_reset();
|
||||
die("After soft_reset - shouldn't see this message!!!\n");
|
||||
}
|
||||
|
||||
post_code(0x3B);
|
||||
|
||||
/* It's the time to set ctrl in sysinfo now; */
|
||||
printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
|
||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
||||
|
||||
post_code(0x40);
|
||||
|
||||
raminit_amdmct(sysinfo);
|
||||
|
||||
cbmem_initialize_empty();
|
||||
post_code(0x41);
|
||||
|
||||
amdmct_cbmem_store_info(sysinfo);
|
||||
|
||||
sb7xx_51xx_before_pci_init();
|
||||
|
||||
post_code(0x42);
|
||||
}
|
||||
|
||||
/**
|
||||
* BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
|
||||
* Description:
|
||||
* This routine is called every time a non-coherent chain is processed.
|
||||
* BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
|
||||
* swap list. The first part of the list controls the BUID assignment and the
|
||||
* second part of the list provides the device to device linking. Device orientation
|
||||
* can be detected automatically, or explicitly. See documentation for more details.
|
||||
*
|
||||
* Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
|
||||
* based on each device's unit count.
|
||||
*
|
||||
* Parameters:
|
||||
* @param[in] node = The node on which this chain is located
|
||||
* @param[in] link = The link on the host for this chain
|
||||
* @param[out] List = supply a pointer to a list
|
||||
*/
|
||||
BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
|
||||
{
|
||||
static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
|
||||
/* If the BUID was adjusted in early_ht we need to do the manual override */
|
||||
if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
|
||||
printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
|
||||
if ((node == 0) && (link == 0)) { /* BSP SB link */
|
||||
*List = swaplist;
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -1,58 +0,0 @@
|
||||
if BOARD_ASUS_M4A785M
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS
|
||||
def_bool y
|
||||
select CPU_AMD_SOCKET_AM3
|
||||
select DIMM_DDR2
|
||||
select NORTHBRIDGE_AMD_AMDFAM10
|
||||
select SOUTHBRIDGE_AMD_RS780
|
||||
select SOUTHBRIDGE_AMD_SB700
|
||||
select SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
|
||||
select SUPERIO_ITE_IT8712F
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
select LIFT_BSP_APIC_ID
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_1024
|
||||
select ENABLE_APIC_EXT_ID
|
||||
select GFXUMA
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default asus/m4a785-m
|
||||
|
||||
config APIC_ID_OFFSET
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "M4A785-M"
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 8
|
||||
|
||||
config MAX_PHYSICAL_CPUS
|
||||
int
|
||||
default 2
|
||||
|
||||
config HT_CHAIN_END_UNITID_BASE
|
||||
hex
|
||||
default 0x1
|
||||
|
||||
config HT_CHAIN_UNITID_BASE
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 19
|
||||
|
||||
config VGA_BIOS_ID
|
||||
string
|
||||
default "1002,9710"
|
||||
|
||||
endif
|
||||
@@ -1,2 +0,0 @@
|
||||
config BOARD_ASUS_M4A785M
|
||||
bool "M4A785-M"
|
||||
@@ -1,16 +0,0 @@
|
||||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
|
||||
romstage-y += resourcemap.c
|
||||
|
||||
ramstage-y += get_bus_conf.c
|
||||
@@ -1,80 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* This file defines the processor and performance state capability
|
||||
* for each core in the system. It is included into the DSDT for each
|
||||
* core. It assumes that each core of the system has the same performance
|
||||
* characteristics.
|
||||
*/
|
||||
/*
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001)
|
||||
{
|
||||
Scope (\_PR) {
|
||||
Device (CPU0) {
|
||||
Name (_HID, "ACPI0007")
|
||||
Name (_UID, 0)
|
||||
#include "cpstate.asl"
|
||||
}
|
||||
Device (CPU1) {
|
||||
Name (_HID, "ACPI0007")
|
||||
Name (_UID, 1)
|
||||
#include "cpstate.asl"
|
||||
}
|
||||
Device (CPU2) {
|
||||
Name (_HID, "ACPI0007")
|
||||
Name (_UID, 2)
|
||||
#include "cpstate.asl"
|
||||
}
|
||||
Device (CPU3) {
|
||||
Name (_HID, "ACPI0007")
|
||||
Name (_UID, 3)
|
||||
#include "cpstate.asl"
|
||||
}
|
||||
}
|
||||
*/
|
||||
/* P-state support: The maximum number of P-states supported by the */
|
||||
/* CPUs we'll use is 6. */
|
||||
/* Get from AMI BIOS. */
|
||||
Name(_PSS, Package(){
|
||||
Package ()
|
||||
{
|
||||
0x00000AF0,
|
||||
0x0000BF81,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000000,
|
||||
0x00000000
|
||||
},
|
||||
|
||||
Package ()
|
||||
{
|
||||
0x00000578,
|
||||
0x000076F2,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000001,
|
||||
0x00000001
|
||||
}
|
||||
})
|
||||
|
||||
Name(_PCT, Package(){
|
||||
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
|
||||
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
|
||||
})
|
||||
|
||||
Method(_PPC, 0){
|
||||
Return(0)
|
||||
}
|
||||
@@ -1,240 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
Scope (_SB) {
|
||||
Device(PCI0) {
|
||||
Device(IDEC) {
|
||||
Name(_ADR, 0x00140001)
|
||||
#include "ide.asl"
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
/* Some timing tables */
|
||||
Name(UDTT, Package(){ /* Udma timing table */
|
||||
120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
|
||||
})
|
||||
|
||||
Name(MDTT, Package(){ /* MWDma timing table */
|
||||
480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
|
||||
})
|
||||
|
||||
Name(POTT, Package(){ /* Pio timing table */
|
||||
600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
|
||||
})
|
||||
|
||||
/* Some timing register value tables */
|
||||
Name(MDRT, Package(){ /* MWDma timing register table */
|
||||
0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
|
||||
})
|
||||
|
||||
Name(PORT, Package(){
|
||||
0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
|
||||
})
|
||||
|
||||
OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
|
||||
Field(ICRG, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
PPTS, 8, /* Primary PIO Slave Timing */
|
||||
PPTM, 8, /* Primary PIO Master Timing */
|
||||
OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
|
||||
PMTM, 8, /* Primary MWDMA Master Timing */
|
||||
OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
|
||||
OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
|
||||
PPSM, 4, /* Primary PIO slave Mode */
|
||||
OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
|
||||
OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
|
||||
PDSM, 4, /* Primary UltraDMA Mode */
|
||||
}
|
||||
|
||||
Method(GTTM, 1) /* get total time*/
|
||||
{
|
||||
Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
|
||||
Increment(Local0)
|
||||
Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
|
||||
Increment(Local1)
|
||||
Return(Multiply(30, Add(Local0, Local1)))
|
||||
}
|
||||
|
||||
Device(PRID)
|
||||
{
|
||||
Name (_ADR, Zero)
|
||||
Method(_GTM, 0)
|
||||
{
|
||||
NAME(OTBF, Buffer(20) { /* out buffer */
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
|
||||
CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
|
||||
CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
|
||||
CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
|
||||
CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
|
||||
|
||||
/* Just return if the channel is disabled */
|
||||
If(And(PPCR, 0x01)) { /* primary PIO control */
|
||||
Return(OTBF)
|
||||
}
|
||||
|
||||
/* Always tell them independent timing available and IOChannelReady used on both drives */
|
||||
Or(BFFG, 0x1A, BFFG)
|
||||
|
||||
Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
|
||||
Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
|
||||
|
||||
If(And(PDCR, 0x01)) { /* It's under UDMA mode */
|
||||
Or(BFFG, 0x01, BFFG)
|
||||
Store(DerefOf(Index(UDTT, PDMM)), DSD0)
|
||||
}
|
||||
Else {
|
||||
Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
|
||||
}
|
||||
|
||||
If(And(PDCR, 0x02)) { /* It's under UDMA mode */
|
||||
Or(BFFG, 0x04, BFFG)
|
||||
Store(DerefOf(Index(UDTT, PDSM)), DSD1)
|
||||
}
|
||||
Else {
|
||||
Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
|
||||
}
|
||||
|
||||
Return(OTBF) /* out buffer */
|
||||
} /* End Method(_GTM) */
|
||||
|
||||
Method(_STM, 3, NotSerialized)
|
||||
{
|
||||
NAME(INBF, Buffer(20) { /* in buffer */
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
|
||||
CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
|
||||
CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
|
||||
CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
|
||||
CreateDwordField(INBF, 16, BFFG) /*buffer flag */
|
||||
|
||||
Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
|
||||
Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
|
||||
Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
|
||||
|
||||
Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
|
||||
Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
|
||||
|
||||
If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
|
||||
Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 7, PDMM,)
|
||||
Or(PDCR, 0x01, PDCR)
|
||||
}
|
||||
Else {
|
||||
If(LNotEqual(DSD0, 0xFFFFFFFF)) {
|
||||
Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
|
||||
Store(DerefOf(Index(MDRT, Local0)), PMTM)
|
||||
}
|
||||
}
|
||||
|
||||
If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
|
||||
Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 7, PDSM,)
|
||||
Or(PDCR, 0x02, PDCR)
|
||||
}
|
||||
Else {
|
||||
If(LNotEqual(DSD1, 0xFFFFFFFF)) {
|
||||
Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
|
||||
Store(DerefOf(Index(MDRT, Local0)), PMTS)
|
||||
}
|
||||
}
|
||||
/* Return(INBF) */
|
||||
} /*End Method(_STM) */
|
||||
Device(MST)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_GTF) {
|
||||
Name(CMBF, Buffer(21) {
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
|
||||
})
|
||||
CreateByteField(CMBF, 1, POMD)
|
||||
CreateByteField(CMBF, 8, DMMD)
|
||||
CreateByteField(CMBF, 5, CMDA)
|
||||
CreateByteField(CMBF, 12, CMDB)
|
||||
CreateByteField(CMBF, 19, CMDC)
|
||||
|
||||
Store(0xA0, CMDA)
|
||||
Store(0xA0, CMDB)
|
||||
Store(0xA0, CMDC)
|
||||
|
||||
Or(PPMM, 0x08, POMD)
|
||||
|
||||
If(And(PDCR, 0x01)) {
|
||||
Or(PDMM, 0x40, DMMD)
|
||||
}
|
||||
Else {
|
||||
Store(Match
|
||||
(MDTT, MLE, GTTM(PMTM),
|
||||
MTR, 0, 0), Local0)
|
||||
If(LLess(Local0, 3)) {
|
||||
Or(0x20, Local0, DMMD)
|
||||
}
|
||||
}
|
||||
Return(CMBF)
|
||||
}
|
||||
} /* End Device(MST) */
|
||||
|
||||
Device(SLAV)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_GTF) {
|
||||
Name(CMBF, Buffer(21) {
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
|
||||
})
|
||||
CreateByteField(CMBF, 1, POMD)
|
||||
CreateByteField(CMBF, 8, DMMD)
|
||||
CreateByteField(CMBF, 5, CMDA)
|
||||
CreateByteField(CMBF, 12, CMDB)
|
||||
CreateByteField(CMBF, 19, CMDC)
|
||||
|
||||
Store(0xB0, CMDA)
|
||||
Store(0xB0, CMDB)
|
||||
Store(0xB0, CMDC)
|
||||
|
||||
Or(PPSM, 0x08, POMD)
|
||||
|
||||
If(And(PDCR, 0x02)) {
|
||||
Or(PDSM, 0x40, DMMD)
|
||||
}
|
||||
Else {
|
||||
Store(Match
|
||||
(MDTT, MLE, GTTM(PMTS),
|
||||
MTR, 0, 0), Local0)
|
||||
If(LLess(Local0, 3)) {
|
||||
Or(0x20, Local0, DMMD)
|
||||
}
|
||||
}
|
||||
Return(CMBF)
|
||||
}
|
||||
} /* End Device(SLAV) */
|
||||
}
|
||||
@@ -1,297 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
|
||||
)
|
||||
{
|
||||
#include "routing.asl"
|
||||
}
|
||||
*/
|
||||
|
||||
/* Routing is in System Bus scope */
|
||||
Scope(\_SB) {
|
||||
Name(PR0, Package(){
|
||||
/* NB devices */
|
||||
/* Bus 0, Dev 0 - RS780 Host Controller */
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
|
||||
Package(){0x0002FFFF, 0, INTC, 0 },
|
||||
Package(){0x0002FFFF, 1, INTD, 0 },
|
||||
Package(){0x0002FFFF, 2, INTA, 0 },
|
||||
Package(){0x0002FFFF, 3, INTB, 0 },
|
||||
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
|
||||
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||
Package(){0x0004FFFF, 0, INTA, 0 },
|
||||
Package(){0x0004FFFF, 1, INTB, 0 },
|
||||
Package(){0x0004FFFF, 2, INTC, 0 },
|
||||
Package(){0x0004FFFF, 3, INTD, 0 },
|
||||
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||
/* Package(){0x0005FFFF, 0, INTB, 0 }, */
|
||||
/* Package(){0x0005FFFF, 1, INTC, 0 }, */
|
||||
/* Package(){0x0005FFFF, 2, INTD, 0 }, */
|
||||
/* Package(){0x0005FFFF, 3, INTA, 0 }, */
|
||||
/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
|
||||
Package(){0x0006FFFF, 0, INTC, 0 },
|
||||
Package(){0x0006FFFF, 1, INTD, 0 },
|
||||
Package(){0x0006FFFF, 2, INTA, 0 },
|
||||
Package(){0x0006FFFF, 3, INTB, 0 },
|
||||
/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
|
||||
Package(){0x0007FFFF, 0, INTD, 0 },
|
||||
Package(){0x0007FFFF, 1, INTA, 0 },
|
||||
Package(){0x0007FFFF, 2, INTB, 0 },
|
||||
Package(){0x0007FFFF, 3, INTC, 0 },
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
/* SB devices */
|
||||
/* Bus 0, Dev 17 - SATA controller #2 */
|
||||
/* Bus 0, Dev 18 - SATA controller #1 */
|
||||
Package(){0x0011FFFF, 1, INTA, 0 },
|
||||
|
||||
/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
|
||||
Package(){0x0012FFFF, 0, INTA, 0 },
|
||||
Package(){0x0012FFFF, 1, INTB, 0 },
|
||||
Package(){0x0013FFFF, 0, INTA, 0 },
|
||||
Package(){0x0013FFFF, 1, INTB, 0 },
|
||||
Package(){0x0014FFFF, 2, INTA, 0 },
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */
|
||||
Package(){0x0014FFFF, 0, INTA, 0 },
|
||||
Package(){0x0014FFFF, 1, INTB, 0 },
|
||||
Package(){0x0014FFFF, 2, INTC, 0 },
|
||||
Package(){0x0014FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APR0, Package(){
|
||||
/* NB devices in APIC mode */
|
||||
/* Bus 0, Dev 0 - RS780 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
/* Package(){0x0001FFFF, 0, 0, 18 }, */
|
||||
/* Package(){0x0001FFFF, 1, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
|
||||
Package(){0x0002FFFF, 0, 0, 18 },
|
||||
/* Package(){0x0002FFFF, 1, 0, 19 }, */
|
||||
/* Package(){0x0002FFFF, 2, 0, 16 }, */
|
||||
/* Package(){0x0002FFFF, 3, 0, 17 }, */
|
||||
|
||||
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
|
||||
Package(){0x0003FFFF, 0, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||
Package(){0x0004FFFF, 0, 0, 16 },
|
||||
/* Package(){0x0004FFFF, 1, 0, 17 }, */
|
||||
/* Package(){0x0004FFFF, 2, 0, 18 }, */
|
||||
/* Package(){0x0004FFFF, 3, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||
/* Package(){0x0005FFFF, 0, 0, 17 }, */
|
||||
/* Package(){0x0005FFFF, 1, 0, 18 }, */
|
||||
/* Package(){0x0005FFFF, 2, 0, 19 }, */
|
||||
/* Package(){0x0005FFFF, 3, 0, 16 }, */
|
||||
|
||||
/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
|
||||
/* Package(){0x0006FFFF, 0, 0, 18 }, */
|
||||
/* Package(){0x0006FFFF, 1, 0, 19 }, */
|
||||
/* Package(){0x0006FFFF, 2, 0, 16 }, */
|
||||
/* Package(){0x0006FFFF, 3, 0, 17 }, */
|
||||
|
||||
/* Bus 0, Dev 7 - PCIe Bridge for network card */
|
||||
/* Package(){0x0007FFFF, 0, 0, 19 }, */
|
||||
/* Package(){0x0007FFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x0007FFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x0007FFFF, 3, 0, 18 }, */
|
||||
|
||||
/* Bus 0, Dev 9 - PCIe Bridge for network card */
|
||||
Package(){0x0009FFFF, 0, 0, 17 },
|
||||
/* Package(){0x0009FFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x0009FFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x0009FFFF, 3, 0, 18 }, */
|
||||
/* Bus 0, Dev A - PCIe Bridge for network card */
|
||||
Package(){0x000AFFFF, 0, 0, 18 },
|
||||
/* Package(){0x000AFFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x000AFFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x000AFFFF, 3, 0, 18 }, */
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
/* SB devices in APIC mode */
|
||||
/* Bus 0, Dev 17 - SATA controller #2 */
|
||||
/* Bus 0, Dev 18 - SATA controller #1 */
|
||||
Package(){0x0011FFFF, 0, 0, 22 },
|
||||
|
||||
/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
|
||||
Package(){0x0012FFFF, 0, 0, 16 },
|
||||
Package(){0x0012FFFF, 1, 0, 17 },
|
||||
Package(){0x0013FFFF, 0, 0, 18 },
|
||||
Package(){0x0013FFFF, 1, 0, 19 },
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
/* Package(){0x00130004, 2, 0, 18 }, */
|
||||
/* Package(){0x00130005, 3, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
Package(){0x0014FFFF, 1, 0, 17 },
|
||||
Package(){0x0014FFFF, 2, 0, 18 },
|
||||
Package(){0x0014FFFF, 3, 0, 19 },
|
||||
/* Package(){0x00140004, 2, 0, 18 }, */
|
||||
/* Package(){0x00140004, 3, 0, 19 }, */
|
||||
/* Package(){0x00140005, 1, 0, 17 }, */
|
||||
/* Package(){0x00140006, 1, 0, 17 }, */
|
||||
})
|
||||
|
||||
Name(PR1, Package(){
|
||||
/* Internal graphics - RS780 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, INTA, 0 },
|
||||
Package(){0x0005FFFF, 1, INTB, 0 },
|
||||
Package(){0x0005FFFF, 2, INTC, 0 },
|
||||
Package(){0x0005FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APR1, Package(){
|
||||
/* Internal graphics - RS780 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, 0, 18 },
|
||||
Package(){0x0005FFFF, 1, 0, 19 },
|
||||
/* Package(){0x0005FFFF, 2, 0, 20 }, */
|
||||
/* Package(){0x0005FFFF, 3, 0, 17 }, */
|
||||
})
|
||||
|
||||
Name(PS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
|
||||
Name(APS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, 0, 16 },
|
||||
Package(){0x0000FFFF, 1, 0, 17 },
|
||||
Package(){0x0000FFFF, 2, 0, 18 },
|
||||
Package(){0x0000FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PS5, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 5 */
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
|
||||
Name(APS5, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 5 */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
|
||||
Name(PS6, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 6 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
|
||||
Name(APS6, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 6 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS7, Package(){
|
||||
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
|
||||
Name(APS7, Package(){
|
||||
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
|
||||
Package(){0x0000FFFF, 0, 0, 19 },
|
||||
Package(){0x0000FFFF, 1, 0, 16 },
|
||||
Package(){0x0000FFFF, 2, 0, 17 },
|
||||
Package(){0x0000FFFF, 3, 0, 18 },
|
||||
})
|
||||
Name(PS9, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 9 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
|
||||
Name(APS9, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 9 */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
Name(PSa, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
|
||||
Name(APSa, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PCIB, Package(){
|
||||
/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
|
||||
Package(){0x0005FFFF, 0, 0, 0x14 },
|
||||
Package(){0x0005FFFF, 1, 0, 0x15 },
|
||||
Package(){0x0005FFFF, 2, 0, 0x16 },
|
||||
Package(){0x0005FFFF, 3, 0, 0x17 },
|
||||
Package(){0x0006FFFF, 0, 0, 0x15 },
|
||||
Package(){0x0006FFFF, 1, 0, 0x16 },
|
||||
Package(){0x0006FFFF, 2, 0, 0x17 },
|
||||
Package(){0x0006FFFF, 3, 0, 0x14 },
|
||||
Package(){0x0007FFFF, 0, 0, 0x16 },
|
||||
Package(){0x0007FFFF, 1, 0, 0x17 },
|
||||
Package(){0x0007FFFF, 2, 0, 0x14 },
|
||||
Package(){0x0007FFFF, 3, 0, 0x15 },
|
||||
})
|
||||
}
|
||||
@@ -1,145 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
|
||||
/*
|
||||
Scope (_SB) {
|
||||
Device(PCI0) {
|
||||
Device(SATA) {
|
||||
Name(_ADR, 0x00110000)
|
||||
#include "sata.asl"
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
Name(STTM, Buffer(20) {
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x1f, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
/* Start by clearing the PhyRdyChg bits */
|
||||
Method(_INI) {
|
||||
\_GPE._L1F()
|
||||
}
|
||||
|
||||
Device(PMRY)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(PMST) {
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P0IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
}/* end of PMST */
|
||||
|
||||
Device(PSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P1IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of PSLA */
|
||||
} /* end of PMRY */
|
||||
|
||||
|
||||
Device(SEDY)
|
||||
{
|
||||
Name(_ADR, 1) /* IDE Scondary Channel */
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(SMST)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P2IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SMST */
|
||||
|
||||
Device(SSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P3IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SSLA */
|
||||
} /* end of SEDY */
|
||||
|
||||
/* SATA Hot Plug Support */
|
||||
Scope(\_GPE) {
|
||||
Method(_L1F,0x0,NotSerialized) {
|
||||
if (\_SB.P0PR) {
|
||||
if (LGreater(\_SB.P0IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P0PR)
|
||||
}
|
||||
|
||||
if (\_SB.P1PR) {
|
||||
if (LGreater(\_SB.P1IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P1PR)
|
||||
}
|
||||
|
||||
if (\_SB.P2PR) {
|
||||
if (LGreater(\_SB.P2IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P2PR)
|
||||
}
|
||||
|
||||
if (\_SB.P3PR) {
|
||||
if (LGreater(\_SB.P3IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P3PR)
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1,158 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
/*
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
|
||||
)
|
||||
{
|
||||
#include "usb.asl"
|
||||
}
|
||||
*/
|
||||
Method(UCOC, 0) {
|
||||
Sleep(20)
|
||||
Store(0x13,CMTI)
|
||||
Store(0,GPSL)
|
||||
}
|
||||
|
||||
/* USB Port 0 overcurrent uses Gpm 0 */
|
||||
If(LLessEqual(UOM0,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L13) {
|
||||
UCOC()
|
||||
if(LEqual(GPB0,PLC0)) {
|
||||
Not(PLC0,PLC0)
|
||||
Store(PLC0, \_SB.PT0D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 1 overcurrent uses Gpm 1 */
|
||||
If (LLessEqual(UOM1,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L14) {
|
||||
UCOC()
|
||||
if (LEqual(GPB1,PLC1)) {
|
||||
Not(PLC1,PLC1)
|
||||
Store(PLC1, \_SB.PT1D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 2 overcurrent uses Gpm 2 */
|
||||
If (LLessEqual(UOM2,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L15) {
|
||||
UCOC()
|
||||
if (LEqual(GPB2,PLC2)) {
|
||||
Not(PLC2,PLC2)
|
||||
Store(PLC2, \_SB.PT2D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 3 overcurrent uses Gpm 3 */
|
||||
If (LLessEqual(UOM3,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L16) {
|
||||
UCOC()
|
||||
if (LEqual(GPB3,PLC3)) {
|
||||
Not(PLC3,PLC3)
|
||||
Store(PLC3, \_SB.PT3D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 4 overcurrent uses Gpm 4 */
|
||||
If (LLessEqual(UOM4,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L19) {
|
||||
UCOC()
|
||||
if (LEqual(GPB4,PLC4)) {
|
||||
Not(PLC4,PLC4)
|
||||
Store(PLC4, \_SB.PT4D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 5 overcurrent uses Gpm 5 */
|
||||
If (LLessEqual(UOM5,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L1A) {
|
||||
UCOC()
|
||||
if (LEqual(GPB5,PLC5)) {
|
||||
Not(PLC5,PLC5)
|
||||
Store(PLC5, \_SB.PT5D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 6 overcurrent uses Gpm 6 */
|
||||
If (LLessEqual(UOM6,9)) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1C) { */
|
||||
Method (_L06) {
|
||||
UCOC()
|
||||
if (LEqual(GPB6,PLC6)) {
|
||||
Not(PLC6,PLC6)
|
||||
Store(PLC6, \_SB.PT6D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 7 overcurrent uses Gpm 7 */
|
||||
If (LLessEqual(UOM7,9)) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1D) { */
|
||||
Method (_L07) {
|
||||
UCOC()
|
||||
if (LEqual(GPB7,PLC7)) {
|
||||
Not(PLC7,PLC7)
|
||||
Store(PLC7, \_SB.PT7D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 8 overcurrent uses Gpm 8 */
|
||||
If (LLessEqual(UOM8,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L17) {
|
||||
if (LEqual(G8IS,PLC8)) {
|
||||
Not(PLC8,PLC8)
|
||||
Store(PLC8, \_SB.PT8D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 9 overcurrent uses Gpm 9 */
|
||||
If (LLessEqual(UOM9,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L0E) {
|
||||
if (LEqual(G9IS,0)) {
|
||||
Store(1,\_SB.PT9D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1,44 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
/* create all subtables for processors */
|
||||
current = acpi_create_madt_lapics(current);
|
||||
|
||||
/* Write SB700 IOAPIC, only one */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
|
||||
CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
|
||||
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 0, 2, 0);
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 9, 9, 0xF);
|
||||
/* 0: mean bus 0--->ISA */
|
||||
/* 0: PIC 0 */
|
||||
/* 2: APIC 2 */
|
||||
/* 5 mean: 0101 --> Edge-triggered, Active high */
|
||||
|
||||
/* create all subtables for processors */
|
||||
/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
|
||||
/* 1: LINT1 connect to NMI */
|
||||
|
||||
return current;
|
||||
}
|
||||
@@ -1,7 +0,0 @@
|
||||
Category: desktop
|
||||
Board URL: http://www.asus.com/Motherboards/AMD_AM2Plus/M4A785M/
|
||||
ROM package: DIP8
|
||||
ROM protocol: SPI
|
||||
ROM socketed: y
|
||||
Flashrom support: y
|
||||
Release year: 2009
|
||||
@@ -1,52 +0,0 @@
|
||||
entries
|
||||
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
#392 3 r 0 unused
|
||||
395 1 e 1 hw_scrubber
|
||||
396 1 e 1 interleave_chip_selects
|
||||
397 2 e 8 max_mem_clock
|
||||
399 1 e 2 multi_core
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
440 4 e 9 slow_cpu
|
||||
444 1 e 1 nmi
|
||||
445 1 e 1 gart
|
||||
456 1 e 1 ECC_memory
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
6 5 Notice
|
||||
6 6 Info
|
||||
6 7 Debug
|
||||
6 8 Spew
|
||||
8 0 400Mhz
|
||||
8 1 333Mhz
|
||||
8 2 266Mhz
|
||||
8 3 200Mhz
|
||||
9 0 off
|
||||
9 1 87.5%
|
||||
9 2 75.0%
|
||||
9 3 62.5%
|
||||
9 4 50.0%
|
||||
9 5 37.5%
|
||||
9 6 25.0%
|
||||
9 7 12.5%
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
@@ -1,106 +0,0 @@
|
||||
chip northbridge/amd/amdfam10/root_complex
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_AM3 #L1 and DDR2
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device domain 0 on
|
||||
subsystemid 0x1043 0x83a2 inherit
|
||||
chip northbridge/amd/amdfam10
|
||||
device pci 18.0 on # northbridge
|
||||
chip southbridge/amd/rs780
|
||||
device pci 0.0 on end # HT 0x9600
|
||||
device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
|
||||
device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603
|
||||
device pci 3.0 off end # PCIE P2P bridge 0x960b
|
||||
device pci 4.0 off end # PCIE P2P bridge 0x9604
|
||||
device pci 5.0 off end # PCIE P2P bridge 0x9605
|
||||
device pci 6.0 off end # PCIE P2P bridge 0x9606
|
||||
device pci 7.0 off end # PCIE P2P bridge 0x9607
|
||||
device pci 8.0 off end # NB/SB Link P2P bridge
|
||||
device pci 9.0 off end #
|
||||
device pci a.0 on end # bridge to RTL8111/8168B PCI Express Gigabit Ethernet
|
||||
register "gppsb_configuration" = "1" # Configuration B
|
||||
register "gpp_configuration" = "3" # Configuration D default
|
||||
register "port_enable" = "0x6fc"
|
||||
register "gfx_dev2_dev3" = "1"
|
||||
register "gfx_dual_slot" = "2"
|
||||
|
||||
register "gfx_lane_reversal" = "0"
|
||||
register "gfx_tmds" = "0"
|
||||
register "gfx_compliance" = "0"
|
||||
register "gfx_reconfiguration" = "1"
|
||||
register "gfx_link_width" = "0"
|
||||
end
|
||||
chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus
|
||||
device pci 11.0 on end # SATA
|
||||
device pci 12.0 on end # USB
|
||||
device pci 12.1 on end # USB
|
||||
device pci 12.2 on end # USB
|
||||
device pci 13.0 on end # USB
|
||||
device pci 13.1 on end # USB
|
||||
device pci 13.2 on end # USB
|
||||
device pci 14.0 on # SM
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
end # SM
|
||||
device pci 14.1 on end # IDE 0x439c
|
||||
device pci 14.2 on end # HDA 0x4383
|
||||
device pci 14.3 on # LPC 0x439d
|
||||
chip superio/ite/it8712f
|
||||
device pnp 2e.0 off end # Floppy
|
||||
device pnp 2e.1 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.2 off # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.3 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.4 off end # Environment Controller
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.6 on # Mouse
|
||||
irq 0x70 = 12
|
||||
end
|
||||
device pnp 2e.7 off # GPIO, must be closed for unresolved reason.
|
||||
end
|
||||
device pnp 2e.8 off # MIDI
|
||||
end
|
||||
device pnp 2e.9 off # GAME
|
||||
end
|
||||
device pnp 2e.a off end # CIR
|
||||
end #superio
|
||||
end #LPC
|
||||
device pci 14.4 on end # PCI to PCI Bridge [1002:4384]
|
||||
device pci 14.5 on end # USB 2
|
||||
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
|
||||
end #southbridge/amd/sb700
|
||||
end # device pci 18.0
|
||||
|
||||
device pci 18.0 on end
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
device pci 18.4 on end
|
||||
end # chip northbridge
|
||||
end #domain
|
||||
end # northbridge/amd/amdfam10/root_complex
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,44 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/pci.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <cpu/amd/multicore.h>
|
||||
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
/* Global variables for MB layouts and these will be shared by irqtable mptable
|
||||
* and acpi_tables busnum is default.
|
||||
*/
|
||||
u32 apicid_sb700;
|
||||
|
||||
void get_bus_conf(void)
|
||||
{
|
||||
u32 apicid_base;
|
||||
|
||||
get_default_pci1234(1);
|
||||
|
||||
sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
|
||||
|
||||
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
if (CONFIG(LOGICAL_CPUS))
|
||||
apicid_base = get_apicid_base(1);
|
||||
else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
apicid_sb700 = apicid_base + 0;
|
||||
}
|
||||
@@ -1,61 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Juhana Helovuo <juhe@iki.fi>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
static const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
|
||||
0x00, /* Interrupt router bus */
|
||||
(0x14 << 3) | 0x3, /* Interrupt router dev */
|
||||
0, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1002, /* Vendor */
|
||||
0x439d, /* Device */
|
||||
0, /* Miniport */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0x8, /* Checksum (has to be set to some value that
|
||||
* would give 0 after the sum of all bytes
|
||||
* for this structure (including checksum).
|
||||
*/
|
||||
{
|
||||
/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x01, (0x05 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
|
||||
{0x00, (0x02 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
|
||||
{0x00, (0x03 << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0},
|
||||
{0x00, (0x04 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
|
||||
{0x00, (0x05 << 3) | 0x0, {{0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}}, 0x0, 0x0},
|
||||
{0x00, (0x06 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
|
||||
{0x00, (0x07 << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0},
|
||||
{0x00, (0x09 << 3) | 0x0, {{0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}}, 0x0, 0x0},
|
||||
{0x00, (0x0a << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
|
||||
{0x02, (0x00 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0xa, 0x0},
|
||||
{0x00, (0x0b << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0},
|
||||
{0x00, (0x0c << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
|
||||
{0x00, (0x14 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
|
||||
{0x00, (0x12 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
|
||||
{0x00, (0x13 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
|
||||
{0x00, (0x11 << 3) | 0x0, {{0x0c, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
|
||||
{0x0a, (0x00 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
|
||||
{0x03, (0x05 << 3) | 0x0, {{0x0a, 0xdc90}, {0x0b, 0xdc90}, {0x0c, 0xdc90}, {0x0d, 0xdc90}}, 0xc, 0x0},
|
||||
{0x03, (0x06 << 3) | 0x0, {{0x0b, 0xdc90}, {0x0c, 0xdc90}, {0x0d, 0xdc90}, {0x0a, 0xdc90}}, 0xd, 0x0},
|
||||
}
|
||||
};
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
|
||||
}
|
||||
@@ -1,189 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <southbridge/amd/sb700/sb700.h>
|
||||
#include <southbridge/amd/sb700/smbus.h>
|
||||
#include <southbridge/amd/rs780/rs780.h>
|
||||
|
||||
#define ADT7461_ADDRESS 0x4C
|
||||
#define ARA_ADDRESS 0x0C /* Alert Response Address */
|
||||
|
||||
#define ADT7461_read_byte(address) \
|
||||
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
|
||||
#define ARA_read_byte(address) \
|
||||
do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
|
||||
#define ADT7461_write_byte(address, val) \
|
||||
do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
|
||||
|
||||
void set_pcie_dereset(void)
|
||||
{
|
||||
u8 byte;
|
||||
u16 word;
|
||||
struct device *sm_dev;
|
||||
/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
|
||||
/* set 0 to bit2 :disable GPM8 as AZ_RST output */
|
||||
byte = pm_ioread(0x8d);
|
||||
byte &= ~((1 << 1) | (1 << 2));
|
||||
pm_iowrite(0x8d, byte);
|
||||
|
||||
/* set the GPM8 and GPM9 output enable and the value to 1 */
|
||||
byte = pm_ioread(0x94);
|
||||
byte &= ~((1 << 2) | (1 << 3));
|
||||
byte |= ((1 << 0) | (1 << 1));
|
||||
pm_iowrite(0x94, byte);
|
||||
|
||||
/* set the GPIO65 output enable and the value is 1 */
|
||||
sm_dev = pcidev_on_root(0x14, 0);
|
||||
word = pci_read_config16(sm_dev, 0x7e);
|
||||
word |= (1 << 0);
|
||||
word &= ~(1 << 4);
|
||||
pci_write_config16(sm_dev, 0x7e, word);
|
||||
}
|
||||
|
||||
void set_pcie_reset(void)
|
||||
{
|
||||
u8 byte;
|
||||
u16 word;
|
||||
struct device *sm_dev;
|
||||
|
||||
/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
|
||||
/* set 0 to bit2 :disable GPM8 as AZ_RST output */
|
||||
byte = pm_ioread(0x8d);
|
||||
byte &= ~((1 << 1) | (1 << 2));
|
||||
pm_iowrite(0x8d, byte);
|
||||
|
||||
/* set the GPM8 and GPM9 output enable and the value to 0 */
|
||||
byte = pm_ioread(0x94);
|
||||
byte &= ~((1 << 2) | (1 << 3));
|
||||
byte &= ~((1 << 0) | (1 << 1));
|
||||
pm_iowrite(0x94, byte);
|
||||
|
||||
/* set the GPIO65 output enable and the value is 0 */
|
||||
sm_dev = pcidev_on_root(0x14, 0);
|
||||
word = pci_read_config16(sm_dev, 0x7e);
|
||||
word &= ~(1 << 0);
|
||||
word &= ~(1 << 4);
|
||||
pci_write_config16(sm_dev, 0x7e, word);
|
||||
}
|
||||
|
||||
/*
|
||||
* justify the dev3 is exist or not
|
||||
* NOTE: This just copied from AMD Tilapia code.
|
||||
* It is completely unknown it it will work at all for ASUS M4A785-M.
|
||||
*/
|
||||
int is_dev3_present(void)
|
||||
{
|
||||
u16 word;
|
||||
struct device *sm_dev;
|
||||
|
||||
/* access the smbus extended register */
|
||||
sm_dev = pcidev_on_root(0x14, 0);
|
||||
|
||||
/* put the GPIO68 output to tristate */
|
||||
word = pci_read_config16(sm_dev, 0x7e);
|
||||
word |= 1 << 6;
|
||||
pci_write_config16(sm_dev, 0x7e,word);
|
||||
|
||||
/* read the GPIO68 input status */
|
||||
word = pci_read_config16(sm_dev, 0x7e);
|
||||
|
||||
return !(word & (1 << 10));
|
||||
}
|
||||
|
||||
/*
|
||||
* set thermal config
|
||||
*/
|
||||
static void set_thermal_config(void)
|
||||
{
|
||||
u8 byte;
|
||||
u16 word;
|
||||
struct device *sm_dev;
|
||||
|
||||
/* set ADT 7461 */
|
||||
ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
|
||||
ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
|
||||
ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
|
||||
ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
|
||||
|
||||
ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
|
||||
ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
|
||||
|
||||
byte = ADT7461_read_byte(0x02); /* read status register to clear it */
|
||||
ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
|
||||
printk(BIOS_INFO, "Init adt7461 end, status 0x02 %02x\n", byte);
|
||||
|
||||
/* sb700 settings for thermal config */
|
||||
/* set SB700 GPIO 64 to GPIO with pull-up */
|
||||
byte = pm2_ioread(0x42);
|
||||
byte &= 0x3f;
|
||||
pm2_iowrite(0x42, byte);
|
||||
|
||||
/* set GPIO 64 to input */
|
||||
sm_dev = pcidev_on_root(0x14, 0);
|
||||
word = pci_read_config16(sm_dev, 0x56);
|
||||
word |= 1 << 7;
|
||||
pci_write_config16(sm_dev, 0x56, word);
|
||||
|
||||
/* set GPIO 64 internal pull-up */
|
||||
byte = pm2_ioread(0xf0);
|
||||
byte &= 0xee;
|
||||
pm2_iowrite(0xf0, byte);
|
||||
|
||||
/* set Talert to be active low */
|
||||
byte = pm_ioread(0x67);
|
||||
byte &= ~(1 << 5);
|
||||
pm_iowrite(0x67, byte);
|
||||
|
||||
/* set Talert to generate ACPI event */
|
||||
byte = pm_ioread(0x3c);
|
||||
byte &= 0xf3;
|
||||
pm_iowrite(0x3c, byte);
|
||||
|
||||
/* THERMTRIP pin */
|
||||
/* byte = pm_ioread(0x68);
|
||||
* byte |= 1 << 3;
|
||||
* pm_iowrite(0x68, byte);
|
||||
*
|
||||
* byte = pm_ioread(0x55);
|
||||
* byte |= 1 << 0;
|
||||
* pm_iowrite(0x55, byte);
|
||||
*
|
||||
* byte = pm_ioread(0x67);
|
||||
* byte &= ~(1 << 6);
|
||||
* pm_iowrite(0x67, byte);
|
||||
*/
|
||||
}
|
||||
|
||||
/*************************************************
|
||||
* enable the dedicated function in this board.
|
||||
* This function called early than rs780_enable.
|
||||
*************************************************/
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev);
|
||||
|
||||
set_pcie_dereset();
|
||||
/* get_ide_dma66(); */
|
||||
set_thermal_config();
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
@@ -1,101 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <stdint.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
extern u32 apicid_sb700;
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
{
|
||||
struct device *dev;
|
||||
u32 dword;
|
||||
u8 byte;
|
||||
|
||||
dev =
|
||||
dev_find_slot(pirq_router_bus,
|
||||
PCI_DEVFN(0x14, 0));
|
||||
if (dev) {
|
||||
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
|
||||
smp_write_ioapic(mc, apicid_sb700,
|
||||
0x11,(void *) dword);
|
||||
|
||||
/* Initialize interrupt mapping */
|
||||
/* aza */
|
||||
byte = pci_read_config8(dev, 0x63);
|
||||
byte &= 0xf8;
|
||||
byte |= 0; /* 0: INTA, ...., 7: INTH */
|
||||
pci_write_config8(dev, 0x63, byte);
|
||||
|
||||
/* SATA */
|
||||
dword = pci_read_config32(dev, 0xac);
|
||||
dword &= ~(7 << 26);
|
||||
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
|
||||
/* dword |= 1 << 22; PIC and APIC co exists */
|
||||
pci_write_config32(dev, 0xac, dword);
|
||||
|
||||
/*
|
||||
* 00:12.0: PROG SATA : INT F
|
||||
* 00:13.0: INTA USB_0
|
||||
* 00:13.1: INTB USB_1
|
||||
* 00:13.2: INTC USB_2
|
||||
* 00:13.3: INTD USB_3
|
||||
* 00:13.4: INTC USB_4
|
||||
* 00:13.5: INTD USB2
|
||||
* 00:14.1: INTA IDE
|
||||
* 00:14.2: Prog HDA : INT E
|
||||
* 00:14.5: INTB ACI
|
||||
* 00:14.6: INTB MCI
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
@@ -1,279 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#include <commonlib/helpers.h>
|
||||
#include <northbridge/amd/amdfam10/amdfam10.h>
|
||||
|
||||
void setup_mb_resource_map(void)
|
||||
{
|
||||
static const unsigned int register_values[] = {
|
||||
/* Careful set limit registers before base registers which contain the enables */
|
||||
/* DRAM Limit i Registers
|
||||
* F1:0x44 i = 0
|
||||
* F1:0x4C i = 1
|
||||
* F1:0x54 i = 2
|
||||
* F1:0x5C i = 3
|
||||
* F1:0x64 i = 4
|
||||
* F1:0x6C i = 5
|
||||
* F1:0x74 i = 6
|
||||
* F1:0x7C i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 3] Reserved
|
||||
* [10: 8] Interleave select
|
||||
* specifies the values of A[14:12] to use with interleave enable.
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Limit Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40 bit address
|
||||
* that define the end of the DRAM region.
|
||||
*/
|
||||
// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
|
||||
ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001,
|
||||
ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002,
|
||||
ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003,
|
||||
ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004,
|
||||
ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005,
|
||||
ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006,
|
||||
ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
|
||||
/* DRAM Base i Registers
|
||||
* F1:0x40 i = 0
|
||||
* F1:0x48 i = 1
|
||||
* F1:0x50 i = 2
|
||||
* F1:0x58 i = 3
|
||||
* F1:0x60 i = 4
|
||||
* F1:0x68 i = 5
|
||||
* F1:0x70 i = 6
|
||||
* F1:0x78 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 7: 2] Reserved
|
||||
* [10: 8] Interleave Enable
|
||||
* 000 = No interleave
|
||||
* 001 = Interleave on A[12] (2 nodes)
|
||||
* 010 = reserved
|
||||
* 011 = Interleave on A[12] and A[14] (4 nodes)
|
||||
* 100 = reserved
|
||||
* 101 = reserved
|
||||
* 110 = reserved
|
||||
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
|
||||
* [15:11] Reserved
|
||||
* [13:16] DRAM Base Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40-bit address
|
||||
* that define the start of the DRAM region.
|
||||
*/
|
||||
// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
|
||||
ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
* F1:0x8C i = 1
|
||||
* F1:0x94 i = 2
|
||||
* F1:0x9C i = 3
|
||||
* F1:0xA4 i = 4
|
||||
* F1:0xAC i = 5
|
||||
* F1:0xB4 i = 6
|
||||
* F1:0xBC i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Reserved
|
||||
* [ 6: 6] Reserved
|
||||
* [ 7: 7] Non-Posted
|
||||
* 0 = CPU writes may be posted
|
||||
* 1 = CPU writes must be non-posted
|
||||
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
|
||||
* This field defines the upp address bits of a 40-bit address that
|
||||
* defines the end of a memory-mapped I/O region n
|
||||
*/
|
||||
ADDRMAP_REG(0x84), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x8C), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x94), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x9C), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xA4), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xAC), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
|
||||
// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
|
||||
|
||||
/* Memory-Mapped I/O Base i Registers
|
||||
* F1:0x80 i = 0
|
||||
* F1:0x88 i = 1
|
||||
* F1:0x90 i = 2
|
||||
* F1:0x98 i = 3
|
||||
* F1:0xA0 i = 4
|
||||
* F1:0xA8 i = 5
|
||||
* F1:0xB0 i = 6
|
||||
* F1:0xB8 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Cpu Disable
|
||||
* 0 = Cpu can use this I/O range
|
||||
* 1 = Cpu requests do not use this I/O range
|
||||
* [ 3: 3] Lock
|
||||
* 0 = base/limit registers i are read/write
|
||||
* 1 = base/limit registers i are read-only
|
||||
* [ 7: 4] Reserved
|
||||
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
|
||||
* This field defines the upper address bits of a 40bit address
|
||||
* that defines the start of memory-mapped I/O region i
|
||||
*/
|
||||
ADDRMAP_REG(0x80), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x88), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x90), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x98), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
|
||||
// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
|
||||
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
* F1:0xCC i = 1
|
||||
* F1:0xD4 i = 2
|
||||
* F1:0xDC i = 3
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = reserved
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Limit Address i
|
||||
* This field defines the end of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000,
|
||||
ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000,
|
||||
ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000,
|
||||
ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
|
||||
|
||||
/* PCI I/O Base i Registers
|
||||
* F1:0xC0 i = 0
|
||||
* F1:0xC8 i = 1
|
||||
* F1:0xD0 i = 2
|
||||
* F1:0xD8 i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 3: 2] Reserved
|
||||
* [ 4: 4] VGA Enable
|
||||
* 0 = VGA matches Disabled
|
||||
* 1 = matches all address < 64K and where A[9:0] is in the
|
||||
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
|
||||
* [ 5: 5] ISA Enable
|
||||
* 0 = ISA matches Disabled
|
||||
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
|
||||
* from matching agains this base/limit pair
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Base i
|
||||
* This field defines the start of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003,
|
||||
ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000,
|
||||
ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000,
|
||||
ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
|
||||
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
* F1:0xE8 i = 2
|
||||
* F1:0xEC i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Device Number Compare Enable
|
||||
* 0 = The ranges are based on bus number
|
||||
* 1 = The ranges are ranges of devices on bus 0
|
||||
* [ 3: 3] Reserved
|
||||
* [ 6: 4] Destination Node
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 7] Reserved
|
||||
* [ 9: 8] Destination Link
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 - Reserved
|
||||
* [15:10] Reserved
|
||||
* [23:16] Bus Number Base i
|
||||
* This field defines the lowest bus number in configuration region i
|
||||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration regin i
|
||||
*/
|
||||
// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
|
||||
ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000,
|
||||
ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000,
|
||||
ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
|
||||
};
|
||||
|
||||
int max;
|
||||
max = ARRAY_SIZE(register_values);
|
||||
setup_resource_map(register_values, max);
|
||||
}
|
||||
@@ -1,236 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
//#define SYSTEM_TYPE 0 /* SERVER */
|
||||
#define SYSTEM_TYPE 1 /* DESKTOP */
|
||||
//#define SYSTEM_TYPE 2 /* MOBILE */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <console/console.h>
|
||||
#include <timestamp.h>
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include <superio/ite/common/ite.h>
|
||||
#include <superio/ite/it8712f/it8712f.h>
|
||||
#include <cpu/amd/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <cpu/amd/car.h>
|
||||
#include <southbridge/amd/common/reset.h>
|
||||
#include <southbridge/amd/sb700/sb700.h>
|
||||
#include <southbridge/amd/sb700/smbus.h>
|
||||
#include <northbridge/amd/amdfam10/raminit.h>
|
||||
#include <northbridge/amd/amdht/ht_wrapper.h>
|
||||
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
|
||||
#include <arch/early_variables.h>
|
||||
#include <cbmem.h>
|
||||
#include <spd.h>
|
||||
#include <southbridge/amd/rs780/rs780.h>
|
||||
|
||||
#include "cpu/amd/quadcore/quadcore.c"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
|
||||
#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
|
||||
|
||||
int spd_read_byte(unsigned int device, unsigned int address);
|
||||
|
||||
|
||||
int spd_read_byte(u32 device, u32 address)
|
||||
{
|
||||
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
|
||||
}
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
struct sys_info *sysinfo = get_sysinfo();
|
||||
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
|
||||
u32 bsp_apicid = 0, val;
|
||||
msr_t msr;
|
||||
|
||||
timestamp_init(timestamp_get());
|
||||
timestamp_add_now(TS_START_ROMSTAGE);
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
/* mov bsp to bus 0xff when > 8 nodes */
|
||||
set_bsp_node_CHtExtNodeCfgEn();
|
||||
enumerate_ht_chain();
|
||||
sb7xx_51xx_pci_port80();
|
||||
}
|
||||
|
||||
post_code(0x30);
|
||||
|
||||
if (bist == 0) {
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
|
||||
/* All cores run this but the BSP(node0,core0) is the only core that returns. */
|
||||
}
|
||||
|
||||
post_code(0x32);
|
||||
|
||||
enable_rs780_dev8();
|
||||
sb7xx_51xx_lpc_init();
|
||||
|
||||
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
ite_kill_watchdog(GPIO_DEV);
|
||||
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
// Load MPB
|
||||
val = cpuid_eax(1);
|
||||
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
|
||||
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
|
||||
printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
|
||||
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
|
||||
|
||||
/* Setup sysinfo defaults */
|
||||
set_sysinfo_in_ram(0);
|
||||
|
||||
update_microcode(val);
|
||||
|
||||
post_code(0x33);
|
||||
|
||||
cpuSetAMDMSR(0);
|
||||
post_code(0x34);
|
||||
|
||||
amd_ht_init(sysinfo);
|
||||
post_code(0x35);
|
||||
|
||||
/* Setup nodes PCI space and start core 0 AP init. */
|
||||
finalize_node_setup(sysinfo);
|
||||
|
||||
/* Setup any mainboard PCI settings etc. */
|
||||
setup_mb_resource_map();
|
||||
post_code(0x36);
|
||||
|
||||
/* wait for all the APs core0 started by finalize_node_setup. */
|
||||
/* FIXME: A bunch of cores are going to start output to serial at once.
|
||||
It would be nice to fixup prink spinlocks for ROM XIP mode.
|
||||
I think it could be done by putting the spinlock flag in the cache
|
||||
of the BSP located right after sysinfo.
|
||||
*/
|
||||
wait_all_core0_started();
|
||||
|
||||
#if CONFIG(LOGICAL_CPUS)
|
||||
/* Core0 on each node is configured. Now setup any additional cores. */
|
||||
printk(BIOS_DEBUG, "start_other_cores()\n");
|
||||
start_other_cores(bsp_apicid);
|
||||
post_code(0x37);
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
#endif
|
||||
|
||||
post_code(0x38);
|
||||
|
||||
/* run _early_setup before soft-reset. */
|
||||
rs780_early_setup();
|
||||
sb7xx_51xx_early_setup();
|
||||
|
||||
#if CONFIG(SET_FIDVID)
|
||||
msr = rdmsr(MSR_COFVID_STS);
|
||||
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
|
||||
|
||||
/* FIXME: The sb fid change may survive the warm reset and only
|
||||
need to be done once.*/
|
||||
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
|
||||
|
||||
post_code(0x39);
|
||||
|
||||
if (!warm_reset_detect(0)) { // BSP is node 0
|
||||
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
|
||||
} else {
|
||||
init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
|
||||
}
|
||||
|
||||
post_code(0x3A);
|
||||
|
||||
/* show final fid and vid */
|
||||
msr = rdmsr(MSR_COFVID_STS);
|
||||
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
|
||||
#endif
|
||||
|
||||
rs780_htinit();
|
||||
|
||||
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
|
||||
if (!warm_reset_detect(0)) {
|
||||
printk(BIOS_INFO, "...WARM RESET...\n\n\n");
|
||||
soft_reset();
|
||||
die("After soft_reset - shouldn't see this message!!!\n");
|
||||
}
|
||||
|
||||
post_code(0x3B);
|
||||
|
||||
/* It's the time to set ctrl in sysinfo now; */
|
||||
printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
|
||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
||||
|
||||
post_code(0x40);
|
||||
|
||||
raminit_amdmct(sysinfo);
|
||||
|
||||
cbmem_initialize_empty();
|
||||
post_code(0x41);
|
||||
|
||||
amdmct_cbmem_store_info(sysinfo);
|
||||
|
||||
sb7xx_51xx_before_pci_init();
|
||||
|
||||
post_code(0x42);
|
||||
}
|
||||
|
||||
/**
|
||||
* BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
|
||||
* Description:
|
||||
* This routine is called every time a non-coherent chain is processed.
|
||||
* BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
|
||||
* swap list. The first part of the list controls the BUID assignment and the
|
||||
* second part of the list provides the device to device linking. Device orientation
|
||||
* can be detected automatically, or explicitly. See documentation for more details.
|
||||
*
|
||||
* Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
|
||||
* based on each device's unit count.
|
||||
*
|
||||
* Parameters:
|
||||
* @param[in] node = The node on which this chain is located
|
||||
* @param[in] link = The link on the host for this chain
|
||||
* @param[out] List = supply a pointer to a list
|
||||
*/
|
||||
BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
|
||||
{
|
||||
#if !CONFIG(BOARD_ASUS_M4A785TM)
|
||||
static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
|
||||
/* If the BUID was adjusted in early_ht we need to do the manual override */
|
||||
if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
|
||||
printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
|
||||
if ((node == 0) && (link == 0)) { /* BSP SB link */
|
||||
*List = swaplist;
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
#else
|
||||
static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF};
|
||||
/* If the BUID was adjusted in early_ht we need to do the manual override */
|
||||
if ((node == 0) && (link == 0)) { /* BSP SB link */
|
||||
*List = swaplist;
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -1,56 +0,0 @@
|
||||
if BOARD_ASUS_M4A785TM
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS
|
||||
def_bool y
|
||||
select CPU_AMD_SOCKET_AM3
|
||||
select DIMM_DDR3
|
||||
select DIMM_REGISTERED
|
||||
select NORTHBRIDGE_AMD_AMDFAM10
|
||||
select SOUTHBRIDGE_AMD_RS780
|
||||
select SOUTHBRIDGE_AMD_SB700
|
||||
select SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
|
||||
select SUPERIO_ITE_IT8712F
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_CMOS_DEFAULT
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
select LIFT_BSP_APIC_ID
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_1024
|
||||
select ENABLE_APIC_EXT_ID
|
||||
select GFXUMA
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default asus/m4a785t-m
|
||||
|
||||
config APIC_ID_OFFSET
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "M4A785T-M"
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 8
|
||||
|
||||
config MAX_PHYSICAL_CPUS
|
||||
int
|
||||
default 2
|
||||
|
||||
config HT_CHAIN_END_UNITID_BASE
|
||||
hex
|
||||
default 0x1
|
||||
|
||||
config HT_CHAIN_UNITID_BASE
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 19
|
||||
|
||||
endif
|
||||
@@ -1,2 +0,0 @@
|
||||
config BOARD_ASUS_M4A785TM
|
||||
bool "M4A785T-M"
|
||||
@@ -1,16 +0,0 @@
|
||||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
|
||||
romstage-y += ../m4a785-m/resourcemap.c
|
||||
|
||||
ramstage-y += ../m4a785-m/get_bus_conf.c
|
||||
@@ -1,100 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* This file defines the processor and performance state capability
|
||||
* for each core in the system. It is included into the DSDT for each
|
||||
* core. It assumes that each core of the system has the same performance
|
||||
* characteristics.
|
||||
*/
|
||||
/*
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001)
|
||||
{
|
||||
Scope (\_PR) {
|
||||
Device (CPU0) {
|
||||
Name (_HID, "ACPI0007")
|
||||
Name (_UID, 0)
|
||||
#include "cpstate.asl"
|
||||
}
|
||||
Device (CPU1) {
|
||||
Name (_HID, "ACPI0007")
|
||||
Name (_UID, 1)
|
||||
#include "cpstate.asl"
|
||||
}
|
||||
Device (CPU2) {
|
||||
Name (_HID, "ACPI0007")
|
||||
Name (_UID, 2)
|
||||
#include "cpstate.asl"
|
||||
}
|
||||
Device (CPU3) {
|
||||
Name (_HID, "ACPI0007")
|
||||
Name (_UID, 3)
|
||||
#include "cpstate.asl"
|
||||
}
|
||||
}
|
||||
*/
|
||||
/* P-state support: The maximum number of P-states supported by the */
|
||||
/* CPUs we'll use is 6. */
|
||||
/* Get from AMI BIOS. */
|
||||
Name(_PSS, Package(){
|
||||
Package ()
|
||||
{
|
||||
0x00000BB8,
|
||||
0x000078D9,
|
||||
0x00000004,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000
|
||||
},
|
||||
|
||||
Package ()
|
||||
{
|
||||
0x000008FC,
|
||||
0x0000659A,
|
||||
0x00000004,
|
||||
0x00000004,
|
||||
0x00000001,
|
||||
0x00000001
|
||||
},
|
||||
|
||||
Package ()
|
||||
{
|
||||
0x00000708,
|
||||
0x000056BF,
|
||||
0x00000004,
|
||||
0x00000004,
|
||||
0x00000002,
|
||||
0x00000002
|
||||
},
|
||||
|
||||
Package ()
|
||||
{
|
||||
0x00000320,
|
||||
0x00001FA1,
|
||||
0x00000004,
|
||||
0x00000004,
|
||||
0x00000003,
|
||||
0x00000003
|
||||
}
|
||||
})
|
||||
|
||||
Name(_PCT, Package(){
|
||||
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
|
||||
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
|
||||
})
|
||||
|
||||
Method(_PPC, 0){
|
||||
Return(0)
|
||||
}
|
||||
@@ -1,240 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
Scope (_SB) {
|
||||
Device(PCI0) {
|
||||
Device(IDEC) {
|
||||
Name(_ADR, 0x00140001)
|
||||
#include "ide.asl"
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
/* Some timing tables */
|
||||
Name(UDTT, Package(){ /* Udma timing table */
|
||||
120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
|
||||
})
|
||||
|
||||
Name(MDTT, Package(){ /* MWDma timing table */
|
||||
480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
|
||||
})
|
||||
|
||||
Name(POTT, Package(){ /* Pio timing table */
|
||||
600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
|
||||
})
|
||||
|
||||
/* Some timing register value tables */
|
||||
Name(MDRT, Package(){ /* MWDma timing register table */
|
||||
0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
|
||||
})
|
||||
|
||||
Name(PORT, Package(){
|
||||
0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
|
||||
})
|
||||
|
||||
OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
|
||||
Field(ICRG, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
PPTS, 8, /* Primary PIO Slave Timing */
|
||||
PPTM, 8, /* Primary PIO Master Timing */
|
||||
OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
|
||||
PMTM, 8, /* Primary MWDMA Master Timing */
|
||||
OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
|
||||
OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
|
||||
PPSM, 4, /* Primary PIO slave Mode */
|
||||
OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
|
||||
OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
|
||||
PDSM, 4, /* Primary UltraDMA Mode */
|
||||
}
|
||||
|
||||
Method(GTTM, 1) /* get total time*/
|
||||
{
|
||||
Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
|
||||
Increment(Local0)
|
||||
Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
|
||||
Increment(Local1)
|
||||
Return(Multiply(30, Add(Local0, Local1)))
|
||||
}
|
||||
|
||||
Device(PRID)
|
||||
{
|
||||
Name (_ADR, Zero)
|
||||
Method(_GTM, 0)
|
||||
{
|
||||
NAME(OTBF, Buffer(20) { /* out buffer */
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
|
||||
CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
|
||||
CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
|
||||
CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
|
||||
CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
|
||||
|
||||
/* Just return if the channel is disabled */
|
||||
If(And(PPCR, 0x01)) { /* primary PIO control */
|
||||
Return(OTBF)
|
||||
}
|
||||
|
||||
/* Always tell them independent timing available and IOChannelReady used on both drives */
|
||||
Or(BFFG, 0x1A, BFFG)
|
||||
|
||||
Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
|
||||
Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
|
||||
|
||||
If(And(PDCR, 0x01)) { /* It's under UDMA mode */
|
||||
Or(BFFG, 0x01, BFFG)
|
||||
Store(DerefOf(Index(UDTT, PDMM)), DSD0)
|
||||
}
|
||||
Else {
|
||||
Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
|
||||
}
|
||||
|
||||
If(And(PDCR, 0x02)) { /* It's under UDMA mode */
|
||||
Or(BFFG, 0x04, BFFG)
|
||||
Store(DerefOf(Index(UDTT, PDSM)), DSD1)
|
||||
}
|
||||
Else {
|
||||
Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
|
||||
}
|
||||
|
||||
Return(OTBF) /* out buffer */
|
||||
} /* End Method(_GTM) */
|
||||
|
||||
Method(_STM, 3, NotSerialized)
|
||||
{
|
||||
NAME(INBF, Buffer(20) { /* in buffer */
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
|
||||
CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
|
||||
CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
|
||||
CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
|
||||
CreateDwordField(INBF, 16, BFFG) /*buffer flag */
|
||||
|
||||
Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
|
||||
Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
|
||||
Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
|
||||
|
||||
Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
|
||||
Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
|
||||
|
||||
If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
|
||||
Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 7, PDMM,)
|
||||
Or(PDCR, 0x01, PDCR)
|
||||
}
|
||||
Else {
|
||||
If(LNotEqual(DSD0, 0xFFFFFFFF)) {
|
||||
Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
|
||||
Store(DerefOf(Index(MDRT, Local0)), PMTM)
|
||||
}
|
||||
}
|
||||
|
||||
If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
|
||||
Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 7, PDSM,)
|
||||
Or(PDCR, 0x02, PDCR)
|
||||
}
|
||||
Else {
|
||||
If(LNotEqual(DSD1, 0xFFFFFFFF)) {
|
||||
Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
|
||||
Store(DerefOf(Index(MDRT, Local0)), PMTS)
|
||||
}
|
||||
}
|
||||
/* Return(INBF) */
|
||||
} /*End Method(_STM) */
|
||||
Device(MST)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_GTF) {
|
||||
Name(CMBF, Buffer(21) {
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
|
||||
})
|
||||
CreateByteField(CMBF, 1, POMD)
|
||||
CreateByteField(CMBF, 8, DMMD)
|
||||
CreateByteField(CMBF, 5, CMDA)
|
||||
CreateByteField(CMBF, 12, CMDB)
|
||||
CreateByteField(CMBF, 19, CMDC)
|
||||
|
||||
Store(0xA0, CMDA)
|
||||
Store(0xA0, CMDB)
|
||||
Store(0xA0, CMDC)
|
||||
|
||||
Or(PPMM, 0x08, POMD)
|
||||
|
||||
If(And(PDCR, 0x01)) {
|
||||
Or(PDMM, 0x40, DMMD)
|
||||
}
|
||||
Else {
|
||||
Store(Match
|
||||
(MDTT, MLE, GTTM(PMTM),
|
||||
MTR, 0, 0), Local0)
|
||||
If(LLess(Local0, 3)) {
|
||||
Or(0x20, Local0, DMMD)
|
||||
}
|
||||
}
|
||||
Return(CMBF)
|
||||
}
|
||||
} /* End Device(MST) */
|
||||
|
||||
Device(SLAV)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_GTF) {
|
||||
Name(CMBF, Buffer(21) {
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
|
||||
})
|
||||
CreateByteField(CMBF, 1, POMD)
|
||||
CreateByteField(CMBF, 8, DMMD)
|
||||
CreateByteField(CMBF, 5, CMDA)
|
||||
CreateByteField(CMBF, 12, CMDB)
|
||||
CreateByteField(CMBF, 19, CMDC)
|
||||
|
||||
Store(0xB0, CMDA)
|
||||
Store(0xB0, CMDB)
|
||||
Store(0xB0, CMDC)
|
||||
|
||||
Or(PPSM, 0x08, POMD)
|
||||
|
||||
If(And(PDCR, 0x02)) {
|
||||
Or(PDSM, 0x40, DMMD)
|
||||
}
|
||||
Else {
|
||||
Store(Match
|
||||
(MDTT, MLE, GTTM(PMTS),
|
||||
MTR, 0, 0), Local0)
|
||||
If(LLess(Local0, 3)) {
|
||||
Or(0x20, Local0, DMMD)
|
||||
}
|
||||
}
|
||||
Return(CMBF)
|
||||
}
|
||||
} /* End Device(SLAV) */
|
||||
}
|
||||
@@ -1,297 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
|
||||
)
|
||||
{
|
||||
#include "routing.asl"
|
||||
}
|
||||
*/
|
||||
|
||||
/* Routing is in System Bus scope */
|
||||
Scope(\_SB) {
|
||||
Name(PR0, Package(){
|
||||
/* NB devices */
|
||||
/* Bus 0, Dev 0 - RS780 Host Controller */
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
|
||||
Package(){0x0002FFFF, 0, INTC, 0 },
|
||||
Package(){0x0002FFFF, 1, INTD, 0 },
|
||||
Package(){0x0002FFFF, 2, INTA, 0 },
|
||||
Package(){0x0002FFFF, 3, INTB, 0 },
|
||||
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
|
||||
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||
Package(){0x0004FFFF, 0, INTA, 0 },
|
||||
Package(){0x0004FFFF, 1, INTB, 0 },
|
||||
Package(){0x0004FFFF, 2, INTC, 0 },
|
||||
Package(){0x0004FFFF, 3, INTD, 0 },
|
||||
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||
/* Package(){0x0005FFFF, 0, INTB, 0 }, */
|
||||
/* Package(){0x0005FFFF, 1, INTC, 0 }, */
|
||||
/* Package(){0x0005FFFF, 2, INTD, 0 }, */
|
||||
/* Package(){0x0005FFFF, 3, INTA, 0 }, */
|
||||
/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
|
||||
Package(){0x0006FFFF, 0, INTC, 0 },
|
||||
Package(){0x0006FFFF, 1, INTD, 0 },
|
||||
Package(){0x0006FFFF, 2, INTA, 0 },
|
||||
Package(){0x0006FFFF, 3, INTB, 0 },
|
||||
/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
|
||||
Package(){0x0007FFFF, 0, INTD, 0 },
|
||||
Package(){0x0007FFFF, 1, INTA, 0 },
|
||||
Package(){0x0007FFFF, 2, INTB, 0 },
|
||||
Package(){0x0007FFFF, 3, INTC, 0 },
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
/* SB devices */
|
||||
/* Bus 0, Dev 17 - SATA controller #2 */
|
||||
/* Bus 0, Dev 18 - SATA controller #1 */
|
||||
Package(){0x0011FFFF, 1, INTA, 0 },
|
||||
|
||||
/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
|
||||
Package(){0x0012FFFF, 0, INTA, 0 },
|
||||
Package(){0x0012FFFF, 1, INTB, 0 },
|
||||
Package(){0x0013FFFF, 0, INTA, 0 },
|
||||
Package(){0x0013FFFF, 1, INTB, 0 },
|
||||
Package(){0x0014FFFF, 2, INTA, 0 },
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */
|
||||
Package(){0x0014FFFF, 0, INTA, 0 },
|
||||
Package(){0x0014FFFF, 1, INTB, 0 },
|
||||
Package(){0x0014FFFF, 2, INTC, 0 },
|
||||
Package(){0x0014FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APR0, Package(){
|
||||
/* NB devices in APIC mode */
|
||||
/* Bus 0, Dev 0 - RS780 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
/* Package(){0x0001FFFF, 0, 0, 18 }, */
|
||||
/* Package(){0x0001FFFF, 1, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
|
||||
Package(){0x0002FFFF, 0, 0, 18 },
|
||||
/* Package(){0x0002FFFF, 1, 0, 19 }, */
|
||||
/* Package(){0x0002FFFF, 2, 0, 16 }, */
|
||||
/* Package(){0x0002FFFF, 3, 0, 17 }, */
|
||||
|
||||
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
|
||||
Package(){0x0003FFFF, 0, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||
Package(){0x0004FFFF, 0, 0, 16 },
|
||||
/* Package(){0x0004FFFF, 1, 0, 17 }, */
|
||||
/* Package(){0x0004FFFF, 2, 0, 18 }, */
|
||||
/* Package(){0x0004FFFF, 3, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||
/* Package(){0x0005FFFF, 0, 0, 17 }, */
|
||||
/* Package(){0x0005FFFF, 1, 0, 18 }, */
|
||||
/* Package(){0x0005FFFF, 2, 0, 19 }, */
|
||||
/* Package(){0x0005FFFF, 3, 0, 16 }, */
|
||||
|
||||
/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
|
||||
/* Package(){0x0006FFFF, 0, 0, 18 }, */
|
||||
/* Package(){0x0006FFFF, 1, 0, 19 }, */
|
||||
/* Package(){0x0006FFFF, 2, 0, 16 }, */
|
||||
/* Package(){0x0006FFFF, 3, 0, 17 }, */
|
||||
|
||||
/* Bus 0, Dev 7 - PCIe Bridge for network card */
|
||||
/* Package(){0x0007FFFF, 0, 0, 19 }, */
|
||||
/* Package(){0x0007FFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x0007FFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x0007FFFF, 3, 0, 18 }, */
|
||||
|
||||
/* Bus 0, Dev 9 - PCIe Bridge for network card */
|
||||
Package(){0x0009FFFF, 0, 0, 17 },
|
||||
/* Package(){0x0009FFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x0009FFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x0009FFFF, 3, 0, 18 }, */
|
||||
/* Bus 0, Dev A - PCIe Bridge for network card */
|
||||
Package(){0x000AFFFF, 0, 0, 18 },
|
||||
/* Package(){0x000AFFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x000AFFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x000AFFFF, 3, 0, 18 }, */
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
/* SB devices in APIC mode */
|
||||
/* Bus 0, Dev 17 - SATA controller #2 */
|
||||
/* Bus 0, Dev 18 - SATA controller #1 */
|
||||
Package(){0x0011FFFF, 0, 0, 22 },
|
||||
|
||||
/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
|
||||
Package(){0x0012FFFF, 0, 0, 16 },
|
||||
Package(){0x0012FFFF, 1, 0, 17 },
|
||||
Package(){0x0013FFFF, 0, 0, 18 },
|
||||
Package(){0x0013FFFF, 1, 0, 19 },
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
/* Package(){0x00130004, 2, 0, 18 }, */
|
||||
/* Package(){0x00130005, 3, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
Package(){0x0014FFFF, 1, 0, 17 },
|
||||
Package(){0x0014FFFF, 2, 0, 18 },
|
||||
Package(){0x0014FFFF, 3, 0, 19 },
|
||||
/* Package(){0x00140004, 2, 0, 18 }, */
|
||||
/* Package(){0x00140004, 3, 0, 19 }, */
|
||||
/* Package(){0x00140005, 1, 0, 17 }, */
|
||||
/* Package(){0x00140006, 1, 0, 17 }, */
|
||||
})
|
||||
|
||||
Name(PR1, Package(){
|
||||
/* Internal graphics - RS780 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, INTA, 0 },
|
||||
Package(){0x0005FFFF, 1, INTB, 0 },
|
||||
Package(){0x0005FFFF, 2, INTC, 0 },
|
||||
Package(){0x0005FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APR1, Package(){
|
||||
/* Internal graphics - RS780 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, 0, 18 },
|
||||
Package(){0x0005FFFF, 1, 0, 19 },
|
||||
/* Package(){0x0005FFFF, 2, 0, 20 }, */
|
||||
/* Package(){0x0005FFFF, 3, 0, 17 }, */
|
||||
})
|
||||
|
||||
Name(PS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
|
||||
Name(APS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, 0, 16 },
|
||||
Package(){0x0000FFFF, 1, 0, 17 },
|
||||
Package(){0x0000FFFF, 2, 0, 18 },
|
||||
Package(){0x0000FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PS5, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 5 */
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
|
||||
Name(APS5, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 5 */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
|
||||
Name(PS6, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 6 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
|
||||
Name(APS6, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 6 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS7, Package(){
|
||||
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
|
||||
Name(APS7, Package(){
|
||||
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
|
||||
Package(){0x0000FFFF, 0, 0, 19 },
|
||||
Package(){0x0000FFFF, 1, 0, 16 },
|
||||
Package(){0x0000FFFF, 2, 0, 17 },
|
||||
Package(){0x0000FFFF, 3, 0, 18 },
|
||||
})
|
||||
Name(PS9, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 9 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
|
||||
Name(APS9, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 9 */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
Name(PSa, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
|
||||
Name(APSa, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PCIB, Package(){
|
||||
/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
|
||||
Package(){0x0005FFFF, 0, 0, 0x14 },
|
||||
Package(){0x0005FFFF, 1, 0, 0x15 },
|
||||
Package(){0x0005FFFF, 2, 0, 0x16 },
|
||||
Package(){0x0005FFFF, 3, 0, 0x17 },
|
||||
Package(){0x0006FFFF, 0, 0, 0x15 },
|
||||
Package(){0x0006FFFF, 1, 0, 0x16 },
|
||||
Package(){0x0006FFFF, 2, 0, 0x17 },
|
||||
Package(){0x0006FFFF, 3, 0, 0x14 },
|
||||
Package(){0x0007FFFF, 0, 0, 0x16 },
|
||||
Package(){0x0007FFFF, 1, 0, 0x17 },
|
||||
Package(){0x0007FFFF, 2, 0, 0x14 },
|
||||
Package(){0x0007FFFF, 3, 0, 0x15 },
|
||||
})
|
||||
}
|
||||
@@ -1,145 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
|
||||
/*
|
||||
Scope (_SB) {
|
||||
Device(PCI0) {
|
||||
Device(SATA) {
|
||||
Name(_ADR, 0x00110000)
|
||||
#include "sata.asl"
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
Name(STTM, Buffer(20) {
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x1f, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
/* Start by clearing the PhyRdyChg bits */
|
||||
Method(_INI) {
|
||||
\_GPE._L1F()
|
||||
}
|
||||
|
||||
Device(PMRY)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(PMST) {
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P0IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
}/* end of PMST */
|
||||
|
||||
Device(PSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P1IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of PSLA */
|
||||
} /* end of PMRY */
|
||||
|
||||
|
||||
Device(SEDY)
|
||||
{
|
||||
Name(_ADR, 1) /* IDE Scondary Channel */
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(SMST)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P2IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SMST */
|
||||
|
||||
Device(SSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P3IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SSLA */
|
||||
} /* end of SEDY */
|
||||
|
||||
/* SATA Hot Plug Support */
|
||||
Scope(\_GPE) {
|
||||
Method(_L1F,0x0,NotSerialized) {
|
||||
if (\_SB.P0PR) {
|
||||
if (LGreater(\_SB.P0IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P0PR)
|
||||
}
|
||||
|
||||
if (\_SB.P1PR) {
|
||||
if (LGreater(\_SB.P1IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P1PR)
|
||||
}
|
||||
|
||||
if (\_SB.P2PR) {
|
||||
if (LGreater(\_SB.P2IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P2PR)
|
||||
}
|
||||
|
||||
if (\_SB.P3PR) {
|
||||
if (LGreater(\_SB.P3IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P3PR)
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1,158 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
/*
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
|
||||
)
|
||||
{
|
||||
#include "usb.asl"
|
||||
}
|
||||
*/
|
||||
Method(UCOC, 0) {
|
||||
Sleep(20)
|
||||
Store(0x13,CMTI)
|
||||
Store(0,GPSL)
|
||||
}
|
||||
|
||||
/* USB Port 0 overcurrent uses Gpm 0 */
|
||||
If(LLessEqual(UOM0,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L13) {
|
||||
UCOC()
|
||||
if(LEqual(GPB0,PLC0)) {
|
||||
Not(PLC0,PLC0)
|
||||
Store(PLC0, \_SB.PT0D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 1 overcurrent uses Gpm 1 */
|
||||
If (LLessEqual(UOM1,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L14) {
|
||||
UCOC()
|
||||
if (LEqual(GPB1,PLC1)) {
|
||||
Not(PLC1,PLC1)
|
||||
Store(PLC1, \_SB.PT1D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 2 overcurrent uses Gpm 2 */
|
||||
If (LLessEqual(UOM2,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L15) {
|
||||
UCOC()
|
||||
if (LEqual(GPB2,PLC2)) {
|
||||
Not(PLC2,PLC2)
|
||||
Store(PLC2, \_SB.PT2D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 3 overcurrent uses Gpm 3 */
|
||||
If (LLessEqual(UOM3,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L16) {
|
||||
UCOC()
|
||||
if (LEqual(GPB3,PLC3)) {
|
||||
Not(PLC3,PLC3)
|
||||
Store(PLC3, \_SB.PT3D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 4 overcurrent uses Gpm 4 */
|
||||
If (LLessEqual(UOM4,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L19) {
|
||||
UCOC()
|
||||
if (LEqual(GPB4,PLC4)) {
|
||||
Not(PLC4,PLC4)
|
||||
Store(PLC4, \_SB.PT4D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 5 overcurrent uses Gpm 5 */
|
||||
If (LLessEqual(UOM5,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L1A) {
|
||||
UCOC()
|
||||
if (LEqual(GPB5,PLC5)) {
|
||||
Not(PLC5,PLC5)
|
||||
Store(PLC5, \_SB.PT5D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 6 overcurrent uses Gpm 6 */
|
||||
If (LLessEqual(UOM6,9)) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1C) { */
|
||||
Method (_L06) {
|
||||
UCOC()
|
||||
if (LEqual(GPB6,PLC6)) {
|
||||
Not(PLC6,PLC6)
|
||||
Store(PLC6, \_SB.PT6D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 7 overcurrent uses Gpm 7 */
|
||||
If (LLessEqual(UOM7,9)) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1D) { */
|
||||
Method (_L07) {
|
||||
UCOC()
|
||||
if (LEqual(GPB7,PLC7)) {
|
||||
Not(PLC7,PLC7)
|
||||
Store(PLC7, \_SB.PT7D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 8 overcurrent uses Gpm 8 */
|
||||
If (LLessEqual(UOM8,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L17) {
|
||||
if (LEqual(G8IS,PLC8)) {
|
||||
Not(PLC8,PLC8)
|
||||
Store(PLC8, \_SB.PT8D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 9 overcurrent uses Gpm 9 */
|
||||
If (LLessEqual(UOM9,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L0E) {
|
||||
if (LEqual(G9IS,0)) {
|
||||
Store(1,\_SB.PT9D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1,17 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "../m4a785-m/acpi_tables.c"
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user