mb/*/*: Drop AMDFAM10 mainboards
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: Ic00ca18de3d73a17041a3a2839307149ad7902b2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36961 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
committed by
Kyösti Mälkki
Kyösti Mälkki
parent
ad983eeec7
commit
f2e42c4a8e
@@ -1,30 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2011 Advanced Micro Devices, Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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if VENDOR_ADVANSUS
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choice
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prompt "Mainboard model"
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source "src/mainboard/advansus/*/Kconfig.name"
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endchoice
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source "src/mainboard/advansus/*/Kconfig"
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config MAINBOARD_VENDOR
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string
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default "Advansus"
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endif # VENDOR_ADVANSUS
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@@ -1,2 +0,0 @@
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config VENDOR_ADVANSUS
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bool "Advansus"
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@@ -1,65 +0,0 @@
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if BOARD_ADVANSUS_A785E_I
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select CPU_AMD_SOCKET_ASB2
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select DIMM_DDR3
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select DIMM_REGISTERED
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select NORTHBRIDGE_AMD_AMDFAM10
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select SOUTHBRIDGE_AMD_RS780
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select SOUTHBRIDGE_AMD_SB800
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select SUPERIO_WINBOND_W83627HF #COM1, COM2
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#select SUPERIO_FINTEK_F81216AD #COM3, COM4
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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select SB_HT_CHAIN_UNITID_OFFSET_ONLY
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select LIFT_BSP_APIC_ID
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select HAVE_MP_TABLE
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_1024
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select ENABLE_APIC_EXT_ID
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select GFXUMA
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select HAVE_DEBUG_CAR
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select SET_FIDVID
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config MAINBOARD_DIR
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string
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default advansus/a785e-i
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config APIC_ID_OFFSET
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hex
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default 0x0
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config MAINBOARD_PART_NUMBER
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string
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default "A785E-I"
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config HW_MEM_HOLE_SIZEK
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hex
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default 0x100000
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config MAX_CPUS
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int
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default 8
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config MAX_PHYSICAL_CPUS
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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config HT_CHAIN_UNITID_BASE
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hex
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default 0x0
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config IRQ_SLOT_COUNT
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int
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default 11
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config VGA_BIOS_ID
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string
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default "1002,9712"
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endif #BOARD_ADVANSUS_A785E_I
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@@ -1,2 +0,0 @@
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config BOARD_ADVANSUS_A785E_I
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bool "A785E-I"
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@@ -1,16 +0,0 @@
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#
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# This file is part of the coreboot project.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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romstage-y += resourcemap.c
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ramstage-y += get_bus_conf.c
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@@ -1,80 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* This file defines the processor and performance state capability
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* for each core in the system. It is included into the DSDT for each
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* core. It assumes that each core of the system has the same performance
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* characteristics.
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*/
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/*
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#include <arch/acpi.h>
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DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001)
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{
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Scope (\_PR) {
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Device (CPU0) {
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Name (_HID, "ACPI0007")
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Name (_UID, 0)
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#include "cpstate.asl"
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}
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Device (CPU1) {
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Name (_HID, "ACPI0007")
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Name (_UID, 1)
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#include "cpstate.asl"
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}
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Device (CPU2) {
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Name (_HID, "ACPI0007")
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Name (_UID, 2)
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#include "cpstate.asl"
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}
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Device (CPU3) {
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Name (_HID, "ACPI0007")
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Name (_UID, 3)
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#include "cpstate.asl"
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}
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}
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*/
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/* P-state support: The maximum number of P-states supported by the */
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/* CPUs we'll use is 6. */
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/* Get from AMI BIOS. */
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Name(_PSS, Package(){
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Package ()
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{
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0x00000AF0,
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0x0000BF81,
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0x00000002,
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0x00000002,
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0x00000000,
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0x00000000
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},
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Package ()
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{
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0x00000578,
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0x000076F2,
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0x00000002,
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0x00000002,
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0x00000001,
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0x00000001
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}
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})
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Name(_PCT, Package(){
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ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
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ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
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})
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Method(_PPC, 0){
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Return(0)
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}
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@@ -1,395 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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||||
* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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||||
*/
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/*
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#include <arch/acpi.h>
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DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
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)
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{
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#include "routing.asl"
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}
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*/
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/* Routing is in System Bus scope */
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Scope(\_SB) {
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Name(PR0, Package(){
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/* NB devices */
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/* Bus 0, Dev 0 - RS780 Host Controller */
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, INTC, 0 },
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Package(){0x0002FFFF, 1, INTD, 0 },
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Package(){0x0002FFFF, 2, INTA, 0 },
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Package(){0x0002FFFF, 3, INTB, 0 },
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/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
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/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
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Package(){0x0004FFFF, 0, INTA, 0 },
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Package(){0x0004FFFF, 1, INTB, 0 },
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Package(){0x0004FFFF, 2, INTC, 0 },
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Package(){0x0004FFFF, 3, INTD, 0 },
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/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
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/* Package(){0x0005FFFF, 0, INTB, 0 }, */
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/* Package(){0x0005FFFF, 1, INTC, 0 }, */
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/* Package(){0x0005FFFF, 2, INTD, 0 }, */
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/* Package(){0x0005FFFF, 3, INTA, 0 }, */
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/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
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Package(){0x0006FFFF, 0, INTC, 0 },
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Package(){0x0006FFFF, 1, INTD, 0 },
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Package(){0x0006FFFF, 2, INTA, 0 },
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Package(){0x0006FFFF, 3, INTB, 0 },
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/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
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Package(){0x0007FFFF, 0, INTD, 0 },
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Package(){0x0007FFFF, 1, INTA, 0 },
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Package(){0x0007FFFF, 2, INTB, 0 },
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Package(){0x0007FFFF, 3, INTC, 0 },
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|
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Package(){0x0009FFFF, 0, INTB, 0 },
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Package(){0x0009FFFF, 1, INTC, 0 },
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Package(){0x0009FFFF, 2, INTD, 0 },
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Package(){0x0009FFFF, 3, INTA, 0 },
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|
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Package(){0x000AFFFF, 0, INTC, 0 },
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Package(){0x000AFFFF, 1, INTD, 0 },
|
||||
Package(){0x000AFFFF, 2, INTA, 0 },
|
||||
Package(){0x000AFFFF, 3, INTB, 0 },
|
||||
|
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Package(){0x000BFFFF, 0, INTD, 0 },
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Package(){0x000BFFFF, 1, INTA, 0 },
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||||
Package(){0x000BFFFF, 2, INTB, 0 },
|
||||
Package(){0x000BFFFF, 3, INTC, 0 },
|
||||
|
||||
Package(){0x000CFFFF, 0, INTA, 0 },
|
||||
Package(){0x000CFFFF, 1, INTB, 0 },
|
||||
Package(){0x000CFFFF, 2, INTC, 0 },
|
||||
Package(){0x000CFFFF, 3, INTD, 0 },
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||||
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
/* SB devices */
|
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/* Bus 0, Dev 17 - SATA controller #2 */
|
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/* Bus 0, Dev 18 - SATA controller #1 */
|
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Package(){0x0011FFFF, 0, INTD, 0 },
|
||||
|
||||
/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
|
||||
* EHCI, dev 18, 19 func 2 */
|
||||
Package(){0x0012FFFF, 0, INTC, 0 },
|
||||
Package(){0x0012FFFF, 1, INTB, 0 },
|
||||
|
||||
Package(){0x0013FFFF, 0, INTC, 0 },
|
||||
Package(){0x0013FFFF, 1, INTB, 0 },
|
||||
|
||||
Package(){0x0016FFFF, 0, INTC, 0 },
|
||||
Package(){0x0016FFFF, 1, INTB, 0 },
|
||||
|
||||
/* Package(){0x0014FFFF, 1, INTA, 0 }, */
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
|
||||
Package(){0x0014FFFF, 0, INTA, 0 },
|
||||
Package(){0x0014FFFF, 1, INTB, 0 },
|
||||
Package(){0x0014FFFF, 2, INTC, 0 },
|
||||
Package(){0x0014FFFF, 3, INTD, 0 },
|
||||
|
||||
Package(){0x0015FFFF, 0, INTA, 0 },
|
||||
Package(){0x0015FFFF, 1, INTB, 0 },
|
||||
Package(){0x0015FFFF, 2, INTC, 0 },
|
||||
Package(){0x0015FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APR0, Package(){
|
||||
/* NB devices in APIC mode */
|
||||
/* Bus 0, Dev 0 - RS780 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
Package(){0x0001FFFF, 0, 0, 18 },
|
||||
Package(){0x0001FFFF, 1, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
|
||||
Package(){0x0002FFFF, 0, 0, 18 },
|
||||
/* Package(){0x0002FFFF, 1, 0, 19 }, */
|
||||
/* Package(){0x0002FFFF, 2, 0, 16 }, */
|
||||
/* Package(){0x0002FFFF, 3, 0, 17 }, */
|
||||
|
||||
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
|
||||
Package(){0x0003FFFF, 0, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||
Package(){0x0004FFFF, 0, 0, 16 },
|
||||
/* Package(){0x0004FFFF, 1, 0, 17 }, */
|
||||
/* Package(){0x0004FFFF, 2, 0, 18 }, */
|
||||
/* Package(){0x0004FFFF, 3, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||
/* Package(){0x0005FFFF, 0, 0, 17 }, */
|
||||
/* Package(){0x0005FFFF, 1, 0, 18 }, */
|
||||
/* Package(){0x0005FFFF, 2, 0, 19 }, */
|
||||
/* Package(){0x0005FFFF, 3, 0, 16 }, */
|
||||
|
||||
/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
|
||||
/* Package(){0x0006FFFF, 0, 0, 18 }, */
|
||||
/* Package(){0x0006FFFF, 1, 0, 19 }, */
|
||||
/* Package(){0x0006FFFF, 2, 0, 16 }, */
|
||||
/* Package(){0x0006FFFF, 3, 0, 17 }, */
|
||||
|
||||
/* Bus 0, Dev 7 - PCIe Bridge for network card */
|
||||
/* Package(){0x0007FFFF, 0, 0, 19 }, */
|
||||
/* Package(){0x0007FFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x0007FFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x0007FFFF, 3, 0, 18 }, */
|
||||
|
||||
/* Bus 0, Dev 9 - PCIe Bridge for network card */
|
||||
Package(){0x0009FFFF, 0, 0, 17 },
|
||||
/* Package(){0x0009FFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x0009FFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x0009FFFF, 3, 0, 18 }, */
|
||||
/* Bus 0, Dev A - PCIe Bridge for network card */
|
||||
Package(){0x000AFFFF, 0, 0, 18 },
|
||||
/* Package(){0x000AFFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x000AFFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x000AFFFF, 3, 0, 18 }, */
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
/* SB devices in APIC mode */
|
||||
/* Bus 0, Dev 17 - SATA controller #2 */
|
||||
/* Bus 0, Dev 18 - SATA controller #1 */
|
||||
Package(){0x0011FFFF, 0, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
|
||||
* EHCI, dev 18, 19 func 2 */
|
||||
Package(){0x0012FFFF, 0, 0, 18 },
|
||||
Package(){0x0012FFFF, 1, 0, 17 },
|
||||
/* Package(){0x0012FFFF, 2, 0, 18 }, */
|
||||
|
||||
Package(){0x0013FFFF, 0, 0, 18 },
|
||||
Package(){0x0013FFFF, 1, 0, 17 },
|
||||
/* Package(){0x0013FFFF, 2, 0, 16 }, */
|
||||
|
||||
/* Package(){0x00140000, 0, 0, 16 }, */
|
||||
|
||||
Package(){0x0016FFFF, 0, 0, 18 },
|
||||
Package(){0x0016FFFF, 1, 0, 17 },
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
Package(){0x0014FFFF, 1, 0, 17 },
|
||||
Package(){0x0014FFFF, 2, 0, 18 },
|
||||
Package(){0x0014FFFF, 3, 0, 19 },
|
||||
/* Package(){0x00140004, 2, 0, 18 }, */
|
||||
/* Package(){0x00140004, 3, 0, 19 }, */
|
||||
/* Package(){0x00140005, 1, 0, 17 }, */
|
||||
/* Package(){0x00140006, 1, 0, 17 }, */
|
||||
|
||||
/* TODO: pcie */
|
||||
Package(){0x0015FFFF, 0, 0, 16 },
|
||||
Package(){0x0015FFFF, 1, 0, 17 },
|
||||
Package(){0x0015FFFF, 2, 0, 18 },
|
||||
Package(){0x0015FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PR1, Package(){
|
||||
/* Internal graphics - RS780 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, INTA, 0 },
|
||||
Package(){0x0005FFFF, 1, INTB, 0 },
|
||||
Package(){0x0005FFFF, 2, INTC, 0 },
|
||||
Package(){0x0005FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APR1, Package(){
|
||||
/* Internal graphics - RS780 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, 0, 18 },
|
||||
Package(){0x0005FFFF, 1, 0, 19 },
|
||||
/* Package(){0x0005FFFF, 2, 0, 20 }, */
|
||||
/* Package(){0x0005FFFF, 3, 0, 17 }, */
|
||||
})
|
||||
|
||||
Name(PS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, 0, 16 },
|
||||
Package(){0x0000FFFF, 1, 0, 17 },
|
||||
Package(){0x0000FFFF, 2, 0, 18 },
|
||||
Package(){0x0000FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PS5, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 5 */
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
Name(APS5, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 5 */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
|
||||
Name(PS6, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 6 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APS6, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 6 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS7, Package(){
|
||||
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
Name(APS7, Package(){
|
||||
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
|
||||
Package(){0x0000FFFF, 0, 0, 19 },
|
||||
Package(){0x0000FFFF, 1, 0, 16 },
|
||||
Package(){0x0000FFFF, 2, 0, 17 },
|
||||
Package(){0x0000FFFF, 3, 0, 18 },
|
||||
})
|
||||
|
||||
Name(PS9, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 9 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
Name(APS9, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 9 */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
|
||||
Name(PSa, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
Name(APSa, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PE0, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APE0, Package(){
|
||||
/* PCIe slot - Hooked to PCIe */
|
||||
Package(){0x0000FFFF, 0, 0, 16 },
|
||||
Package(){0x0000FFFF, 1, 0, 17 },
|
||||
Package(){0x0000FFFF, 2, 0, 18 },
|
||||
Package(){0x0000FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PE1, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
Name(APE1, Package(){
|
||||
/* PCIe slot - Hooked to PCIe */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
|
||||
Name(PE2, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APE2, Package(){
|
||||
/* PCIe slot - Hooked to PCIe */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PE3, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
Name(APE3, Package(){
|
||||
/* PCIe slot - Hooked to PCIe */
|
||||
Package(){0x0000FFFF, 0, 0, 19 },
|
||||
Package(){0x0000FFFF, 1, 0, 16 },
|
||||
Package(){0x0000FFFF, 2, 0, 17 },
|
||||
Package(){0x0000FFFF, 3, 0, 18 },
|
||||
})
|
||||
|
||||
Name(PCIB, Package(){
|
||||
/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
|
||||
Package(){0x0005FFFF, 0, 0, 0x14 },
|
||||
Package(){0x0005FFFF, 1, 0, 0x15 },
|
||||
Package(){0x0005FFFF, 2, 0, 0x16 },
|
||||
Package(){0x0005FFFF, 3, 0, 0x17 },
|
||||
Package(){0x0006FFFF, 0, 0, 0x15 },
|
||||
Package(){0x0006FFFF, 1, 0, 0x16 },
|
||||
Package(){0x0006FFFF, 2, 0, 0x17 },
|
||||
Package(){0x0006FFFF, 3, 0, 0x14 },
|
||||
Package(){0x0007FFFF, 0, 0, 0x16 },
|
||||
Package(){0x0007FFFF, 1, 0, 0x17 },
|
||||
Package(){0x0007FFFF, 2, 0, 0x14 },
|
||||
Package(){0x0007FFFF, 3, 0, 0x15 },
|
||||
})
|
||||
}
|
||||
@@ -1,145 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
|
||||
/*
|
||||
Scope (_SB) {
|
||||
Device(PCI0) {
|
||||
Device(SATA) {
|
||||
Name(_ADR, 0x00110000)
|
||||
#include "sata.asl"
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
Name(STTM, Buffer(20) {
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x1f, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
/* Start by clearing the PhyRdyChg bits */
|
||||
Method(_INI) {
|
||||
\_GPE._L1F()
|
||||
}
|
||||
|
||||
Device(PMRY)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(PMST) {
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P0IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
}/* end of PMST */
|
||||
|
||||
Device(PSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P1IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of PSLA */
|
||||
} /* end of PMRY */
|
||||
|
||||
|
||||
Device(SEDY)
|
||||
{
|
||||
Name(_ADR, 1) /* IDE Scondary Channel */
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(SMST)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P2IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SMST */
|
||||
|
||||
Device(SSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P3IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SSLA */
|
||||
} /* end of SEDY */
|
||||
|
||||
/* SATA Hot Plug Support */
|
||||
Scope(\_GPE) {
|
||||
Method(_L1F,0x0,NotSerialized) {
|
||||
if (\_SB.P0PR) {
|
||||
if (LGreater(\_SB.P0IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P0PR)
|
||||
}
|
||||
|
||||
if (\_SB.P1PR) {
|
||||
if (LGreater(\_SB.P1IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P1PR)
|
||||
}
|
||||
|
||||
if (\_SB.P2PR) {
|
||||
if (LGreater(\_SB.P2IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P2PR)
|
||||
}
|
||||
|
||||
if (\_SB.P3PR) {
|
||||
if (LGreater(\_SB.P3IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P3PR)
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1,158 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
/*
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
|
||||
)
|
||||
{
|
||||
#include "usb.asl"
|
||||
}
|
||||
*/
|
||||
Method(UCOC, 0) {
|
||||
Sleep(20)
|
||||
Store(0x13,CMTI)
|
||||
Store(0,GPSL)
|
||||
}
|
||||
|
||||
/* USB Port 0 overcurrent uses Gpm 0 */
|
||||
If(LLessEqual(UOM0,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L13) {
|
||||
UCOC()
|
||||
if(LEqual(GPB0,PLC0)) {
|
||||
Not(PLC0,PLC0)
|
||||
Store(PLC0, \_SB.PT0D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 1 overcurrent uses Gpm 1 */
|
||||
If (LLessEqual(UOM1,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L14) {
|
||||
UCOC()
|
||||
if (LEqual(GPB1,PLC1)) {
|
||||
Not(PLC1,PLC1)
|
||||
Store(PLC1, \_SB.PT1D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 2 overcurrent uses Gpm 2 */
|
||||
If (LLessEqual(UOM2,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L15) {
|
||||
UCOC()
|
||||
if (LEqual(GPB2,PLC2)) {
|
||||
Not(PLC2,PLC2)
|
||||
Store(PLC2, \_SB.PT2D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 3 overcurrent uses Gpm 3 */
|
||||
If (LLessEqual(UOM3,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L16) {
|
||||
UCOC()
|
||||
if (LEqual(GPB3,PLC3)) {
|
||||
Not(PLC3,PLC3)
|
||||
Store(PLC3, \_SB.PT3D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 4 overcurrent uses Gpm 4 */
|
||||
If (LLessEqual(UOM4,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L19) {
|
||||
UCOC()
|
||||
if (LEqual(GPB4,PLC4)) {
|
||||
Not(PLC4,PLC4)
|
||||
Store(PLC4, \_SB.PT4D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 5 overcurrent uses Gpm 5 */
|
||||
If (LLessEqual(UOM5,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L1A) {
|
||||
UCOC()
|
||||
if (LEqual(GPB5,PLC5)) {
|
||||
Not(PLC5,PLC5)
|
||||
Store(PLC5, \_SB.PT5D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 6 overcurrent uses Gpm 6 */
|
||||
If (LLessEqual(UOM6,9)) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1C) { */
|
||||
Method (_L06) {
|
||||
UCOC()
|
||||
if (LEqual(GPB6,PLC6)) {
|
||||
Not(PLC6,PLC6)
|
||||
Store(PLC6, \_SB.PT6D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 7 overcurrent uses Gpm 7 */
|
||||
If (LLessEqual(UOM7,9)) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1D) { */
|
||||
Method (_L07) {
|
||||
UCOC()
|
||||
if (LEqual(GPB7,PLC7)) {
|
||||
Not(PLC7,PLC7)
|
||||
Store(PLC7, \_SB.PT7D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 8 overcurrent uses Gpm 8 */
|
||||
If (LLessEqual(UOM8,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L17) {
|
||||
if (LEqual(G8IS,PLC8)) {
|
||||
Not(PLC8,PLC8)
|
||||
Store(PLC8, \_SB.PT8D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 9 overcurrent uses Gpm 9 */
|
||||
If (LLessEqual(UOM9,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L0E) {
|
||||
if (LEqual(G9IS,0)) {
|
||||
Store(1,\_SB.PT9D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1,44 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
/* create all subtables for processors */
|
||||
current = acpi_create_madt_lapics(current);
|
||||
|
||||
/* Write SB800 IOAPIC, only one */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
|
||||
IO_APIC_ADDR, 0);
|
||||
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 0, 2, 0);
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 9, 9, 0xF);
|
||||
/* 0: mean bus 0--->ISA */
|
||||
/* 0: PIC 0 */
|
||||
/* 2: APIC 2 */
|
||||
/* 5 mean: 0101 --> Edge-triggered, Active high */
|
||||
|
||||
/* create all subtables for processors */
|
||||
/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
|
||||
/* 1: LINT1 connect to NMI */
|
||||
|
||||
return current;
|
||||
}
|
||||
@@ -1,5 +0,0 @@
|
||||
Category: mini
|
||||
Board URL: http://www.advansus.com.tw/products/247/A785E-I
|
||||
ROM package: SOIC-8
|
||||
ROM protocol: SPI
|
||||
ROM socketed: n
|
||||
@@ -1,52 +0,0 @@
|
||||
entries
|
||||
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
#392 3 r 0 unused
|
||||
395 1 e 1 hw_scrubber
|
||||
396 1 e 1 interleave_chip_selects
|
||||
397 2 e 8 max_mem_clock
|
||||
399 1 e 2 multi_core
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
440 4 e 9 slow_cpu
|
||||
444 1 e 1 nmi
|
||||
445 1 e 1 gart
|
||||
456 1 e 1 ECC_memory
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
6 5 Notice
|
||||
6 6 Info
|
||||
6 7 Debug
|
||||
6 8 Spew
|
||||
8 0 400Mhz
|
||||
8 1 333Mhz
|
||||
8 2 266Mhz
|
||||
8 3 200Mhz
|
||||
9 0 off
|
||||
9 1 87.5%
|
||||
9 2 75.0%
|
||||
9 3 62.5%
|
||||
9 4 50.0%
|
||||
9 5 37.5%
|
||||
9 6 25.0%
|
||||
9 7 12.5%
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
@@ -1,124 +0,0 @@
|
||||
# sample config for advansus/A785E-I
|
||||
chip northbridge/amd/amdfam10/root_complex
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_ASB2 #L1 and DDR3
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device domain 0 on
|
||||
subsystemid 0x1612 0x3060 inherit #TODO: Set the correctly subsystem id.
|
||||
chip northbridge/amd/amdfam10
|
||||
device pci 18.0 on # northbridge
|
||||
chip southbridge/amd/rs780
|
||||
device pci 0.0 on end # HT 0x9600
|
||||
device pci 1.0 on end # Internal Graphics P2P bridge 0x9712
|
||||
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
|
||||
device pci 3.0 off end # PCIE P2P bridge 0x960b
|
||||
device pci 4.0 on end # PCIE P2P bridge 0x9604 wireless
|
||||
device pci 5.0 off end # PCIE P2P bridge 0x9605
|
||||
device pci 6.0 off end # PCIE P2P bridge 0x9606
|
||||
device pci 7.0 off end # PCIE P2P bridge 0x9607
|
||||
device pci 8.0 off end # NB/SB Link P2P bridge
|
||||
device pci 9.0 on end # Ethernet
|
||||
device pci a.0 on end # Ethernet
|
||||
register "gppsb_configuration" = "4" # Configuration E
|
||||
register "gpp_configuration" = "3" # Configuration D
|
||||
register "port_enable" = "0x6f6"
|
||||
register "gfx_dev2_dev3" = "0"
|
||||
register "gfx_dual_slot" = "0"
|
||||
register "gfx_lane_reversal" = "0"
|
||||
register "gfx_compliance" = "0"
|
||||
register "gfx_reconfiguration" = "1"
|
||||
register "gfx_link_width" = "0"
|
||||
register "gfx_tmds" = "1"
|
||||
register "gfx_pcie_config" = "3" # 1x8 GFX on Lanes 8-15
|
||||
register "gfx_ddi_config" = "1" # Lanes 0-3 DDI_SL
|
||||
end
|
||||
chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pci bus
|
||||
device pci 11.0 on end # SATA
|
||||
device pci 12.0 on end # USB
|
||||
device pci 12.2 on end # USB
|
||||
device pci 13.0 on end # USB
|
||||
device pci 13.2 on end # USB
|
||||
device pci 14.0 on # SM
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
end # SM
|
||||
device pci 14.1 on end # IDE 0x439c
|
||||
device pci 14.2 on end # HDA 0x4383
|
||||
device pci 14.3 on
|
||||
chip superio/winbond/w83627hf
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.2 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 on # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.6 off # SFI
|
||||
io 0x62 = 0x100
|
||||
end
|
||||
device pnp 2e.7 off # GPIO_GAME_MIDI
|
||||
io 0x60 = 0x220
|
||||
io 0x62 = 0x300
|
||||
irq 0x70 = 9
|
||||
end
|
||||
device pnp 2e.8 off end # WDTO_PLED
|
||||
device pnp 2e.9 off end # GPIO_SUSLED
|
||||
device pnp 2e.a off end # ACPI
|
||||
device pnp 2e.b on # HW Monitor
|
||||
io 0x60 = 0x290
|
||||
irq 0x70 = 5
|
||||
end
|
||||
end #superio/winbond/w83627hf
|
||||
end # LPC 0x439d
|
||||
device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
|
||||
device pci 14.5 on end # USB 2
|
||||
device pci 14.6 off end # Gec
|
||||
device pci 15.0 on end # PCIe 0
|
||||
device pci 15.1 on end # PCIe 1
|
||||
device pci 15.2 on end # PCIe 2
|
||||
device pci 15.3 on end # PCIe 3
|
||||
device pci 16.0 on end # USB
|
||||
device pci 16.2 on end # USB
|
||||
#register "gpp_configuration" = "0" #4:0:0:0
|
||||
#register "gpp_configuration" = "2" #2:2:0:0
|
||||
#register "gpp_configuration" = "3" #2:1:1:0
|
||||
register "gpp_configuration" = "4" #1:1:1:1
|
||||
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
|
||||
end #southbridge/amd/cimx/sb800
|
||||
end # device pci 18.0
|
||||
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
device pci 18.4 on end
|
||||
end
|
||||
end #domain
|
||||
end
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,44 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/pci.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <cpu/amd/multicore.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
/* Global variables for MB layouts and these will be shared by irqtable mptable
|
||||
* and acpi_tables busnum is default.
|
||||
*/
|
||||
u32 apicid_sb800;
|
||||
|
||||
void get_bus_conf(void)
|
||||
{
|
||||
u32 apicid_base;
|
||||
|
||||
get_default_pci1234(1);
|
||||
|
||||
sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
|
||||
|
||||
|
||||
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
if (CONFIG(LOGICAL_CPUS))
|
||||
apicid_base = get_apicid_base(1);
|
||||
else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
apicid_sb800 = apicid_base + 0;
|
||||
}
|
||||
@@ -1,101 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
|
||||
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
|
||||
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
|
||||
u8 slot, u8 rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
u32 slot_num;
|
||||
u8 *v;
|
||||
|
||||
u8 sum = 0;
|
||||
int i;
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be between 0xf0000 & 0x100000 */
|
||||
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (u8 *) (addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
pirq->rtr_bus = pirq_router_bus;
|
||||
pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
pirq->rtr_vendor = 0x1002;
|
||||
pirq->rtr_device = 0x4384;
|
||||
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *)(&pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
|
||||
/* pci bridge */
|
||||
write_pirq_info(pirq_info, pirq_router_bus, PCI_DEVFN(0x14, 4),
|
||||
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
|
||||
0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "write_pirq_routing_table done.\n");
|
||||
|
||||
return (unsigned long)pirq_info;
|
||||
}
|
||||
@@ -1,64 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <southbridge/amd/common/amd_defs.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <southbridge/amd/rs780/rs780.h>
|
||||
|
||||
/* GPIO6. */
|
||||
static void enable_int_gfx(void)
|
||||
{
|
||||
volatile u8 *gpio_reg;
|
||||
|
||||
/* make sure the Acpi MMIO(fed80000) is accessible */
|
||||
// XXX Redo this RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
|
||||
|
||||
gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0xD00; /* IoMux Register */
|
||||
|
||||
*(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
|
||||
*(gpio_reg + 170) = 0x1; /* gpio_gate */
|
||||
|
||||
gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0x100; /* GPIO Registers */
|
||||
|
||||
*(gpio_reg + 0x6) = 0x8;
|
||||
*(gpio_reg + 170) = 0x0;
|
||||
}
|
||||
|
||||
int is_dev3_present(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*************************************************
|
||||
* enable the dedicated function in A785E-I board.
|
||||
* This function called early than rs780_enable.
|
||||
*************************************************/
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
printk(BIOS_INFO, "Mainboard A785E-I Enable. dev=0x%p\n", dev);
|
||||
|
||||
set_pcie_dereset();
|
||||
enable_int_gfx();
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
@@ -1,79 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/pci.h>
|
||||
#include <arch/io.h>
|
||||
#include <stdint.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
extern u32 apicid_sb800;
|
||||
|
||||
u8 intr_data[] = {
|
||||
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
|
||||
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
|
||||
[0x10] = 0x1F,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x10,0x11,0x12,0x13
|
||||
};
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
u32 dword = 0;
|
||||
u8 byte;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
// XXX Redo this: ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
|
||||
dword &= 0xFFFFFFF0;
|
||||
smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword);
|
||||
|
||||
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
|
||||
outb(byte | 0x80, 0xC00);
|
||||
outb(intr_data[byte], 0xC01);
|
||||
}
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
@@ -1,215 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _PLATFORM_CFG_H_
|
||||
#define _PLATFORM_CFG_H_
|
||||
|
||||
/**
|
||||
* @def BIOS_SIZE
|
||||
* BIOS_SIZE_{1,2,4,8,16}M
|
||||
*
|
||||
* In SB800, default ROM size is 1M Bytes, if your platform ROM
|
||||
* bigger than 1M you have to set the ROM size outside CIMx module and
|
||||
* before AGESA module get call.
|
||||
*/
|
||||
#ifndef BIOS_SIZE
|
||||
#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1)
|
||||
#endif /* BIOS_SIZE */
|
||||
|
||||
/**
|
||||
* @def SPREAD_SPECTRUM
|
||||
* @brief
|
||||
* 0 - Disable Spread Spectrum function
|
||||
* 1 - Enable Spread Spectrum function
|
||||
*/
|
||||
#define SPREAD_SPECTRUM 0
|
||||
|
||||
/**
|
||||
* @def SB_HPET_TIMER
|
||||
* @brief
|
||||
* 0 - Disable hpet
|
||||
* 1 - Enable hpet
|
||||
*/
|
||||
#define HPET_TIMER 1
|
||||
|
||||
/**
|
||||
* @def USB_CONFIG
|
||||
* @brief bit[0-6] used to control USB
|
||||
* 0 - Disable
|
||||
* 1 - Enable
|
||||
* Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0
|
||||
* Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1
|
||||
* Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2
|
||||
* Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3
|
||||
* Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4
|
||||
* Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5
|
||||
* Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6
|
||||
*/
|
||||
#define USB_CONFIG 0x7F
|
||||
|
||||
/**
|
||||
* @def PCI_CLOCK_CTRL
|
||||
* @brief bit[0-4] used for PCI Slots Clock Control,
|
||||
* 0 - disable
|
||||
* 1 - enable
|
||||
* PCI SLOT 0 define at BIT0
|
||||
* PCI SLOT 1 define at BIT1
|
||||
* PCI SLOT 2 define at BIT2
|
||||
* PCI SLOT 3 define at BIT3
|
||||
* PCI SLOT 4 define at BIT4
|
||||
*/
|
||||
#define PCI_CLOCK_CTRL 0x1F
|
||||
|
||||
/**
|
||||
* @def SATA_CONTROLLER
|
||||
* @brief INCHIP Sata Controller
|
||||
*/
|
||||
#define SATA_CONTROLLER CIMX_OPTION_ENABLED
|
||||
|
||||
/**
|
||||
* @def SATA_MODE
|
||||
* @brief INCHIP Sata Controller Mode
|
||||
* NOTE: DO NOT ALLOW SATA & IDE use same mode
|
||||
*/
|
||||
#define SATA_MODE CONFIG_SB800_SATA_MODE
|
||||
|
||||
/**
|
||||
* @brief INCHIP Sata IDE Controller Mode
|
||||
*/
|
||||
#define IDE_LEGACY_MODE 0
|
||||
#define IDE_NATIVE_MODE 1
|
||||
|
||||
/**
|
||||
* @def SATA_IDE_MODE
|
||||
* @brief INCHIP Sata IDE Controller Mode
|
||||
* NOTE: DO NOT ALLOW SATA & IDE use same mode
|
||||
*/
|
||||
#define SATA_IDE_MODE IDE_LEGACY_MODE
|
||||
|
||||
/**
|
||||
* @def EXTERNAL_CLOCK
|
||||
* @brief 00/10: Reference clock from crystal oscillator via
|
||||
* PAD_XTALI and PAD_XTALO
|
||||
*
|
||||
* @def INTERNAL_CLOCK
|
||||
* @brief 01/11: Reference clock from internal clock through
|
||||
* CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
|
||||
*/
|
||||
#define EXTERNAL_CLOCK 0x00
|
||||
#define INTERNAL_CLOCK 0x01
|
||||
|
||||
/* NOTE: inagua have to using internal clock,
|
||||
* otherwise can not detect sata drive
|
||||
*/
|
||||
#define SATA_CLOCK_SOURCE INTERNAL_CLOCK
|
||||
|
||||
/**
|
||||
* @def SATA_PORT_MULT_CAP_RESERVED
|
||||
* @brief 1 ON, 0 0FF
|
||||
*/
|
||||
#define SATA_PORT_MULT_CAP_RESERVED 1
|
||||
|
||||
|
||||
/**
|
||||
* @def AZALIA_AUTO
|
||||
* @brief Detect Azalia controller automatically.
|
||||
*
|
||||
* @def AZALIA_DISABLE
|
||||
* @brief Disable Azalia controller.
|
||||
|
||||
* @def AZALIA_ENABLE
|
||||
* @brief Enable Azalia controller.
|
||||
*/
|
||||
#define AZALIA_AUTO 0
|
||||
#define AZALIA_DISABLE 1
|
||||
#define AZALIA_ENABLE 2
|
||||
|
||||
/**
|
||||
* @brief INCHIP HDA controller
|
||||
*/
|
||||
#define AZALIA_CONTROLLER AZALIA_AUTO
|
||||
|
||||
/**
|
||||
* @def AZALIA_PIN_CONFIG
|
||||
* @brief
|
||||
* 0 - disable
|
||||
* 1 - enable
|
||||
*/
|
||||
#define AZALIA_PIN_CONFIG 1
|
||||
|
||||
/**
|
||||
* @def AZALIA_SDIN_PIN
|
||||
* @brief
|
||||
* SDIN0 is define at BIT0 & BIT1
|
||||
* 00 - GPIO PIN
|
||||
* 01 - Reserved
|
||||
* 10 - As a Azalia SDIN pin
|
||||
* SDIN1 is define at BIT2 & BIT3
|
||||
* SDIN2 is define at BIT4 & BIT5
|
||||
* SDIN3 is define at BIT6 & BIT7
|
||||
*/
|
||||
#define AZALIA_SDIN_PIN 0x2A
|
||||
|
||||
/**
|
||||
* @def GPP_CONTROLLER
|
||||
*/
|
||||
#define GPP_CONTROLLER CIMX_OPTION_ENABLED
|
||||
|
||||
/**
|
||||
* @def GPP_CFGMODE
|
||||
* @brief GPP Link Configuration
|
||||
* four possible configuration:
|
||||
* GPP_CFGMODE_X4000
|
||||
* GPP_CFGMODE_X2200
|
||||
* GPP_CFGMODE_X2110
|
||||
* GPP_CFGMODE_X1111
|
||||
*/
|
||||
#define GPP_CFGMODE GPP_CFGMODE_X1111
|
||||
|
||||
/**
|
||||
* @def NB_SB_GEN2
|
||||
* 0 - Disable
|
||||
* 1 - Enable
|
||||
*/
|
||||
#define NB_SB_GEN2 TRUE
|
||||
|
||||
/**
|
||||
* @def SB_GPP_GEN2
|
||||
* 0 - Disable
|
||||
* 1 - Enable
|
||||
*/
|
||||
#define SB_GPP_GEN2 TRUE
|
||||
|
||||
/**
|
||||
* @def SB_GPP_UNHIDE_PORTS
|
||||
* TRUE - ports visible always, even port empty
|
||||
* FALSE - ports invisible if port empty
|
||||
*/
|
||||
#define SB_GPP_UNHIDE_PORTS FALSE
|
||||
|
||||
/**
|
||||
* @def GEC_CONFIG
|
||||
* 0 - Enable
|
||||
* 1 - Disable
|
||||
*/
|
||||
#define GEC_CONFIG 0
|
||||
|
||||
/**
|
||||
* @def SIO_HWM_BASE_ADDRESS
|
||||
* Super IO HWM base address
|
||||
*/
|
||||
#define SIO_HWM_BASE_ADDRESS 0x290
|
||||
|
||||
#endif
|
||||
@@ -1,273 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <commonlib/helpers.h>
|
||||
#include <northbridge/amd/amdfam10/amdfam10.h>
|
||||
|
||||
void setup_mb_resource_map(void)
|
||||
{
|
||||
static const unsigned int register_values[] = {
|
||||
/* Careful set limit registers before base registers which contain the enables */
|
||||
/* DRAM Limit i Registers
|
||||
* F1:0x44 i = 0
|
||||
* F1:0x4C i = 1
|
||||
* F1:0x54 i = 2
|
||||
* F1:0x5C i = 3
|
||||
* F1:0x64 i = 4
|
||||
* F1:0x6C i = 5
|
||||
* F1:0x74 i = 6
|
||||
* F1:0x7C i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 3] Reserved
|
||||
* [10: 8] Interleave select
|
||||
* specifies the values of A[14:12] to use with interleave enable.
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Limit Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40 bit address
|
||||
* that define the end of the DRAM region.
|
||||
*/
|
||||
/* Don't touch it, we need it for CONFIG_CAR_FAM10 */
|
||||
ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001,
|
||||
ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002,
|
||||
ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003,
|
||||
ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004,
|
||||
ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005,
|
||||
ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006,
|
||||
ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
|
||||
/* DRAM Base i Registers
|
||||
* F1:0x40 i = 0
|
||||
* F1:0x48 i = 1
|
||||
* F1:0x50 i = 2
|
||||
* F1:0x58 i = 3
|
||||
* F1:0x60 i = 4
|
||||
* F1:0x68 i = 5
|
||||
* F1:0x70 i = 6
|
||||
* F1:0x78 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 7: 2] Reserved
|
||||
* [10: 8] Interleave Enable
|
||||
* 000 = No interleave
|
||||
* 001 = Interleave on A[12] (2 nodes)
|
||||
* 010 = reserved
|
||||
* 011 = Interleave on A[12] and A[14] (4 nodes)
|
||||
* 100 = reserved
|
||||
* 101 = reserved
|
||||
* 110 = reserved
|
||||
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
|
||||
* [15:11] Reserved
|
||||
* [13:16] DRAM Base Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40-bit address
|
||||
* that define the start of the DRAM region.
|
||||
*/
|
||||
/* don't touch it, we need it for CONFIG_CAR_FAM10 */
|
||||
ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
* F1:0x8C i = 1
|
||||
* F1:0x94 i = 2
|
||||
* F1:0x9C i = 3
|
||||
* F1:0xA4 i = 4
|
||||
* F1:0xAC i = 5
|
||||
* F1:0xB4 i = 6
|
||||
* F1:0xBC i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Reserved
|
||||
* [ 6: 6] Reserved
|
||||
* [ 7: 7] Non-Posted
|
||||
* 0 = CPU writes may be posted
|
||||
* 1 = CPU writes must be non-posted
|
||||
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
|
||||
* This field defines the upp address bits of a 40-bit address that
|
||||
* defines the end of a memory-mapped I/O region n
|
||||
*/
|
||||
ADDRMAP_REG(0x84), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x8C), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x94), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x9C), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xA4), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xAC), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Base i Registers
|
||||
* F1:0x80 i = 0
|
||||
* F1:0x88 i = 1
|
||||
* F1:0x90 i = 2
|
||||
* F1:0x98 i = 3
|
||||
* F1:0xA0 i = 4
|
||||
* F1:0xA8 i = 5
|
||||
* F1:0xB0 i = 6
|
||||
* F1:0xB8 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Cpu Disable
|
||||
* 0 = Cpu can use this I/O range
|
||||
* 1 = Cpu requests do not use this I/O range
|
||||
* [ 3: 3] Lock
|
||||
* 0 = base/limit registers i are read/write
|
||||
* 1 = base/limit registers i are read-only
|
||||
* [ 7: 4] Reserved
|
||||
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
|
||||
* This field defines the upper address bits of a 40bit address
|
||||
* that defines the start of memory-mapped I/O region i
|
||||
*/
|
||||
ADDRMAP_REG(0x80), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x88), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x90), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x98), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
|
||||
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
* F1:0xCC i = 1
|
||||
* F1:0xD4 i = 2
|
||||
* F1:0xDC i = 3
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = reserved
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Limit Address i
|
||||
* This field defines the end of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000,
|
||||
ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000,
|
||||
ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
|
||||
|
||||
/* PCI I/O Base i Registers
|
||||
* F1:0xC0 i = 0
|
||||
* F1:0xC8 i = 1
|
||||
* F1:0xD0 i = 2
|
||||
* F1:0xD8 i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 3: 2] Reserved
|
||||
* [ 4: 4] VGA Enable
|
||||
* 0 = VGA matches Disabled
|
||||
* 1 = matches all address < 64K and where A[9:0] is in the
|
||||
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
|
||||
* [ 5: 5] ISA Enable
|
||||
* 0 = ISA matches Disabled
|
||||
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
|
||||
* from matching agains this base/limit pair
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Base i
|
||||
* This field defines the start of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000,
|
||||
ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000,
|
||||
ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
|
||||
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
* F1:0xE8 i = 2
|
||||
* F1:0xEC i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Device Number Compare Enable
|
||||
* 0 = The ranges are based on bus number
|
||||
* 1 = The ranges are ranges of devices on bus 0
|
||||
* [ 3: 3] Reserved
|
||||
* [ 6: 4] Destination Node
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 7] Reserved
|
||||
* [ 9: 8] Destination Link
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 - Reserved
|
||||
* [15:10] Reserved
|
||||
* [23:16] Bus Number Base i
|
||||
* This field defines the lowest bus number in configuration region i
|
||||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration regin i
|
||||
*/
|
||||
/* AMD 8111 on link0 of CPU 0 */
|
||||
ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000,
|
||||
ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000,
|
||||
ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
|
||||
};
|
||||
|
||||
int max;
|
||||
max = ARRAY_SIZE(register_values);
|
||||
setup_resource_map(register_values, max);
|
||||
}
|
||||
@@ -1,223 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#define SYSTEM_TYPE 1 /* SERVER=0, DESKTOP=1, MOBILE=2 */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <console/console.h>
|
||||
#include <timestamp.h>
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include <superio/winbond/common/winbond.h>
|
||||
#include <superio/winbond/w83627hf/w83627hf.h>
|
||||
#include <cpu/amd/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <cpu/amd/car.h>
|
||||
#include <northbridge/amd/amdfam10/raminit.h>
|
||||
#include <northbridge/amd/amdht/ht_wrapper.h>
|
||||
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
|
||||
#include <southbridge/amd/common/reset.h>
|
||||
#include <southbridge/amd/sb800/smbus.h>
|
||||
#include <southbridge/amd/sb800/sb800.h>
|
||||
#include <southbridge/amd/rs780/rs780.h>
|
||||
#include "southbridge/amd/sb800/early_setup.c"
|
||||
#include <arch/early_variables.h>
|
||||
#include <cbmem.h>
|
||||
|
||||
#include "cpu/amd/quadcore/quadcore.c"
|
||||
#include "spd.h"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
|
||||
|
||||
int spd_read_byte(unsigned int device, unsigned int address);
|
||||
|
||||
|
||||
int spd_read_byte(u32 device, u32 address)
|
||||
{
|
||||
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
|
||||
}
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
struct sys_info *sysinfo = get_sysinfo();
|
||||
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
|
||||
u32 bsp_apicid = 0, val;
|
||||
msr_t msr;
|
||||
|
||||
timestamp_init(timestamp_get());
|
||||
timestamp_add_now(TS_START_ROMSTAGE);
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
/* mov bsp to bus 0xff when > 8 nodes */
|
||||
set_bsp_node_CHtExtNodeCfgEn();
|
||||
enumerate_ht_chain();
|
||||
|
||||
/* enable port80 decoding and southbridge poweron init */
|
||||
sb800_lpc_init();
|
||||
sb800_pci_port80();
|
||||
}
|
||||
|
||||
post_code(0x30);
|
||||
|
||||
if (bist == 0) {
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
|
||||
/* All cores run this but the BSP(node0,core0) is the only core that returns. */
|
||||
}
|
||||
|
||||
post_code(0x32);
|
||||
|
||||
enable_rs780_dev8();
|
||||
sb800_clk_output_48Mhz();
|
||||
|
||||
winbond_set_clksel_48(PNP_DEV(0x2e, 0));
|
||||
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
|
||||
console_init();
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
/* Load MPB */
|
||||
val = cpuid_eax(1);
|
||||
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
|
||||
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
|
||||
printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
|
||||
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
|
||||
|
||||
/* Setup sysinfo defaults */
|
||||
set_sysinfo_in_ram(0);
|
||||
|
||||
update_microcode(val);
|
||||
|
||||
post_code(0x33);
|
||||
|
||||
cpuSetAMDMSR(0);
|
||||
post_code(0x34);
|
||||
|
||||
amd_ht_init(sysinfo);
|
||||
post_code(0x35);
|
||||
|
||||
/* Setup nodes PCI space and start core 0 AP init. */
|
||||
finalize_node_setup(sysinfo);
|
||||
|
||||
/* Setup any mainboard PCI settings etc. */
|
||||
setup_mb_resource_map();
|
||||
post_code(0x36);
|
||||
|
||||
/* wait for all the APs core0 started by finalize_node_setup. */
|
||||
/* FIXME: A bunch of cores are going to start output to serial at once.
|
||||
It would be nice to fixup prink spinlocks for ROM XIP mode.
|
||||
I think it could be done by putting the spinlock flag in the cache
|
||||
of the BSP located right after sysinfo.
|
||||
*/
|
||||
wait_all_core0_started();
|
||||
|
||||
#if CONFIG(LOGICAL_CPUS)
|
||||
/* Core0 on each node is configured. Now setup any additional cores. */
|
||||
printk(BIOS_DEBUG, "start_other_cores()\n");
|
||||
start_other_cores(bsp_apicid);
|
||||
post_code(0x37);
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
#endif
|
||||
|
||||
post_code(0x38);
|
||||
|
||||
/* run _early_setup before soft-reset. */
|
||||
rs780_early_setup();
|
||||
sb800_early_setup();
|
||||
|
||||
#if CONFIG(SET_FIDVID)
|
||||
msr = rdmsr(MSR_COFVID_STS);
|
||||
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
|
||||
post_code(0x39);
|
||||
|
||||
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
|
||||
|
||||
if (!warm_reset_detect(0)) { /* BSP is node 0 */
|
||||
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
|
||||
} else {
|
||||
init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */
|
||||
}
|
||||
|
||||
post_code(0x3A);
|
||||
|
||||
/* show final fid and vid */
|
||||
msr = rdmsr(MSR_COFVID_STS);
|
||||
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
|
||||
#endif
|
||||
|
||||
rs780_htinit();
|
||||
|
||||
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
|
||||
if (!warm_reset_detect(0)) {
|
||||
printk(BIOS_INFO, "...WARM RESET...\n\n\n");
|
||||
soft_reset();
|
||||
die("After soft_reset - shouldn't see this message!!!\n");
|
||||
}
|
||||
|
||||
post_code(0x3B);
|
||||
|
||||
/* It's the time to set ctrl in sysinfo now; */
|
||||
printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
|
||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
||||
|
||||
post_code(0x40);
|
||||
|
||||
raminit_amdmct(sysinfo);
|
||||
|
||||
cbmem_initialize_empty();
|
||||
post_code(0x41);
|
||||
|
||||
amdmct_cbmem_store_info(sysinfo);
|
||||
|
||||
sb800_before_pci_init();
|
||||
|
||||
post_code(0x42);
|
||||
}
|
||||
|
||||
/**
|
||||
* BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
|
||||
* Description:
|
||||
* This routine is called every time a non-coherent chain is processed.
|
||||
* BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
|
||||
* swap list. The first part of the list controls the BUID assignment and the
|
||||
* second part of the list provides the device to device linking. Device orientation
|
||||
* can be detected automatically, or explicitly. See documentation for more details.
|
||||
*
|
||||
* Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
|
||||
* based on each device's unit count.
|
||||
*
|
||||
* Parameters:
|
||||
* @param[in] node = The node on which this chain is located
|
||||
* @param[in] link = The link on the host for this chain
|
||||
* @param[out] List = supply a pointer to a list
|
||||
*/
|
||||
BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
|
||||
{
|
||||
static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF};
|
||||
/* If the BUID was adjusted in early_ht we need to do the manual override */
|
||||
if ((node == 0) && (link == 0)) { /* BSP SB link */
|
||||
*List = swaplist;
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -1,60 +0,0 @@
|
||||
if BOARD_AMD_BIMINI_FAM10
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS
|
||||
def_bool y
|
||||
select CPU_AMD_SOCKET_ASB2
|
||||
select DIMM_DDR3
|
||||
select DIMM_REGISTERED
|
||||
select NORTHBRIDGE_AMD_AMDFAM10
|
||||
select SOUTHBRIDGE_AMD_RS780
|
||||
select SOUTHBRIDGE_AMD_SB800
|
||||
select SUPERIO_ITE_IT8718F
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_TABLES
|
||||
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
select LIFT_BSP_APIC_ID
|
||||
select BOARD_ROMSIZE_KB_2048
|
||||
select ENABLE_APIC_EXT_ID
|
||||
select GFXUMA
|
||||
select HAVE_DEBUG_CAR
|
||||
select SET_FIDVID
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default amd/bimini_fam10
|
||||
|
||||
config APIC_ID_OFFSET
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "Bimini (Fam10)"
|
||||
|
||||
config HW_MEM_HOLE_SIZEK
|
||||
hex
|
||||
default 0x100000
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 8
|
||||
|
||||
config MAX_PHYSICAL_CPUS
|
||||
int
|
||||
default 2
|
||||
|
||||
config HT_CHAIN_END_UNITID_BASE
|
||||
hex
|
||||
default 0x1
|
||||
|
||||
config HT_CHAIN_UNITID_BASE
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 11
|
||||
|
||||
endif #BOARD_AMD_BIMINI_FAM10
|
||||
@@ -1,2 +0,0 @@
|
||||
config BOARD_AMD_BIMINI_FAM10
|
||||
bool "Bimini (Fam10)"
|
||||
@@ -1,16 +0,0 @@
|
||||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
|
||||
romstage-y += resourcemap.c
|
||||
|
||||
ramstage-y += get_bus_conf.c
|
||||
@@ -1,80 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* This file defines the processor and performance state capability
|
||||
* for each core in the system. It is included into the DSDT for each
|
||||
* core. It assumes that each core of the system has the same performance
|
||||
* characteristics.
|
||||
*/
|
||||
/*
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001)
|
||||
{
|
||||
Scope (\_PR) {
|
||||
Device (CPU0) {
|
||||
Name (_HID, "ACPI0007")
|
||||
Name (_UID, 0)
|
||||
#include "cpstate.asl"
|
||||
}
|
||||
Device (CPU1) {
|
||||
Name (_HID, "ACPI0007")
|
||||
Name (_UID, 1)
|
||||
#include "cpstate.asl"
|
||||
}
|
||||
Device (CPU2) {
|
||||
Name (_HID, "ACPI0007")
|
||||
Name (_UID, 2)
|
||||
#include "cpstate.asl"
|
||||
}
|
||||
Device (CPU3) {
|
||||
Name (_HID, "ACPI0007")
|
||||
Name (_UID, 3)
|
||||
#include "cpstate.asl"
|
||||
}
|
||||
}
|
||||
*/
|
||||
/* P-state support: The maximum number of P-states supported by the */
|
||||
/* CPUs we'll use is 6. */
|
||||
/* Get from AMI BIOS. */
|
||||
Name(_PSS, Package(){
|
||||
Package ()
|
||||
{
|
||||
0x00000AF0,
|
||||
0x0000BF81,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000000,
|
||||
0x00000000
|
||||
},
|
||||
|
||||
Package ()
|
||||
{
|
||||
0x00000578,
|
||||
0x000076F2,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000001,
|
||||
0x00000001
|
||||
}
|
||||
})
|
||||
|
||||
Name(_PCT, Package(){
|
||||
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
|
||||
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
|
||||
})
|
||||
|
||||
Method(_PPC, 0){
|
||||
Return(0)
|
||||
}
|
||||
@@ -1,240 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
Scope (_SB) {
|
||||
Device(PCI0) {
|
||||
Device(IDEC) {
|
||||
Name(_ADR, 0x00140001)
|
||||
#include "ide.asl"
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
/* Some timing tables */
|
||||
Name(UDTT, Package(){ /* Udma timing table */
|
||||
120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
|
||||
})
|
||||
|
||||
Name(MDTT, Package(){ /* MWDma timing table */
|
||||
480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
|
||||
})
|
||||
|
||||
Name(POTT, Package(){ /* Pio timing table */
|
||||
600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
|
||||
})
|
||||
|
||||
/* Some timing register value tables */
|
||||
Name(MDRT, Package(){ /* MWDma timing register table */
|
||||
0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
|
||||
})
|
||||
|
||||
Name(PORT, Package(){
|
||||
0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
|
||||
})
|
||||
|
||||
OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
|
||||
Field(ICRG, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
PPTS, 8, /* Primary PIO Slave Timing */
|
||||
PPTM, 8, /* Primary PIO Master Timing */
|
||||
OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
|
||||
PMTM, 8, /* Primary MWDMA Master Timing */
|
||||
OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
|
||||
OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
|
||||
PPSM, 4, /* Primary PIO slave Mode */
|
||||
OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
|
||||
OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
|
||||
PDSM, 4, /* Primary UltraDMA Mode */
|
||||
}
|
||||
|
||||
Method(GTTM, 1) /* get total time*/
|
||||
{
|
||||
Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
|
||||
Increment(Local0)
|
||||
Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
|
||||
Increment(Local1)
|
||||
Return(Multiply(30, Add(Local0, Local1)))
|
||||
}
|
||||
|
||||
Device(PRID)
|
||||
{
|
||||
Name (_ADR, Zero)
|
||||
Method(_GTM, 0)
|
||||
{
|
||||
NAME(OTBF, Buffer(20) { /* out buffer */
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
|
||||
CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
|
||||
CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
|
||||
CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
|
||||
CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
|
||||
|
||||
/* Just return if the channel is disabled */
|
||||
If(And(PPCR, 0x01)) { /* primary PIO control */
|
||||
Return(OTBF)
|
||||
}
|
||||
|
||||
/* Always tell them independent timing available and IOChannelReady used on both drives */
|
||||
Or(BFFG, 0x1A, BFFG)
|
||||
|
||||
Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
|
||||
Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
|
||||
|
||||
If(And(PDCR, 0x01)) { /* It's under UDMA mode */
|
||||
Or(BFFG, 0x01, BFFG)
|
||||
Store(DerefOf(Index(UDTT, PDMM)), DSD0)
|
||||
}
|
||||
Else {
|
||||
Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
|
||||
}
|
||||
|
||||
If(And(PDCR, 0x02)) { /* It's under UDMA mode */
|
||||
Or(BFFG, 0x04, BFFG)
|
||||
Store(DerefOf(Index(UDTT, PDSM)), DSD1)
|
||||
}
|
||||
Else {
|
||||
Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
|
||||
}
|
||||
|
||||
Return(OTBF) /* out buffer */
|
||||
} /* End Method(_GTM) */
|
||||
|
||||
Method(_STM, 3, NotSerialized)
|
||||
{
|
||||
NAME(INBF, Buffer(20) { /* in buffer */
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
|
||||
CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
|
||||
CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
|
||||
CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
|
||||
CreateDwordField(INBF, 16, BFFG) /*buffer flag */
|
||||
|
||||
Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
|
||||
Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
|
||||
Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
|
||||
|
||||
Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
|
||||
Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
|
||||
|
||||
If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
|
||||
Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 7, PDMM,)
|
||||
Or(PDCR, 0x01, PDCR)
|
||||
}
|
||||
Else {
|
||||
If(LNotEqual(DSD0, 0xFFFFFFFF)) {
|
||||
Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
|
||||
Store(DerefOf(Index(MDRT, Local0)), PMTM)
|
||||
}
|
||||
}
|
||||
|
||||
If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
|
||||
Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 7, PDSM,)
|
||||
Or(PDCR, 0x02, PDCR)
|
||||
}
|
||||
Else {
|
||||
If(LNotEqual(DSD1, 0xFFFFFFFF)) {
|
||||
Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
|
||||
Store(DerefOf(Index(MDRT, Local0)), PMTS)
|
||||
}
|
||||
}
|
||||
/* Return(INBF) */
|
||||
} /*End Method(_STM) */
|
||||
Device(MST)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_GTF) {
|
||||
Name(CMBF, Buffer(21) {
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
|
||||
})
|
||||
CreateByteField(CMBF, 1, POMD)
|
||||
CreateByteField(CMBF, 8, DMMD)
|
||||
CreateByteField(CMBF, 5, CMDA)
|
||||
CreateByteField(CMBF, 12, CMDB)
|
||||
CreateByteField(CMBF, 19, CMDC)
|
||||
|
||||
Store(0xA0, CMDA)
|
||||
Store(0xA0, CMDB)
|
||||
Store(0xA0, CMDC)
|
||||
|
||||
Or(PPMM, 0x08, POMD)
|
||||
|
||||
If(And(PDCR, 0x01)) {
|
||||
Or(PDMM, 0x40, DMMD)
|
||||
}
|
||||
Else {
|
||||
Store(Match
|
||||
(MDTT, MLE, GTTM(PMTM),
|
||||
MTR, 0, 0), Local0)
|
||||
If(LLess(Local0, 3)) {
|
||||
Or(0x20, Local0, DMMD)
|
||||
}
|
||||
}
|
||||
Return(CMBF)
|
||||
}
|
||||
} /* End Device(MST) */
|
||||
|
||||
Device(SLAV)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_GTF) {
|
||||
Name(CMBF, Buffer(21) {
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
|
||||
})
|
||||
CreateByteField(CMBF, 1, POMD)
|
||||
CreateByteField(CMBF, 8, DMMD)
|
||||
CreateByteField(CMBF, 5, CMDA)
|
||||
CreateByteField(CMBF, 12, CMDB)
|
||||
CreateByteField(CMBF, 19, CMDC)
|
||||
|
||||
Store(0xB0, CMDA)
|
||||
Store(0xB0, CMDB)
|
||||
Store(0xB0, CMDC)
|
||||
|
||||
Or(PPSM, 0x08, POMD)
|
||||
|
||||
If(And(PDCR, 0x02)) {
|
||||
Or(PDSM, 0x40, DMMD)
|
||||
}
|
||||
Else {
|
||||
Store(Match
|
||||
(MDTT, MLE, GTTM(PMTS),
|
||||
MTR, 0, 0), Local0)
|
||||
If(LLess(Local0, 3)) {
|
||||
Or(0x20, Local0, DMMD)
|
||||
}
|
||||
}
|
||||
Return(CMBF)
|
||||
}
|
||||
} /* End Device(SLAV) */
|
||||
}
|
||||
@@ -1,395 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
|
||||
)
|
||||
{
|
||||
#include "routing.asl"
|
||||
}
|
||||
*/
|
||||
|
||||
/* Routing is in System Bus scope */
|
||||
Scope(\_SB) {
|
||||
Name(PR0, Package(){
|
||||
/* NB devices */
|
||||
/* Bus 0, Dev 0 - RS780 Host Controller */
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
|
||||
Package(){0x0002FFFF, 0, INTC, 0 },
|
||||
Package(){0x0002FFFF, 1, INTD, 0 },
|
||||
Package(){0x0002FFFF, 2, INTA, 0 },
|
||||
Package(){0x0002FFFF, 3, INTB, 0 },
|
||||
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
|
||||
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||
Package(){0x0004FFFF, 0, INTA, 0 },
|
||||
Package(){0x0004FFFF, 1, INTB, 0 },
|
||||
Package(){0x0004FFFF, 2, INTC, 0 },
|
||||
Package(){0x0004FFFF, 3, INTD, 0 },
|
||||
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||
/* Package(){0x0005FFFF, 0, INTB, 0 }, */
|
||||
/* Package(){0x0005FFFF, 1, INTC, 0 }, */
|
||||
/* Package(){0x0005FFFF, 2, INTD, 0 }, */
|
||||
/* Package(){0x0005FFFF, 3, INTA, 0 }, */
|
||||
/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
|
||||
Package(){0x0006FFFF, 0, INTC, 0 },
|
||||
Package(){0x0006FFFF, 1, INTD, 0 },
|
||||
Package(){0x0006FFFF, 2, INTA, 0 },
|
||||
Package(){0x0006FFFF, 3, INTB, 0 },
|
||||
/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
|
||||
Package(){0x0007FFFF, 0, INTD, 0 },
|
||||
Package(){0x0007FFFF, 1, INTA, 0 },
|
||||
Package(){0x0007FFFF, 2, INTB, 0 },
|
||||
Package(){0x0007FFFF, 3, INTC, 0 },
|
||||
|
||||
Package(){0x0009FFFF, 0, INTB, 0 },
|
||||
Package(){0x0009FFFF, 1, INTC, 0 },
|
||||
Package(){0x0009FFFF, 2, INTD, 0 },
|
||||
Package(){0x0009FFFF, 3, INTA, 0 },
|
||||
|
||||
Package(){0x000AFFFF, 0, INTC, 0 },
|
||||
Package(){0x000AFFFF, 1, INTD, 0 },
|
||||
Package(){0x000AFFFF, 2, INTA, 0 },
|
||||
Package(){0x000AFFFF, 3, INTB, 0 },
|
||||
|
||||
Package(){0x000BFFFF, 0, INTD, 0 },
|
||||
Package(){0x000BFFFF, 1, INTA, 0 },
|
||||
Package(){0x000BFFFF, 2, INTB, 0 },
|
||||
Package(){0x000BFFFF, 3, INTC, 0 },
|
||||
|
||||
Package(){0x000CFFFF, 0, INTA, 0 },
|
||||
Package(){0x000CFFFF, 1, INTB, 0 },
|
||||
Package(){0x000CFFFF, 2, INTC, 0 },
|
||||
Package(){0x000CFFFF, 3, INTD, 0 },
|
||||
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
/* SB devices */
|
||||
/* Bus 0, Dev 17 - SATA controller #2 */
|
||||
/* Bus 0, Dev 18 - SATA controller #1 */
|
||||
Package(){0x0011FFFF, 0, INTD, 0 },
|
||||
|
||||
/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
|
||||
* EHCI, dev 18, 19 func 2 */
|
||||
Package(){0x0012FFFF, 0, INTC, 0 },
|
||||
Package(){0x0012FFFF, 1, INTB, 0 },
|
||||
|
||||
Package(){0x0013FFFF, 0, INTC, 0 },
|
||||
Package(){0x0013FFFF, 1, INTB, 0 },
|
||||
|
||||
Package(){0x0016FFFF, 0, INTC, 0 },
|
||||
Package(){0x0016FFFF, 1, INTB, 0 },
|
||||
|
||||
/* Package(){0x0014FFFF, 1, INTA, 0 }, */
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
|
||||
Package(){0x0014FFFF, 0, INTA, 0 },
|
||||
Package(){0x0014FFFF, 1, INTB, 0 },
|
||||
Package(){0x0014FFFF, 2, INTC, 0 },
|
||||
Package(){0x0014FFFF, 3, INTD, 0 },
|
||||
|
||||
Package(){0x0015FFFF, 0, INTA, 0 },
|
||||
Package(){0x0015FFFF, 1, INTB, 0 },
|
||||
Package(){0x0015FFFF, 2, INTC, 0 },
|
||||
Package(){0x0015FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APR0, Package(){
|
||||
/* NB devices in APIC mode */
|
||||
/* Bus 0, Dev 0 - RS780 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
Package(){0x0001FFFF, 0, 0, 18 },
|
||||
Package(){0x0001FFFF, 1, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
|
||||
Package(){0x0002FFFF, 0, 0, 18 },
|
||||
/* Package(){0x0002FFFF, 1, 0, 19 }, */
|
||||
/* Package(){0x0002FFFF, 2, 0, 16 }, */
|
||||
/* Package(){0x0002FFFF, 3, 0, 17 }, */
|
||||
|
||||
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
|
||||
Package(){0x0003FFFF, 0, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||
Package(){0x0004FFFF, 0, 0, 16 },
|
||||
/* Package(){0x0004FFFF, 1, 0, 17 }, */
|
||||
/* Package(){0x0004FFFF, 2, 0, 18 }, */
|
||||
/* Package(){0x0004FFFF, 3, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||
/* Package(){0x0005FFFF, 0, 0, 17 }, */
|
||||
/* Package(){0x0005FFFF, 1, 0, 18 }, */
|
||||
/* Package(){0x0005FFFF, 2, 0, 19 }, */
|
||||
/* Package(){0x0005FFFF, 3, 0, 16 }, */
|
||||
|
||||
/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
|
||||
/* Package(){0x0006FFFF, 0, 0, 18 }, */
|
||||
/* Package(){0x0006FFFF, 1, 0, 19 }, */
|
||||
/* Package(){0x0006FFFF, 2, 0, 16 }, */
|
||||
/* Package(){0x0006FFFF, 3, 0, 17 }, */
|
||||
|
||||
/* Bus 0, Dev 7 - PCIe Bridge for network card */
|
||||
/* Package(){0x0007FFFF, 0, 0, 19 }, */
|
||||
/* Package(){0x0007FFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x0007FFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x0007FFFF, 3, 0, 18 }, */
|
||||
|
||||
/* Bus 0, Dev 9 - PCIe Bridge for network card */
|
||||
Package(){0x0009FFFF, 0, 0, 17 },
|
||||
/* Package(){0x0009FFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x0009FFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x0009FFFF, 3, 0, 18 }, */
|
||||
/* Bus 0, Dev A - PCIe Bridge for network card */
|
||||
Package(){0x000AFFFF, 0, 0, 18 },
|
||||
/* Package(){0x000AFFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x000AFFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x000AFFFF, 3, 0, 18 }, */
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
/* SB devices in APIC mode */
|
||||
/* Bus 0, Dev 17 - SATA controller #2 */
|
||||
/* Bus 0, Dev 18 - SATA controller #1 */
|
||||
Package(){0x0011FFFF, 0, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
|
||||
* EHCI, dev 18, 19 func 2 */
|
||||
Package(){0x0012FFFF, 0, 0, 18 },
|
||||
Package(){0x0012FFFF, 1, 0, 17 },
|
||||
/* Package(){0x0012FFFF, 2, 0, 18 }, */
|
||||
|
||||
Package(){0x0013FFFF, 0, 0, 18 },
|
||||
Package(){0x0013FFFF, 1, 0, 17 },
|
||||
/* Package(){0x0013FFFF, 2, 0, 16 }, */
|
||||
|
||||
/* Package(){0x00140000, 0, 0, 16 }, */
|
||||
|
||||
Package(){0x0016FFFF, 0, 0, 18 },
|
||||
Package(){0x0016FFFF, 1, 0, 17 },
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
Package(){0x0014FFFF, 1, 0, 17 },
|
||||
Package(){0x0014FFFF, 2, 0, 18 },
|
||||
Package(){0x0014FFFF, 3, 0, 19 },
|
||||
/* Package(){0x00140004, 2, 0, 18 }, */
|
||||
/* Package(){0x00140004, 3, 0, 19 }, */
|
||||
/* Package(){0x00140005, 1, 0, 17 }, */
|
||||
/* Package(){0x00140006, 1, 0, 17 }, */
|
||||
|
||||
/* TODO: pcie */
|
||||
Package(){0x0015FFFF, 0, 0, 16 },
|
||||
Package(){0x0015FFFF, 1, 0, 17 },
|
||||
Package(){0x0015FFFF, 2, 0, 18 },
|
||||
Package(){0x0015FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PR1, Package(){
|
||||
/* Internal graphics - RS780 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, INTA, 0 },
|
||||
Package(){0x0005FFFF, 1, INTB, 0 },
|
||||
Package(){0x0005FFFF, 2, INTC, 0 },
|
||||
Package(){0x0005FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APR1, Package(){
|
||||
/* Internal graphics - RS780 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, 0, 18 },
|
||||
Package(){0x0005FFFF, 1, 0, 19 },
|
||||
/* Package(){0x0005FFFF, 2, 0, 20 }, */
|
||||
/* Package(){0x0005FFFF, 3, 0, 17 }, */
|
||||
})
|
||||
|
||||
Name(PS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, 0, 16 },
|
||||
Package(){0x0000FFFF, 1, 0, 17 },
|
||||
Package(){0x0000FFFF, 2, 0, 18 },
|
||||
Package(){0x0000FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PS5, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 5 */
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
Name(APS5, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 5 */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
|
||||
Name(PS6, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 6 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APS6, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 6 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS7, Package(){
|
||||
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
Name(APS7, Package(){
|
||||
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
|
||||
Package(){0x0000FFFF, 0, 0, 19 },
|
||||
Package(){0x0000FFFF, 1, 0, 16 },
|
||||
Package(){0x0000FFFF, 2, 0, 17 },
|
||||
Package(){0x0000FFFF, 3, 0, 18 },
|
||||
})
|
||||
|
||||
Name(PS9, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 9 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
Name(APS9, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 9 */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
|
||||
Name(PSa, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
Name(APSa, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PE0, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APE0, Package(){
|
||||
/* PCIe slot - Hooked to PCIe */
|
||||
Package(){0x0000FFFF, 0, 0, 16 },
|
||||
Package(){0x0000FFFF, 1, 0, 17 },
|
||||
Package(){0x0000FFFF, 2, 0, 18 },
|
||||
Package(){0x0000FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PE1, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
Name(APE1, Package(){
|
||||
/* PCIe slot - Hooked to PCIe */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
|
||||
Name(PE2, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APE2, Package(){
|
||||
/* PCIe slot - Hooked to PCIe */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PE3, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
Name(APE3, Package(){
|
||||
/* PCIe slot - Hooked to PCIe */
|
||||
Package(){0x0000FFFF, 0, 0, 19 },
|
||||
Package(){0x0000FFFF, 1, 0, 16 },
|
||||
Package(){0x0000FFFF, 2, 0, 17 },
|
||||
Package(){0x0000FFFF, 3, 0, 18 },
|
||||
})
|
||||
|
||||
Name(PCIB, Package(){
|
||||
/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
|
||||
Package(){0x0005FFFF, 0, 0, 0x14 },
|
||||
Package(){0x0005FFFF, 1, 0, 0x15 },
|
||||
Package(){0x0005FFFF, 2, 0, 0x16 },
|
||||
Package(){0x0005FFFF, 3, 0, 0x17 },
|
||||
Package(){0x0006FFFF, 0, 0, 0x15 },
|
||||
Package(){0x0006FFFF, 1, 0, 0x16 },
|
||||
Package(){0x0006FFFF, 2, 0, 0x17 },
|
||||
Package(){0x0006FFFF, 3, 0, 0x14 },
|
||||
Package(){0x0007FFFF, 0, 0, 0x16 },
|
||||
Package(){0x0007FFFF, 1, 0, 0x17 },
|
||||
Package(){0x0007FFFF, 2, 0, 0x14 },
|
||||
Package(){0x0007FFFF, 3, 0, 0x15 },
|
||||
})
|
||||
}
|
||||
@@ -1,145 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
|
||||
/*
|
||||
Scope (_SB) {
|
||||
Device(PCI0) {
|
||||
Device(SATA) {
|
||||
Name(_ADR, 0x00110000)
|
||||
#include "sata.asl"
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
Name(STTM, Buffer(20) {
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x1f, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
/* Start by clearing the PhyRdyChg bits */
|
||||
Method(_INI) {
|
||||
\_GPE._L1F()
|
||||
}
|
||||
|
||||
Device(PMRY)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(PMST) {
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P0IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
}/* end of PMST */
|
||||
|
||||
Device(PSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P1IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of PSLA */
|
||||
} /* end of PMRY */
|
||||
|
||||
|
||||
Device(SEDY)
|
||||
{
|
||||
Name(_ADR, 1) /* IDE Scondary Channel */
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(SMST)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P2IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SMST */
|
||||
|
||||
Device(SSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P3IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SSLA */
|
||||
} /* end of SEDY */
|
||||
|
||||
/* SATA Hot Plug Support */
|
||||
Scope(\_GPE) {
|
||||
Method(_L1F,0x0,NotSerialized) {
|
||||
if (\_SB.P0PR) {
|
||||
if (LGreater(\_SB.P0IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P0PR)
|
||||
}
|
||||
|
||||
if (\_SB.P1PR) {
|
||||
if (LGreater(\_SB.P1IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P1PR)
|
||||
}
|
||||
|
||||
if (\_SB.P2PR) {
|
||||
if (LGreater(\_SB.P2IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P2PR)
|
||||
}
|
||||
|
||||
if (\_SB.P3PR) {
|
||||
if (LGreater(\_SB.P3IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P3PR)
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1,158 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
/*
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
|
||||
)
|
||||
{
|
||||
#include "usb.asl"
|
||||
}
|
||||
*/
|
||||
Method(UCOC, 0) {
|
||||
Sleep(20)
|
||||
Store(0x13,CMTI)
|
||||
Store(0,GPSL)
|
||||
}
|
||||
|
||||
/* USB Port 0 overcurrent uses Gpm 0 */
|
||||
If(LLessEqual(UOM0,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L13) {
|
||||
UCOC()
|
||||
if(LEqual(GPB0,PLC0)) {
|
||||
Not(PLC0,PLC0)
|
||||
Store(PLC0, \_SB.PT0D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 1 overcurrent uses Gpm 1 */
|
||||
If (LLessEqual(UOM1,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L14) {
|
||||
UCOC()
|
||||
if (LEqual(GPB1,PLC1)) {
|
||||
Not(PLC1,PLC1)
|
||||
Store(PLC1, \_SB.PT1D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 2 overcurrent uses Gpm 2 */
|
||||
If (LLessEqual(UOM2,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L15) {
|
||||
UCOC()
|
||||
if (LEqual(GPB2,PLC2)) {
|
||||
Not(PLC2,PLC2)
|
||||
Store(PLC2, \_SB.PT2D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 3 overcurrent uses Gpm 3 */
|
||||
If (LLessEqual(UOM3,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L16) {
|
||||
UCOC()
|
||||
if (LEqual(GPB3,PLC3)) {
|
||||
Not(PLC3,PLC3)
|
||||
Store(PLC3, \_SB.PT3D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 4 overcurrent uses Gpm 4 */
|
||||
If (LLessEqual(UOM4,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L19) {
|
||||
UCOC()
|
||||
if (LEqual(GPB4,PLC4)) {
|
||||
Not(PLC4,PLC4)
|
||||
Store(PLC4, \_SB.PT4D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 5 overcurrent uses Gpm 5 */
|
||||
If (LLessEqual(UOM5,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L1A) {
|
||||
UCOC()
|
||||
if (LEqual(GPB5,PLC5)) {
|
||||
Not(PLC5,PLC5)
|
||||
Store(PLC5, \_SB.PT5D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 6 overcurrent uses Gpm 6 */
|
||||
If (LLessEqual(UOM6,9)) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1C) { */
|
||||
Method (_L06) {
|
||||
UCOC()
|
||||
if (LEqual(GPB6,PLC6)) {
|
||||
Not(PLC6,PLC6)
|
||||
Store(PLC6, \_SB.PT6D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 7 overcurrent uses Gpm 7 */
|
||||
If (LLessEqual(UOM7,9)) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1D) { */
|
||||
Method (_L07) {
|
||||
UCOC()
|
||||
if (LEqual(GPB7,PLC7)) {
|
||||
Not(PLC7,PLC7)
|
||||
Store(PLC7, \_SB.PT7D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 8 overcurrent uses Gpm 8 */
|
||||
If (LLessEqual(UOM8,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L17) {
|
||||
if (LEqual(G8IS,PLC8)) {
|
||||
Not(PLC8,PLC8)
|
||||
Store(PLC8, \_SB.PT8D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 9 overcurrent uses Gpm 9 */
|
||||
If (LLessEqual(UOM9,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L0E) {
|
||||
if (LEqual(G9IS,0)) {
|
||||
Store(1,\_SB.PT9D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1,44 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
/* create all subtables for processors */
|
||||
current = acpi_create_madt_lapics(current);
|
||||
|
||||
/* Write SB800 IOAPIC, only one */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
|
||||
IO_APIC_ADDR, 0);
|
||||
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 0, 2, 0);
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 9, 9, 0xF);
|
||||
/* 0: mean bus 0--->ISA */
|
||||
/* 0: PIC 0 */
|
||||
/* 2: APIC 2 */
|
||||
/* 5 mean: 0101 --> Edge-triggered, Active high */
|
||||
|
||||
/* create all subtables for processors */
|
||||
/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
|
||||
/* 1: LINT1 connect to NMI */
|
||||
|
||||
return current;
|
||||
}
|
||||
@@ -1 +0,0 @@
|
||||
Category: eval
|
||||
@@ -1,52 +0,0 @@
|
||||
entries
|
||||
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
#392 3 r 0 unused
|
||||
395 1 e 1 hw_scrubber
|
||||
396 1 e 1 interleave_chip_selects
|
||||
397 2 e 8 max_mem_clock
|
||||
399 1 e 2 multi_core
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
440 4 e 9 slow_cpu
|
||||
444 1 e 1 nmi
|
||||
445 1 e 1 gart
|
||||
456 1 e 1 ECC_memory
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
6 5 Notice
|
||||
6 6 Info
|
||||
6 7 Debug
|
||||
6 8 Spew
|
||||
8 0 400Mhz
|
||||
8 1 333Mhz
|
||||
8 2 266Mhz
|
||||
8 3 200Mhz
|
||||
9 0 off
|
||||
9 1 87.5%
|
||||
9 2 75.0%
|
||||
9 3 62.5%
|
||||
9 4 50.0%
|
||||
9 5 37.5%
|
||||
9 6 25.0%
|
||||
9 7 12.5%
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
@@ -1,95 +0,0 @@
|
||||
# sample config for amd/bimini_fam10
|
||||
chip northbridge/amd/amdfam10/root_complex
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_ASB2 #L1 and DDR3
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device domain 0 on
|
||||
subsystemid 0x1022 0x3060 inherit
|
||||
chip northbridge/amd/amdfam10
|
||||
device pci 18.0 on # northbridge
|
||||
chip southbridge/amd/rs780
|
||||
device pci 0.0 on end # HT 0x9600
|
||||
device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
|
||||
device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603
|
||||
device pci 3.0 off end # PCIE P2P bridge 0x960b
|
||||
device pci 4.0 on end # PCIE P2P bridge 0x9604
|
||||
device pci 5.0 on end # PCIE P2P bridge 0x9605
|
||||
device pci 6.0 on end # PCIE P2P bridge 0x9606
|
||||
device pci 7.0 on end # PCIE P2P bridge 0x9607
|
||||
device pci 8.0 off end # NB/SB Link P2P bridge
|
||||
device pci 9.0 on end #
|
||||
device pci a.0 off end #
|
||||
register "gppsb_configuration" = "4" # Configuration E
|
||||
register "gpp_configuration" = "2" # Configuration C
|
||||
register "port_enable" = "0x6fc"
|
||||
register "gfx_dev2_dev3" = "1"
|
||||
register "gfx_dual_slot" = "0"
|
||||
register "gfx_lane_reversal" = "0"
|
||||
register "gfx_tmds" = "0"
|
||||
register "gfx_compliance" = "0"
|
||||
register "gfx_reconfiguration" = "1"
|
||||
register "gfx_link_width" = "0"
|
||||
end
|
||||
chip southbridge/amd/sb800 # it is under NB/SB Link, but on the same pci bus
|
||||
device pci 11.0 on end # SATA
|
||||
device pci 12.0 on end # USB
|
||||
device pci 12.2 on end # USB
|
||||
device pci 13.0 on end # USB
|
||||
device pci 13.2 on end # USB
|
||||
device pci 14.0 on # SM
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
end # SM
|
||||
device pci 14.1 on end # IDE 0x439c
|
||||
device pci 14.2 on end # HDA 0x4383
|
||||
device pci 14.3 on end # LPC 0x439d
|
||||
device pci 14.4 off end # PCI 0x4384 # PCI-b conflict with GPIO.
|
||||
device pci 14.5 on end # USB 2
|
||||
device pci 14.6 on end # Gec
|
||||
device pci 15.0 on end # PCIe 0
|
||||
device pci 15.1 on end # PCIe 1
|
||||
device pci 15.2 on end # PCIe 2
|
||||
device pci 15.3 on end # PCIe 3
|
||||
device pci 16.0 on end # USB
|
||||
device pci 16.2 on end # USB
|
||||
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
|
||||
register "gpp_configuration" = "4"
|
||||
end #southbridge/amd/sb800
|
||||
end # device pci 18.0
|
||||
|
||||
device pci 18.0 on end
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
device pci 18.4 on end
|
||||
end
|
||||
end #domain
|
||||
#for node 32 to node 63
|
||||
# device domain 0 on
|
||||
# chip northbridge/amd/amdfam10
|
||||
# device pci 00.0 on end# northbridge
|
||||
# device pci 00.0 on end
|
||||
# device pci 00.0 on end
|
||||
# device pci 00.0 on end
|
||||
# device pci 00.1 on end
|
||||
# device pci 00.2 on end
|
||||
# device pci 00.3 on end
|
||||
# device pci 00.4 on end
|
||||
# device pci 00.5 on end
|
||||
# end
|
||||
# end #domain
|
||||
|
||||
end
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,43 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/pci.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <cpu/amd/multicore.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
/* Global variables for MB layouts and these will be shared by irqtable mptable
|
||||
* and acpi_tables busnum is default.
|
||||
*/
|
||||
u32 apicid_sb800;
|
||||
|
||||
void get_bus_conf(void)
|
||||
{
|
||||
u32 apicid_base;
|
||||
|
||||
get_default_pci1234(1);
|
||||
|
||||
sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
|
||||
|
||||
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
if (CONFIG(LOGICAL_CPUS))
|
||||
apicid_base = get_apicid_base(1);
|
||||
else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
apicid_sb800 = apicid_base + 0;
|
||||
}
|
||||
@@ -1,101 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
|
||||
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
|
||||
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
|
||||
u8 slot, u8 rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
u32 slot_num;
|
||||
u8 *v;
|
||||
|
||||
u8 sum = 0;
|
||||
int i;
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be between 0xf0000 & 0x100000 */
|
||||
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (u8 *) (addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
pirq->rtr_bus = pirq_router_bus;
|
||||
pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
pirq->rtr_vendor = 0x1002;
|
||||
pirq->rtr_device = 0x4384;
|
||||
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *)(&pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
|
||||
/* pci bridge */
|
||||
write_pirq_info(pirq_info, pirq_router_bus, PCI_DEVFN(0x14, 4),
|
||||
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
|
||||
0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "write_pirq_routing_table done.\n");
|
||||
|
||||
return (unsigned long)pirq_info;
|
||||
}
|
||||
@@ -1,79 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <southbridge/amd/common/amd_defs.h>
|
||||
#include <southbridge/amd/sb800/sb800.h>
|
||||
#include <southbridge/amd/rs780/rs780.h>
|
||||
|
||||
/* GPIO6. */
|
||||
static void enable_int_gfx(void)
|
||||
{
|
||||
u8 byte;
|
||||
|
||||
volatile u8 *gpio_reg;
|
||||
|
||||
pm_iowrite(0xEA, 0x01); /* disable the PCIB */
|
||||
/* Disable Gec */
|
||||
byte = pm_ioread(0xF6);
|
||||
byte |= 1;
|
||||
pm_iowrite(0xF6, byte);
|
||||
/* make sure the fed80000 is accessible */
|
||||
byte = pm_ioread(0x24);
|
||||
byte |= 1;
|
||||
pm_iowrite(0x24, byte);
|
||||
|
||||
gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0xD00; /* IoMux Register */
|
||||
|
||||
*(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
|
||||
*(gpio_reg + 170) = 0x1; /* gpio_gate */
|
||||
|
||||
gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0x100; /* GPIO Registers */
|
||||
|
||||
*(gpio_reg + 0x6) = 0x8;
|
||||
*(gpio_reg + 170) = 0x0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Bimini uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
|
||||
* pull it up before training the slot.
|
||||
*
|
||||
* Old comment says: GPIO 50h to reset PCIe slot.
|
||||
***/
|
||||
|
||||
int is_dev3_present(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*************************************************
|
||||
* enable the dedicated function in bimini board.
|
||||
* This function called early than rs780_enable.
|
||||
*************************************************/
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
printk(BIOS_INFO, "Mainboard BIMINI Enable. dev=0x%p\n", dev);
|
||||
|
||||
set_pcie_dereset();
|
||||
enable_int_gfx();
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
@@ -1,84 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/pci.h>
|
||||
#include <arch/io.h>
|
||||
#include <stdint.h>
|
||||
#include <southbridge/amd/sb800/sb800.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
extern u32 apicid_sb800;
|
||||
|
||||
u8 intr_data[] = {
|
||||
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
|
||||
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
|
||||
[0x10] = 0x1F,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x10,0x11,0x12,0x13
|
||||
};
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
u32 dword;
|
||||
u8 byte;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
|
||||
dword = 0;
|
||||
dword = pm_ioread(0x34) & 0xF0;
|
||||
dword |= (pm_ioread(0x35) & 0xFF) << 8;
|
||||
dword |= (pm_ioread(0x36) & 0xFF) << 16;
|
||||
dword |= (pm_ioread(0x37) & 0xFF) << 24;
|
||||
smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword);
|
||||
|
||||
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
|
||||
outb(byte | 0x80, 0xC00);
|
||||
outb(intr_data[byte], 0xC01);
|
||||
}
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
@@ -1,274 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <commonlib/helpers.h>
|
||||
#include <northbridge/amd/amdfam10/amdfam10.h>
|
||||
|
||||
void setup_mb_resource_map(void)
|
||||
{
|
||||
static const unsigned int register_values[] = {
|
||||
/* Careful set limit registers before base registers which contain the enables */
|
||||
/* DRAM Limit i Registers
|
||||
* F1:0x44 i = 0
|
||||
* F1:0x4C i = 1
|
||||
* F1:0x54 i = 2
|
||||
* F1:0x5C i = 3
|
||||
* F1:0x64 i = 4
|
||||
* F1:0x6C i = 5
|
||||
* F1:0x74 i = 6
|
||||
* F1:0x7C i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 3] Reserved
|
||||
* [10: 8] Interleave select
|
||||
* specifies the values of A[14:12] to use with interleave enable.
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Limit Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40 bit address
|
||||
* that define the end of the DRAM region.
|
||||
*/
|
||||
/* Don't touch it, we need it for CONFIG_CAR_FAM10 */
|
||||
ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001,
|
||||
ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002,
|
||||
ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003,
|
||||
ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004,
|
||||
ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005,
|
||||
ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006,
|
||||
ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
|
||||
/* DRAM Base i Registers
|
||||
* F1:0x40 i = 0
|
||||
* F1:0x48 i = 1
|
||||
* F1:0x50 i = 2
|
||||
* F1:0x58 i = 3
|
||||
* F1:0x60 i = 4
|
||||
* F1:0x68 i = 5
|
||||
* F1:0x70 i = 6
|
||||
* F1:0x78 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 7: 2] Reserved
|
||||
* [10: 8] Interleave Enable
|
||||
* 000 = No interleave
|
||||
* 001 = Interleave on A[12] (2 nodes)
|
||||
* 010 = reserved
|
||||
* 011 = Interleave on A[12] and A[14] (4 nodes)
|
||||
* 100 = reserved
|
||||
* 101 = reserved
|
||||
* 110 = reserved
|
||||
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
|
||||
* [15:11] Reserved
|
||||
* [13:16] DRAM Base Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40-bit address
|
||||
* that define the start of the DRAM region.
|
||||
*/
|
||||
|
||||
/* don't touch it, we need it for CONFIG_CAR_FAM10 */
|
||||
ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
* F1:0x8C i = 1
|
||||
* F1:0x94 i = 2
|
||||
* F1:0x9C i = 3
|
||||
* F1:0xA4 i = 4
|
||||
* F1:0xAC i = 5
|
||||
* F1:0xB4 i = 6
|
||||
* F1:0xBC i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Reserved
|
||||
* [ 6: 6] Reserved
|
||||
* [ 7: 7] Non-Posted
|
||||
* 0 = CPU writes may be posted
|
||||
* 1 = CPU writes must be non-posted
|
||||
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
|
||||
* This field defines the upp address bits of a 40-bit address that
|
||||
* defines the end of a memory-mapped I/O region n
|
||||
*/
|
||||
ADDRMAP_REG(0x84), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x8C), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x94), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x9C), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xA4), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xAC), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Base i Registers
|
||||
* F1:0x80 i = 0
|
||||
* F1:0x88 i = 1
|
||||
* F1:0x90 i = 2
|
||||
* F1:0x98 i = 3
|
||||
* F1:0xA0 i = 4
|
||||
* F1:0xA8 i = 5
|
||||
* F1:0xB0 i = 6
|
||||
* F1:0xB8 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Cpu Disable
|
||||
* 0 = Cpu can use this I/O range
|
||||
* 1 = Cpu requests do not use this I/O range
|
||||
* [ 3: 3] Lock
|
||||
* 0 = base/limit registers i are read/write
|
||||
* 1 = base/limit registers i are read-only
|
||||
* [ 7: 4] Reserved
|
||||
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
|
||||
* This field defines the upper address bits of a 40bit address
|
||||
* that defines the start of memory-mapped I/O region i
|
||||
*/
|
||||
ADDRMAP_REG(0x80), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x88), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x90), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x98), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
|
||||
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
* F1:0xCC i = 1
|
||||
* F1:0xD4 i = 2
|
||||
* F1:0xDC i = 3
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = reserved
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Limit Address i
|
||||
* This field defines the end of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000,
|
||||
ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000,
|
||||
ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
|
||||
|
||||
/* PCI I/O Base i Registers
|
||||
* F1:0xC0 i = 0
|
||||
* F1:0xC8 i = 1
|
||||
* F1:0xD0 i = 2
|
||||
* F1:0xD8 i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 3: 2] Reserved
|
||||
* [ 4: 4] VGA Enable
|
||||
* 0 = VGA matches Disabled
|
||||
* 1 = matches all address < 64K and where A[9:0] is in the
|
||||
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
|
||||
* [ 5: 5] ISA Enable
|
||||
* 0 = ISA matches Disabled
|
||||
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
|
||||
* from matching agains this base/limit pair
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Base i
|
||||
* This field defines the start of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000,
|
||||
ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000,
|
||||
ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
|
||||
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
* F1:0xE8 i = 2
|
||||
* F1:0xEC i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Device Number Compare Enable
|
||||
* 0 = The ranges are based on bus number
|
||||
* 1 = The ranges are ranges of devices on bus 0
|
||||
* [ 3: 3] Reserved
|
||||
* [ 6: 4] Destination Node
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 7] Reserved
|
||||
* [ 9: 8] Destination Link
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 - Reserved
|
||||
* [15:10] Reserved
|
||||
* [23:16] Bus Number Base i
|
||||
* This field defines the lowest bus number in configuration region i
|
||||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration regin i
|
||||
*/
|
||||
/* AMD 8111 on link0 of CPU 0 */
|
||||
ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000,
|
||||
ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000,
|
||||
ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
|
||||
};
|
||||
|
||||
int max;
|
||||
max = ARRAY_SIZE(register_values);
|
||||
setup_resource_map(register_values, max);
|
||||
}
|
||||
@@ -1,219 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#define SYSTEM_TYPE 1 /* SERVER = 0, DESKTOP = 1, MOBILE = 2 */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <console/console.h>
|
||||
#include <timestamp.h>
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include <cpu/amd/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <cpu/amd/car.h>
|
||||
#include <southbridge/amd/common/reset.h>
|
||||
#include <southbridge/amd/sb800/smbus.h>
|
||||
#include <northbridge/amd/amdfam10/raminit.h>
|
||||
#include <northbridge/amd/amdht/ht_wrapper.h>
|
||||
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
|
||||
#include <arch/early_variables.h>
|
||||
#include <cbmem.h>
|
||||
#include <southbridge/amd/rs780/rs780.h>
|
||||
#include "southbridge/amd/sb800/early_setup.c"
|
||||
#include <spd.h>
|
||||
|
||||
#include "cpu/amd/quadcore/quadcore.c"
|
||||
|
||||
int spd_read_byte(unsigned int device, unsigned int address);
|
||||
|
||||
|
||||
int spd_read_byte(u32 device, u32 address)
|
||||
{
|
||||
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
|
||||
}
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
struct sys_info *sysinfo = get_sysinfo();
|
||||
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
|
||||
u32 bsp_apicid = 0, val;
|
||||
msr_t msr;
|
||||
|
||||
timestamp_init(timestamp_get());
|
||||
timestamp_add_now(TS_START_ROMSTAGE);
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
/* mov bsp to bus 0xff when > 8 nodes */
|
||||
set_bsp_node_CHtExtNodeCfgEn();
|
||||
enumerate_ht_chain();
|
||||
|
||||
/* enable port80 decoding and southbridge poweron init */
|
||||
sb800_lpc_port80();
|
||||
inb(0x80); /* Wait sometime before post to port80, otherwise reset was needed. */
|
||||
}
|
||||
|
||||
post_code(0x30);
|
||||
|
||||
if (bist == 0) {
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
|
||||
/* All cores run this but the BSP(node0,core0) is the only core that returns. */
|
||||
}
|
||||
|
||||
post_code(0x32);
|
||||
|
||||
enable_rs780_dev8();
|
||||
sb800_lpc_init();
|
||||
|
||||
console_init();
|
||||
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
/* Load MPB */
|
||||
val = cpuid_eax(1);
|
||||
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
|
||||
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
|
||||
printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
|
||||
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
|
||||
|
||||
/* Setup sysinfo defaults */
|
||||
set_sysinfo_in_ram(0);
|
||||
|
||||
update_microcode(val);
|
||||
|
||||
post_code(0x33);
|
||||
|
||||
cpuSetAMDMSR(0);
|
||||
post_code(0x34);
|
||||
|
||||
amd_ht_init(sysinfo);
|
||||
post_code(0x35);
|
||||
|
||||
/* Setup nodes PCI space and start core 0 AP init. */
|
||||
finalize_node_setup(sysinfo);
|
||||
|
||||
/* Setup any mainboard PCI settings etc. */
|
||||
setup_mb_resource_map();
|
||||
post_code(0x36);
|
||||
|
||||
/* wait for all the APs core0 started by finalize_node_setup. */
|
||||
/* FIXME: A bunch of cores are going to start output to serial at once.
|
||||
It would be nice to fixup prink spinlocks for ROM XIP mode.
|
||||
I think it could be done by putting the spinlock flag in the cache
|
||||
of the BSP located right after sysinfo.
|
||||
*/
|
||||
wait_all_core0_started();
|
||||
|
||||
#if CONFIG(LOGICAL_CPUS)
|
||||
/* Core0 on each node is configured. Now setup any additional cores. */
|
||||
printk(BIOS_DEBUG, "start_other_cores()\n");
|
||||
start_other_cores(bsp_apicid);
|
||||
post_code(0x37);
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
#endif
|
||||
|
||||
post_code(0x38);
|
||||
|
||||
/* run _early_setup before soft-reset. */
|
||||
rs780_early_setup();
|
||||
sb800_early_setup();
|
||||
|
||||
#if CONFIG(SET_FIDVID)
|
||||
msr = rdmsr(MSR_COFVID_STS);
|
||||
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
|
||||
|
||||
/* FIXME: The sb fid change may survive the warm reset and only
|
||||
need to be done once.*/
|
||||
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
|
||||
|
||||
post_code(0x39);
|
||||
|
||||
if (!warm_reset_detect(0)) { /* BSP is node 0 */
|
||||
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
|
||||
} else {
|
||||
init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */
|
||||
}
|
||||
|
||||
post_code(0x3A);
|
||||
|
||||
/* show final fid and vid */
|
||||
msr = rdmsr(MSR_COFVID_STS);
|
||||
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
|
||||
#endif
|
||||
|
||||
rs780_htinit();
|
||||
|
||||
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
|
||||
if (!warm_reset_detect(0)) {
|
||||
printk(BIOS_INFO, "...WARM RESET...\n\n\n");
|
||||
soft_reset();
|
||||
die("After soft_reset - shouldn't see this message!!!\n");
|
||||
}
|
||||
|
||||
post_code(0x3B);
|
||||
|
||||
/* It's the time to set ctrl in sysinfo now; */
|
||||
printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
|
||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
||||
|
||||
post_code(0x40);
|
||||
|
||||
raminit_amdmct(sysinfo);
|
||||
|
||||
cbmem_initialize_empty();
|
||||
post_code(0x41);
|
||||
|
||||
amdmct_cbmem_store_info(sysinfo);
|
||||
|
||||
sb800_before_pci_init();
|
||||
|
||||
post_code(0x42);
|
||||
}
|
||||
|
||||
/**
|
||||
* BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
|
||||
* Description:
|
||||
* This routine is called every time a non-coherent chain is processed.
|
||||
* BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
|
||||
* swap list. The first part of the list controls the BUID assignment and the
|
||||
* second part of the list provides the device to device linking. Device orientation
|
||||
* can be detected automatically, or explicitly. See documentation for more details.
|
||||
*
|
||||
* Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
|
||||
* based on each device's unit count.
|
||||
*
|
||||
* Parameters:
|
||||
* @param[in] node = The node on which this chain is located
|
||||
* @param[in] link = The link on the host for this chain
|
||||
* @param[out] List = supply a pointer to a list
|
||||
*/
|
||||
BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
|
||||
{
|
||||
static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
|
||||
/* If the BUID was adjusted in early_ht we need to do the manual override */
|
||||
if ((node == 0) && (link == 0)) { /* BSP SB link */
|
||||
*List = swaplist;
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -1,58 +0,0 @@
|
||||
if BOARD_AMD_MAHOGANY_FAM10
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS
|
||||
def_bool y
|
||||
select CPU_AMD_SOCKET_AM2R2
|
||||
select DIMM_DDR2
|
||||
select DIMM_REGISTERED
|
||||
select NORTHBRIDGE_AMD_AMDFAM10
|
||||
select SOUTHBRIDGE_AMD_RS780
|
||||
select SOUTHBRIDGE_AMD_SB700
|
||||
select SUPERIO_ITE_IT8718F
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
select LIFT_BSP_APIC_ID
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_1024
|
||||
select ENABLE_APIC_EXT_ID
|
||||
select GFXUMA
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default amd/mahogany_fam10
|
||||
|
||||
config APIC_ID_OFFSET
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "Mahogany (Fam10)"
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 8
|
||||
|
||||
config MAX_PHYSICAL_CPUS
|
||||
int
|
||||
default 2
|
||||
|
||||
config HT_CHAIN_END_UNITID_BASE
|
||||
hex
|
||||
default 0x1
|
||||
|
||||
config HT_CHAIN_UNITID_BASE
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 11
|
||||
|
||||
config VGA_BIOS_ID
|
||||
string
|
||||
default "1002,9615"
|
||||
|
||||
endif # BOARD_AMD_MAHOGANY_FAM10
|
||||
@@ -1,2 +0,0 @@
|
||||
config BOARD_AMD_MAHOGANY_FAM10
|
||||
bool "Mahogany (Fam10)"
|
||||
@@ -1,16 +0,0 @@
|
||||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
|
||||
romstage-y += resourcemap.c
|
||||
|
||||
ramstage-y += get_bus_conf.c
|
||||
@@ -1,80 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* This file defines the processor and performance state capability
|
||||
* for each core in the system. It is included into the DSDT for each
|
||||
* core. It assumes that each core of the system has the same performance
|
||||
* characteristics.
|
||||
*/
|
||||
/*
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001)
|
||||
{
|
||||
Scope (\_PR) {
|
||||
Device (CPU0) {
|
||||
Name (_HID, "ACPI0007")
|
||||
Name (_UID, 0)
|
||||
#include "cpstate.asl"
|
||||
}
|
||||
Device (CPU1) {
|
||||
Name (_HID, "ACPI0007")
|
||||
Name (_UID, 1)
|
||||
#include "cpstate.asl"
|
||||
}
|
||||
Device (CPU2) {
|
||||
Name (_HID, "ACPI0007")
|
||||
Name (_UID, 2)
|
||||
#include "cpstate.asl"
|
||||
}
|
||||
Device (CPU3) {
|
||||
Name (_HID, "ACPI0007")
|
||||
Name (_UID, 3)
|
||||
#include "cpstate.asl"
|
||||
}
|
||||
}
|
||||
*/
|
||||
/* P-state support: The maximum number of P-states supported by the */
|
||||
/* CPUs we'll use is 6. */
|
||||
/* Get from AMI BIOS. */
|
||||
Name(_PSS, Package(){
|
||||
Package ()
|
||||
{
|
||||
0x00000AF0,
|
||||
0x0000BF81,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000000,
|
||||
0x00000000
|
||||
},
|
||||
|
||||
Package ()
|
||||
{
|
||||
0x00000578,
|
||||
0x000076F2,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000001,
|
||||
0x00000001
|
||||
}
|
||||
})
|
||||
|
||||
Name(_PCT, Package(){
|
||||
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
|
||||
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
|
||||
})
|
||||
|
||||
Method(_PPC, 0){
|
||||
Return(0)
|
||||
}
|
||||
@@ -1,240 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
Scope (_SB) {
|
||||
Device(PCI0) {
|
||||
Device(IDEC) {
|
||||
Name(_ADR, 0x00140001)
|
||||
#include "ide.asl"
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
/* Some timing tables */
|
||||
Name(UDTT, Package(){ /* Udma timing table */
|
||||
120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
|
||||
})
|
||||
|
||||
Name(MDTT, Package(){ /* MWDma timing table */
|
||||
480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
|
||||
})
|
||||
|
||||
Name(POTT, Package(){ /* Pio timing table */
|
||||
600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
|
||||
})
|
||||
|
||||
/* Some timing register value tables */
|
||||
Name(MDRT, Package(){ /* MWDma timing register table */
|
||||
0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
|
||||
})
|
||||
|
||||
Name(PORT, Package(){
|
||||
0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
|
||||
})
|
||||
|
||||
OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
|
||||
Field(ICRG, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
PPTS, 8, /* Primary PIO Slave Timing */
|
||||
PPTM, 8, /* Primary PIO Master Timing */
|
||||
OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
|
||||
PMTM, 8, /* Primary MWDMA Master Timing */
|
||||
OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
|
||||
OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
|
||||
PPSM, 4, /* Primary PIO slave Mode */
|
||||
OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
|
||||
OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
|
||||
PDSM, 4, /* Primary UltraDMA Mode */
|
||||
}
|
||||
|
||||
Method(GTTM, 1) /* get total time*/
|
||||
{
|
||||
Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
|
||||
Increment(Local0)
|
||||
Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
|
||||
Increment(Local1)
|
||||
Return(Multiply(30, Add(Local0, Local1)))
|
||||
}
|
||||
|
||||
Device(PRID)
|
||||
{
|
||||
Name (_ADR, Zero)
|
||||
Method(_GTM, 0)
|
||||
{
|
||||
NAME(OTBF, Buffer(20) { /* out buffer */
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
|
||||
CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
|
||||
CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
|
||||
CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
|
||||
CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
|
||||
|
||||
/* Just return if the channel is disabled */
|
||||
If(And(PPCR, 0x01)) { /* primary PIO control */
|
||||
Return(OTBF)
|
||||
}
|
||||
|
||||
/* Always tell them independent timing available and IOChannelReady used on both drives */
|
||||
Or(BFFG, 0x1A, BFFG)
|
||||
|
||||
Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
|
||||
Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
|
||||
|
||||
If(And(PDCR, 0x01)) { /* It's under UDMA mode */
|
||||
Or(BFFG, 0x01, BFFG)
|
||||
Store(DerefOf(Index(UDTT, PDMM)), DSD0)
|
||||
}
|
||||
Else {
|
||||
Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
|
||||
}
|
||||
|
||||
If(And(PDCR, 0x02)) { /* It's under UDMA mode */
|
||||
Or(BFFG, 0x04, BFFG)
|
||||
Store(DerefOf(Index(UDTT, PDSM)), DSD1)
|
||||
}
|
||||
Else {
|
||||
Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
|
||||
}
|
||||
|
||||
Return(OTBF) /* out buffer */
|
||||
} /* End Method(_GTM) */
|
||||
|
||||
Method(_STM, 3, NotSerialized)
|
||||
{
|
||||
NAME(INBF, Buffer(20) { /* in buffer */
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
|
||||
CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
|
||||
CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
|
||||
CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
|
||||
CreateDwordField(INBF, 16, BFFG) /*buffer flag */
|
||||
|
||||
Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
|
||||
Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
|
||||
Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
|
||||
|
||||
Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
|
||||
Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
|
||||
|
||||
If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
|
||||
Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 7, PDMM,)
|
||||
Or(PDCR, 0x01, PDCR)
|
||||
}
|
||||
Else {
|
||||
If(LNotEqual(DSD0, 0xFFFFFFFF)) {
|
||||
Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
|
||||
Store(DerefOf(Index(MDRT, Local0)), PMTM)
|
||||
}
|
||||
}
|
||||
|
||||
If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
|
||||
Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 7, PDSM,)
|
||||
Or(PDCR, 0x02, PDCR)
|
||||
}
|
||||
Else {
|
||||
If(LNotEqual(DSD1, 0xFFFFFFFF)) {
|
||||
Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
|
||||
Store(DerefOf(Index(MDRT, Local0)), PMTS)
|
||||
}
|
||||
}
|
||||
/* Return(INBF) */
|
||||
} /*End Method(_STM) */
|
||||
Device(MST)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_GTF) {
|
||||
Name(CMBF, Buffer(21) {
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
|
||||
})
|
||||
CreateByteField(CMBF, 1, POMD)
|
||||
CreateByteField(CMBF, 8, DMMD)
|
||||
CreateByteField(CMBF, 5, CMDA)
|
||||
CreateByteField(CMBF, 12, CMDB)
|
||||
CreateByteField(CMBF, 19, CMDC)
|
||||
|
||||
Store(0xA0, CMDA)
|
||||
Store(0xA0, CMDB)
|
||||
Store(0xA0, CMDC)
|
||||
|
||||
Or(PPMM, 0x08, POMD)
|
||||
|
||||
If(And(PDCR, 0x01)) {
|
||||
Or(PDMM, 0x40, DMMD)
|
||||
}
|
||||
Else {
|
||||
Store(Match
|
||||
(MDTT, MLE, GTTM(PMTM),
|
||||
MTR, 0, 0), Local0)
|
||||
If(LLess(Local0, 3)) {
|
||||
Or(0x20, Local0, DMMD)
|
||||
}
|
||||
}
|
||||
Return(CMBF)
|
||||
}
|
||||
} /* End Device(MST) */
|
||||
|
||||
Device(SLAV)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_GTF) {
|
||||
Name(CMBF, Buffer(21) {
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
|
||||
})
|
||||
CreateByteField(CMBF, 1, POMD)
|
||||
CreateByteField(CMBF, 8, DMMD)
|
||||
CreateByteField(CMBF, 5, CMDA)
|
||||
CreateByteField(CMBF, 12, CMDB)
|
||||
CreateByteField(CMBF, 19, CMDC)
|
||||
|
||||
Store(0xB0, CMDA)
|
||||
Store(0xB0, CMDB)
|
||||
Store(0xB0, CMDC)
|
||||
|
||||
Or(PPSM, 0x08, POMD)
|
||||
|
||||
If(And(PDCR, 0x02)) {
|
||||
Or(PDSM, 0x40, DMMD)
|
||||
}
|
||||
Else {
|
||||
Store(Match
|
||||
(MDTT, MLE, GTTM(PMTS),
|
||||
MTR, 0, 0), Local0)
|
||||
If(LLess(Local0, 3)) {
|
||||
Or(0x20, Local0, DMMD)
|
||||
}
|
||||
}
|
||||
Return(CMBF)
|
||||
}
|
||||
} /* End Device(SLAV) */
|
||||
}
|
||||
@@ -1,334 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
|
||||
)
|
||||
{
|
||||
#include "routing.asl"
|
||||
}
|
||||
*/
|
||||
|
||||
/* Routing is in System Bus scope */
|
||||
Scope(\_SB) {
|
||||
Name(PR0, Package(){
|
||||
/* NB devices */
|
||||
/* Bus 0, Dev 0 - RS780 Host Controller */
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
Package(){0x0001FFFF, 0, INTC, 0 },
|
||||
Package(){0x0001FFFF, 1, INTD, 0 },
|
||||
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
|
||||
Package(){0x0002FFFF, 0, INTC, 0 },
|
||||
Package(){0x0002FFFF, 1, INTD, 0 },
|
||||
Package(){0x0002FFFF, 2, INTA, 0 },
|
||||
Package(){0x0002FFFF, 3, INTB, 0 },
|
||||
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
|
||||
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||
Package(){0x0004FFFF, 0, INTA, 0 },
|
||||
Package(){0x0004FFFF, 1, INTB, 0 },
|
||||
Package(){0x0004FFFF, 2, INTC, 0 },
|
||||
Package(){0x0004FFFF, 3, INTD, 0 },
|
||||
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||
/* Package(){0x0005FFFF, 0, INTB, 0 }, */
|
||||
/* Package(){0x0005FFFF, 1, INTC, 0 }, */
|
||||
/* Package(){0x0005FFFF, 2, INTD, 0 }, */
|
||||
/* Package(){0x0005FFFF, 3, INTA, 0 }, */
|
||||
/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
|
||||
Package(){0x0006FFFF, 0, INTC, 0 },
|
||||
Package(){0x0006FFFF, 1, INTD, 0 },
|
||||
Package(){0x0006FFFF, 2, INTA, 0 },
|
||||
Package(){0x0006FFFF, 3, INTB, 0 },
|
||||
/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
|
||||
Package(){0x0007FFFF, 0, INTD, 0 },
|
||||
Package(){0x0007FFFF, 1, INTA, 0 },
|
||||
Package(){0x0007FFFF, 2, INTB, 0 },
|
||||
Package(){0x0007FFFF, 3, INTC, 0 },
|
||||
|
||||
Package(){0x0009FFFF, 0, INTB, 0 },
|
||||
Package(){0x0009FFFF, 1, INTC, 0 },
|
||||
Package(){0x0009FFFF, 2, INTD, 0 },
|
||||
Package(){0x0009FFFF, 3, INTA, 0 },
|
||||
|
||||
Package(){0x000AFFFF, 0, INTC, 0 },
|
||||
Package(){0x000AFFFF, 1, INTD, 0 },
|
||||
Package(){0x000AFFFF, 2, INTA, 0 },
|
||||
Package(){0x000AFFFF, 3, INTB, 0 },
|
||||
|
||||
Package(){0x000BFFFF, 0, INTD, 0 },
|
||||
Package(){0x000BFFFF, 1, INTA, 0 },
|
||||
Package(){0x000BFFFF, 2, INTB, 0 },
|
||||
Package(){0x000BFFFF, 3, INTC, 0 },
|
||||
|
||||
Package(){0x000CFFFF, 0, INTA, 0 },
|
||||
Package(){0x000CFFFF, 1, INTB, 0 },
|
||||
Package(){0x000CFFFF, 2, INTC, 0 },
|
||||
Package(){0x000CFFFF, 3, INTD, 0 },
|
||||
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
/* SB devices */
|
||||
/* Bus 0, Dev 17 - SATA controller #2 */
|
||||
/* Bus 0, Dev 18 - SATA controller #1 */
|
||||
Package(){0x0011FFFF, 0, INTG, 0 },
|
||||
|
||||
/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
|
||||
* EHCI, dev 18, 19 func 2 */
|
||||
Package(){0x0012FFFF, 0, INTA, 0 },
|
||||
Package(){0x0012FFFF, 1, INTB, 0 },
|
||||
Package(){0x0012FFFF, 2, INTC, 0 },
|
||||
Package(){0x0012FFFF, 3, INTD, 0 },
|
||||
|
||||
Package(){0x0013FFFF, 0, INTC, 0 },
|
||||
Package(){0x0013FFFF, 1, INTD, 0 },
|
||||
Package(){0x0013FFFF, 2, INTA, 0 },
|
||||
Package(){0x0013FFFF, 3, INTB, 0 },
|
||||
|
||||
/* Package(){0x0014FFFF, 1, INTA, 0 }, */
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
|
||||
Package(){0x0014FFFF, 0, INTA, 0 },
|
||||
Package(){0x0014FFFF, 1, INTB, 0 },
|
||||
Package(){0x0014FFFF, 2, INTC, 0 },
|
||||
Package(){0x0014FFFF, 3, INTD, 0 },
|
||||
|
||||
/* Package(){0x0015FFFF, 0, INTA, 0 },
|
||||
Package(){0x0015FFFF, 1, INTB, 0 },
|
||||
Package(){0x0015FFFF, 2, INTC, 0 },
|
||||
Package(){0x0015FFFF, 3, INTD, 0 },
|
||||
*/
|
||||
})
|
||||
|
||||
Name(APR0, Package(){
|
||||
/* NB devices in APIC mode */
|
||||
/* Bus 0, Dev 0 - RS780 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
/* Package(){0x0001FFFF, 0, 0, 18 }, */
|
||||
/* Package(){0x0001FFFF, 1, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
|
||||
Package(){0x0002FFFF, 0, 0, 18 },
|
||||
/* Package(){0x0002FFFF, 1, 0, 19 }, */
|
||||
/* Package(){0x0002FFFF, 2, 0, 16 }, */
|
||||
/* Package(){0x0002FFFF, 3, 0, 17 }, */
|
||||
|
||||
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
|
||||
Package(){0x0003FFFF, 0, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||
Package(){0x0004FFFF, 0, 0, 16 },
|
||||
/* Package(){0x0004FFFF, 1, 0, 17 }, */
|
||||
/* Package(){0x0004FFFF, 2, 0, 18 }, */
|
||||
/* Package(){0x0004FFFF, 3, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||
/* Package(){0x0005FFFF, 0, 0, 17 }, */
|
||||
/* Package(){0x0005FFFF, 1, 0, 18 }, */
|
||||
/* Package(){0x0005FFFF, 2, 0, 19 }, */
|
||||
/* Package(){0x0005FFFF, 3, 0, 16 }, */
|
||||
|
||||
/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
|
||||
/* Package(){0x0006FFFF, 0, 0, 18 }, */
|
||||
/* Package(){0x0006FFFF, 1, 0, 19 }, */
|
||||
/* Package(){0x0006FFFF, 2, 0, 16 }, */
|
||||
/* Package(){0x0006FFFF, 3, 0, 17 }, */
|
||||
|
||||
/* Bus 0, Dev 7 - PCIe Bridge for network card */
|
||||
/* Package(){0x0007FFFF, 0, 0, 19 }, */
|
||||
/* Package(){0x0007FFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x0007FFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x0007FFFF, 3, 0, 18 }, */
|
||||
|
||||
/* Bus 0, Dev 9 - PCIe Bridge for network card */
|
||||
Package(){0x0009FFFF, 0, 0, 17 },
|
||||
/* Package(){0x0009FFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x0009FFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x0009FFFF, 3, 0, 18 }, */
|
||||
|
||||
/* Bus 0, Dev A - PCIe Bridge for network card */
|
||||
Package(){0x000AFFFF, 0, 0, 18 },
|
||||
/* Package(){0x000AFFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x000AFFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x000AFFFF, 3, 0, 18 }, */
|
||||
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
/* SB devices in APIC mode */
|
||||
/* Bus 0, Dev 17 - SATA controller #2 */
|
||||
/* Bus 0, Dev 18 - SATA controller #1 */
|
||||
Package(){0x0011FFFF, 0, 0, 22 },
|
||||
|
||||
/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
|
||||
* EHCI, dev 18, 19 func 2 */
|
||||
Package(){0x0012FFFF, 0, 0, 16 },
|
||||
Package(){0x0012FFFF, 1, 0, 17 },
|
||||
Package(){0x0012FFFF, 2, 0, 18 },
|
||||
Package(){0x0012FFFF, 3, 0, 19 },
|
||||
|
||||
Package(){0x0013FFFF, 0, 0, 18 },
|
||||
Package(){0x0013FFFF, 1, 0, 19 },
|
||||
Package(){0x0013FFFF, 2, 0, 16 },
|
||||
Package(){0x0013FFFF, 3, 0, 17 },
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
Package(){0x0014FFFF, 1, 0, 17 },
|
||||
Package(){0x0014FFFF, 2, 0, 18 },
|
||||
Package(){0x0014FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PR1, Package(){
|
||||
/* Internal graphics - RS780 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, INTC, 0 },
|
||||
Package(){0x0005FFFF, 1, INTD, 0 },
|
||||
Package(){0x0005FFFF, 2, INTA, 0 },
|
||||
Package(){0x0005FFFF, 3, INTB, 0 },
|
||||
})
|
||||
|
||||
Name(APR1, Package(){
|
||||
/* Internal graphics - RS780 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, 0, 18 },
|
||||
Package(){0x0005FFFF, 1, 0, 19 },
|
||||
Package(){0x0005FFFF, 2, 0, 16 },
|
||||
Package(){0x0005FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
|
||||
Name(APS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
|
||||
Name(APS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, 0, 16 },
|
||||
Package(){0x0000FFFF, 1, 0, 17 },
|
||||
Package(){0x0000FFFF, 2, 0, 18 },
|
||||
Package(){0x0000FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PS5, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 5 */
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
|
||||
Name(APS5, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 5 */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
|
||||
Name(PS6, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 6 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
|
||||
Name(APS6, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 6 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS7, Package(){
|
||||
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
|
||||
Name(APS7, Package(){
|
||||
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
|
||||
Package(){0x0000FFFF, 0, 0, 19 },
|
||||
Package(){0x0000FFFF, 1, 0, 16 },
|
||||
Package(){0x0000FFFF, 2, 0, 17 },
|
||||
Package(){0x0000FFFF, 3, 0, 18 },
|
||||
})
|
||||
Name(PS9, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 9 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
|
||||
Name(APS9, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 9 */
|
||||
Package(){0x0000FFFF, 0, 0, 19 },
|
||||
Package(){0x0000FFFF, 1, 0, 16 },
|
||||
Package(){0x0000FFFF, 2, 0, 17 },
|
||||
Package(){0x0000FFFF, 3, 0, 18 },
|
||||
})
|
||||
Name(PSa, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
|
||||
Name(APSa, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 16 },
|
||||
Package(){0x0000FFFF, 2, 0, 17 },
|
||||
Package(){0x0000FFFF, 3, 0, 18 },
|
||||
})
|
||||
|
||||
Name(PCIB, Package(){
|
||||
/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
|
||||
Package(){0x0005FFFF, 0, 0, 0x14 },
|
||||
Package(){0x0005FFFF, 1, 0, 0x15 },
|
||||
Package(){0x0005FFFF, 2, 0, 0x16 },
|
||||
Package(){0x0005FFFF, 3, 0, 0x17 },
|
||||
Package(){0x0006FFFF, 0, 0, 0x15 },
|
||||
Package(){0x0006FFFF, 1, 0, 0x16 },
|
||||
Package(){0x0006FFFF, 2, 0, 0x17 },
|
||||
Package(){0x0006FFFF, 3, 0, 0x14 },
|
||||
Package(){0x0007FFFF, 0, 0, 0x16 },
|
||||
Package(){0x0007FFFF, 1, 0, 0x17 },
|
||||
Package(){0x0007FFFF, 2, 0, 0x14 },
|
||||
Package(){0x0007FFFF, 3, 0, 0x15 },
|
||||
})
|
||||
}
|
||||
@@ -1,145 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
|
||||
/*
|
||||
Scope (_SB) {
|
||||
Device(PCI0) {
|
||||
Device(SATA) {
|
||||
Name(_ADR, 0x00110000)
|
||||
#include "sata.asl"
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
Name(STTM, Buffer(20) {
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x1f, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
/* Start by clearing the PhyRdyChg bits */
|
||||
Method(_INI) {
|
||||
\_GPE._L1F()
|
||||
}
|
||||
|
||||
Device(PMRY)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(PMST) {
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P0IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
}/* end of PMST */
|
||||
|
||||
Device(PSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P1IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of PSLA */
|
||||
} /* end of PMRY */
|
||||
|
||||
|
||||
Device(SEDY)
|
||||
{
|
||||
Name(_ADR, 1) /* IDE Scondary Channel */
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(SMST)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P2IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SMST */
|
||||
|
||||
Device(SSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P3IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SSLA */
|
||||
} /* end of SEDY */
|
||||
|
||||
/* SATA Hot Plug Support */
|
||||
Scope(\_GPE) {
|
||||
Method(_L1F,0x0,NotSerialized) {
|
||||
if (\_SB.P0PR) {
|
||||
if (LGreater(\_SB.P0IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P0PR)
|
||||
}
|
||||
|
||||
if (\_SB.P1PR) {
|
||||
if (LGreater(\_SB.P1IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P1PR)
|
||||
}
|
||||
|
||||
if (\_SB.P2PR) {
|
||||
if (LGreater(\_SB.P2IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P2PR)
|
||||
}
|
||||
|
||||
if (\_SB.P3PR) {
|
||||
if (LGreater(\_SB.P3IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P3PR)
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1,158 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
/*
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
|
||||
)
|
||||
{
|
||||
#include "usb.asl"
|
||||
}
|
||||
*/
|
||||
Method(UCOC, 0) {
|
||||
Sleep(20)
|
||||
Store(0x13,CMTI)
|
||||
Store(0,GPSL)
|
||||
}
|
||||
|
||||
/* USB Port 0 overcurrent uses Gpm 0 */
|
||||
If(LLessEqual(UOM0,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L13) {
|
||||
UCOC()
|
||||
if(LEqual(GPB0,PLC0)) {
|
||||
Not(PLC0,PLC0)
|
||||
Store(PLC0, \_SB.PT0D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 1 overcurrent uses Gpm 1 */
|
||||
If (LLessEqual(UOM1,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L14) {
|
||||
UCOC()
|
||||
if (LEqual(GPB1,PLC1)) {
|
||||
Not(PLC1,PLC1)
|
||||
Store(PLC1, \_SB.PT1D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 2 overcurrent uses Gpm 2 */
|
||||
If (LLessEqual(UOM2,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L15) {
|
||||
UCOC()
|
||||
if (LEqual(GPB2,PLC2)) {
|
||||
Not(PLC2,PLC2)
|
||||
Store(PLC2, \_SB.PT2D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 3 overcurrent uses Gpm 3 */
|
||||
If (LLessEqual(UOM3,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L16) {
|
||||
UCOC()
|
||||
if (LEqual(GPB3,PLC3)) {
|
||||
Not(PLC3,PLC3)
|
||||
Store(PLC3, \_SB.PT3D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 4 overcurrent uses Gpm 4 */
|
||||
If (LLessEqual(UOM4,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L19) {
|
||||
UCOC()
|
||||
if (LEqual(GPB4,PLC4)) {
|
||||
Not(PLC4,PLC4)
|
||||
Store(PLC4, \_SB.PT4D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 5 overcurrent uses Gpm 5 */
|
||||
If (LLessEqual(UOM5,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L1A) {
|
||||
UCOC()
|
||||
if (LEqual(GPB5,PLC5)) {
|
||||
Not(PLC5,PLC5)
|
||||
Store(PLC5, \_SB.PT5D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 6 overcurrent uses Gpm 6 */
|
||||
If (LLessEqual(UOM6,9)) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1C) { */
|
||||
Method (_L06) {
|
||||
UCOC()
|
||||
if (LEqual(GPB6,PLC6)) {
|
||||
Not(PLC6,PLC6)
|
||||
Store(PLC6, \_SB.PT6D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 7 overcurrent uses Gpm 7 */
|
||||
If (LLessEqual(UOM7,9)) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1D) { */
|
||||
Method (_L07) {
|
||||
UCOC()
|
||||
if (LEqual(GPB7,PLC7)) {
|
||||
Not(PLC7,PLC7)
|
||||
Store(PLC7, \_SB.PT7D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 8 overcurrent uses Gpm 8 */
|
||||
If (LLessEqual(UOM8,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L17) {
|
||||
if (LEqual(G8IS,PLC8)) {
|
||||
Not(PLC8,PLC8)
|
||||
Store(PLC8, \_SB.PT8D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 9 overcurrent uses Gpm 9 */
|
||||
If (LLessEqual(UOM9,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L0E) {
|
||||
if (LEqual(G9IS,0)) {
|
||||
Store(1,\_SB.PT9D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1,44 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010-2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
/* create all subtables for processors */
|
||||
current = acpi_create_madt_lapics(current);
|
||||
|
||||
/* Write SB700 IOAPIC, only one */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
|
||||
CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
|
||||
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 0, 2, 0);
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 9, 9, 0xF);
|
||||
/* 0: mean bus 0--->ISA */
|
||||
/* 0: PIC 0 */
|
||||
/* 2: APIC 2 */
|
||||
/* 5 mean: 0101 --> Edge-triggered, Active high */
|
||||
|
||||
/* create all subtables for processors */
|
||||
/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
|
||||
/* 1: LINT1 connect to NMI */
|
||||
|
||||
return current;
|
||||
}
|
||||
@@ -1 +0,0 @@
|
||||
Category: eval
|
||||
@@ -1,52 +0,0 @@
|
||||
entries
|
||||
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
#392 3 r 0 unused
|
||||
395 1 e 1 hw_scrubber
|
||||
396 1 e 1 interleave_chip_selects
|
||||
397 2 e 8 max_mem_clock
|
||||
399 1 e 2 multi_core
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
440 4 e 9 slow_cpu
|
||||
444 1 e 1 nmi
|
||||
445 1 e 1 gart
|
||||
456 1 e 1 ECC_memory
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
6 5 Notice
|
||||
6 6 Info
|
||||
6 7 Debug
|
||||
6 8 Spew
|
||||
8 0 400Mhz
|
||||
8 1 333Mhz
|
||||
8 2 266Mhz
|
||||
8 3 200Mhz
|
||||
9 0 off
|
||||
9 1 87.5%
|
||||
9 2 75.0%
|
||||
9 3 62.5%
|
||||
9 4 50.0%
|
||||
9 5 37.5%
|
||||
9 6 25.0%
|
||||
9 7 12.5%
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
@@ -1,129 +0,0 @@
|
||||
# sample config for amd/mahogany_fam10
|
||||
chip northbridge/amd/amdfam10/root_complex
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_AM2r2 #L1 and DDR2
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device domain 0 on
|
||||
subsystemid 0x1022 0x3060 inherit
|
||||
chip northbridge/amd/amdfam10
|
||||
device pci 18.0 on # northbridge
|
||||
chip southbridge/amd/rs780
|
||||
device pci 0.0 on end # HT 0x9600
|
||||
device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
|
||||
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
|
||||
device pci 3.0 on end # PCIE P2P bridge 0x960b
|
||||
device pci 4.0 on end # PCIE P2P bridge 0x9604
|
||||
device pci 5.0 off end # PCIE P2P bridge 0x9605
|
||||
device pci 6.0 off end # PCIE P2P bridge 0x9606
|
||||
device pci 7.0 off end # PCIE P2P bridge 0x9607
|
||||
device pci 8.0 off end # NB/SB Link P2P bridge
|
||||
device pci 9.0 on end #
|
||||
device pci a.0 on end #
|
||||
register "gppsb_configuration" = "1" # Configuration B
|
||||
register "gpp_configuration" = "3" # Configuration D default
|
||||
register "port_enable" = "0x6fc"
|
||||
register "gfx_dev2_dev3" = "1"
|
||||
register "gfx_dual_slot" = "1"
|
||||
register "gfx_lane_reversal" = "0"
|
||||
register "gfx_tmds" = "0"
|
||||
register "gfx_compliance" = "0"
|
||||
register "gfx_reconfiguration" = "1"
|
||||
register "gfx_link_width" = "0"
|
||||
end
|
||||
chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus
|
||||
device pci 11.0 on end # SATA
|
||||
device pci 12.0 on end # USB
|
||||
device pci 12.1 on end # USB
|
||||
device pci 12.2 on end # USB
|
||||
device pci 13.0 on end # USB
|
||||
device pci 13.1 on end # USB
|
||||
device pci 13.2 on end # USB
|
||||
device pci 14.0 on # SM
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
end # SM
|
||||
device pci 14.1 on end # IDE 0x439c
|
||||
device pci 14.2 on end # HDA 0x4383
|
||||
device pci 14.3 on # LPC 0x439d
|
||||
chip superio/ite/it8718f
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.2 off # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.3 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.4 off end # EC
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.6 on # Mouse
|
||||
irq 0x70 = 12
|
||||
end
|
||||
device pnp 2e.7 off # GPIO, must be closed for unresolved reason.
|
||||
end
|
||||
device pnp 2e.8 off # MIDI
|
||||
io 0x60 = 0x300
|
||||
irq 0x70 = 9
|
||||
end
|
||||
device pnp 2e.9 off # GAME
|
||||
io 0x60 = 0x220
|
||||
end
|
||||
device pnp 2e.a off end # CIR
|
||||
end #superio/ite/it8718f
|
||||
end #LPC
|
||||
device pci 14.4 on end # PCI 0x4384
|
||||
device pci 14.5 on end # USB 2
|
||||
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
|
||||
end #southbridge/amd/sb700
|
||||
end # device pci 18.0
|
||||
|
||||
device pci 18.0 on end
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
device pci 18.4 on end
|
||||
# device pci 00.5 on end
|
||||
end
|
||||
end #domain
|
||||
#for node 32 to node 63
|
||||
# device domain 0 on
|
||||
# chip northbridge/amd/amdfam10
|
||||
# device pci 00.0 on end# northbridge
|
||||
# device pci 00.0 on end
|
||||
# device pci 00.0 on end
|
||||
# device pci 00.0 on end
|
||||
# device pci 00.1 on end
|
||||
# device pci 00.2 on end
|
||||
# device pci 00.3 on end
|
||||
# device pci 00.4 on end
|
||||
# device pci 00.5 on end
|
||||
# end
|
||||
# end #domain
|
||||
|
||||
end
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,44 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/pci.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <cpu/amd/multicore.h>
|
||||
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
/* Global variables for MB layouts and these will be shared by irqtable mptable
|
||||
* and acpi_tables busnum is default.
|
||||
*/
|
||||
u32 apicid_sb700;
|
||||
|
||||
void get_bus_conf(void)
|
||||
{
|
||||
u32 apicid_base;
|
||||
|
||||
get_default_pci1234(1);
|
||||
|
||||
sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
|
||||
|
||||
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
if (CONFIG(LOGICAL_CPUS))
|
||||
apicid_base = get_apicid_base(1);
|
||||
else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
apicid_sb700 = apicid_base + 0;
|
||||
}
|
||||
@@ -1,102 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
|
||||
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
|
||||
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
|
||||
u8 slot, u8 rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
u32 slot_num;
|
||||
u8 *v;
|
||||
|
||||
u8 sum = 0;
|
||||
int i;
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be between 0xf0000 & 0x100000 */
|
||||
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (u8 *) (addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
pirq->rtr_bus = pirq_router_bus;
|
||||
pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
pirq->rtr_vendor = 0x1002;
|
||||
pirq->rtr_device = 0x4384;
|
||||
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *)(&pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
|
||||
/* pci bridge */
|
||||
write_pirq_info(pirq_info, pirq_router_bus, PCI_DEVFN(0x14, 4),
|
||||
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
|
||||
0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "write_pirq_routing_table done.\n");
|
||||
|
||||
return (unsigned long)pirq_info;
|
||||
}
|
||||
@@ -1,103 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <southbridge/amd/sb700/sb700.h>
|
||||
#include <southbridge/amd/sb700/smbus.h>
|
||||
#include <southbridge/amd/rs780/rs780.h>
|
||||
|
||||
/*
|
||||
* Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
|
||||
* pull it up before training the slot.
|
||||
***/
|
||||
void set_pcie_dereset(void)
|
||||
{
|
||||
u16 word;
|
||||
struct device *sm_dev;
|
||||
/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
|
||||
sm_dev = pcidev_on_root(0x14, 0);
|
||||
|
||||
word = pci_read_config16(sm_dev, 0xA8);
|
||||
word |= (1 << 0) | (1 << 2); /* Set Gpio6,4 as output */
|
||||
word &= ~((1 << 8) | (1 << 10));
|
||||
pci_write_config16(sm_dev, 0xA8, word);
|
||||
}
|
||||
|
||||
void set_pcie_reset(void)
|
||||
{
|
||||
u16 word;
|
||||
struct device *sm_dev;
|
||||
/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
|
||||
sm_dev = pcidev_on_root(0x14, 0);
|
||||
|
||||
word = pci_read_config16(sm_dev, 0xA8);
|
||||
word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */
|
||||
word &= ~((1 << 8) | (1 << 10));
|
||||
pci_write_config16(sm_dev, 0xA8, word);
|
||||
}
|
||||
|
||||
#if 0 /* not tested yet. */
|
||||
/********************************************************
|
||||
* mahogany uses SB700 GPIO9 to detect IDE_DMA66.
|
||||
* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
|
||||
* get the cable type, 40 pin or 80 pin?
|
||||
********************************************************/
|
||||
static void get_ide_dma66(void)
|
||||
{
|
||||
u8 byte;
|
||||
/*u32 sm_dev, ide_dev; */
|
||||
struct device *sm_dev, ide_dev;
|
||||
|
||||
sm_dev = pcidev_on_root(0x14, 0);
|
||||
|
||||
byte = pci_read_config8(sm_dev, 0xA9);
|
||||
byte |= (1 << 5); /* Set Gpio9 as input */
|
||||
pci_write_config8(sm_dev, 0xA9, byte);
|
||||
|
||||
ide_dev = pcidev_on_root(0x14, 1);
|
||||
byte = pci_read_config8(ide_dev, 0x56);
|
||||
byte &= ~(7 << 0);
|
||||
if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
|
||||
byte |= 2 << 0; /* mode 2 */
|
||||
else
|
||||
byte |= 5 << 0; /* mode 5 */
|
||||
pci_write_config8(ide_dev, 0x56, byte);
|
||||
}
|
||||
#endif /* get_ide_dma66() */
|
||||
|
||||
int is_dev3_present(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*************************************************
|
||||
* enable the dedicated function in mahogany board.
|
||||
* This function called early than rs780_enable.
|
||||
*************************************************/
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev);
|
||||
|
||||
set_pcie_dereset();
|
||||
/* get_ide_dma66(); */
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
@@ -1,102 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <stdint.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
extern u32 apicid_sb700;
|
||||
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
{
|
||||
struct device *dev;
|
||||
u32 dword;
|
||||
u8 byte;
|
||||
|
||||
dev =
|
||||
dev_find_slot(pirq_router_bus,
|
||||
PCI_DEVFN(0x14, 0));
|
||||
if (dev) {
|
||||
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
|
||||
smp_write_ioapic(mc, apicid_sb700,
|
||||
0x11,(void *) dword);
|
||||
|
||||
/* Initialize interrupt mapping */
|
||||
/* aza */
|
||||
byte = pci_read_config8(dev, 0x63);
|
||||
byte &= 0xf8;
|
||||
byte |= 0; /* 0: INTA, ...., 7: INTH */
|
||||
pci_write_config8(dev, 0x63, byte);
|
||||
|
||||
/* SATA */
|
||||
dword = pci_read_config32(dev, 0xac);
|
||||
dword &= ~(7 << 26);
|
||||
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
|
||||
/* dword |= 1 << 22; PIC and APIC co exists */
|
||||
pci_write_config32(dev, 0xac, dword);
|
||||
|
||||
/*
|
||||
* 00:12.0: PROG SATA : INT F
|
||||
* 00:13.0: INTA USB_0
|
||||
* 00:13.1: INTB USB_1
|
||||
* 00:13.2: INTC USB_2
|
||||
* 00:13.3: INTD USB_3
|
||||
* 00:13.4: INTC USB_4
|
||||
* 00:13.5: INTD USB2
|
||||
* 00:14.1: INTA IDE
|
||||
* 00:14.2: Prog HDA : INT E
|
||||
* 00:14.5: INTB ACI
|
||||
* 00:14.6: INTB MCI
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
@@ -1,279 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#include <commonlib/helpers.h>
|
||||
#include <northbridge/amd/amdfam10/amdfam10.h>
|
||||
|
||||
void setup_mb_resource_map(void)
|
||||
{
|
||||
static const unsigned int register_values[] = {
|
||||
/* Careful set limit registers before base registers which contain the enables */
|
||||
/* DRAM Limit i Registers
|
||||
* F1:0x44 i = 0
|
||||
* F1:0x4C i = 1
|
||||
* F1:0x54 i = 2
|
||||
* F1:0x5C i = 3
|
||||
* F1:0x64 i = 4
|
||||
* F1:0x6C i = 5
|
||||
* F1:0x74 i = 6
|
||||
* F1:0x7C i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 3] Reserved
|
||||
* [10: 8] Interleave select
|
||||
* specifies the values of A[14:12] to use with interleave enable.
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Limit Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40 bit address
|
||||
* that define the end of the DRAM region.
|
||||
*/
|
||||
// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
|
||||
ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001,
|
||||
ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002,
|
||||
ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003,
|
||||
ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004,
|
||||
ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005,
|
||||
ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006,
|
||||
ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
|
||||
/* DRAM Base i Registers
|
||||
* F1:0x40 i = 0
|
||||
* F1:0x48 i = 1
|
||||
* F1:0x50 i = 2
|
||||
* F1:0x58 i = 3
|
||||
* F1:0x60 i = 4
|
||||
* F1:0x68 i = 5
|
||||
* F1:0x70 i = 6
|
||||
* F1:0x78 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 7: 2] Reserved
|
||||
* [10: 8] Interleave Enable
|
||||
* 000 = No interleave
|
||||
* 001 = Interleave on A[12] (2 nodes)
|
||||
* 010 = reserved
|
||||
* 011 = Interleave on A[12] and A[14] (4 nodes)
|
||||
* 100 = reserved
|
||||
* 101 = reserved
|
||||
* 110 = reserved
|
||||
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
|
||||
* [15:11] Reserved
|
||||
* [13:16] DRAM Base Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40-bit address
|
||||
* that define the start of the DRAM region.
|
||||
*/
|
||||
// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
|
||||
ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
* F1:0x8C i = 1
|
||||
* F1:0x94 i = 2
|
||||
* F1:0x9C i = 3
|
||||
* F1:0xA4 i = 4
|
||||
* F1:0xAC i = 5
|
||||
* F1:0xB4 i = 6
|
||||
* F1:0xBC i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Reserved
|
||||
* [ 6: 6] Reserved
|
||||
* [ 7: 7] Non-Posted
|
||||
* 0 = CPU writes may be posted
|
||||
* 1 = CPU writes must be non-posted
|
||||
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
|
||||
* This field defines the upp address bits of a 40-bit address that
|
||||
* defines the end of a memory-mapped I/O region n
|
||||
*/
|
||||
ADDRMAP_REG(0x84), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x8C), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x94), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x9C), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xA4), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xAC), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
|
||||
// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
|
||||
|
||||
/* Memory-Mapped I/O Base i Registers
|
||||
* F1:0x80 i = 0
|
||||
* F1:0x88 i = 1
|
||||
* F1:0x90 i = 2
|
||||
* F1:0x98 i = 3
|
||||
* F1:0xA0 i = 4
|
||||
* F1:0xA8 i = 5
|
||||
* F1:0xB0 i = 6
|
||||
* F1:0xB8 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Cpu Disable
|
||||
* 0 = Cpu can use this I/O range
|
||||
* 1 = Cpu requests do not use this I/O range
|
||||
* [ 3: 3] Lock
|
||||
* 0 = base/limit registers i are read/write
|
||||
* 1 = base/limit registers i are read-only
|
||||
* [ 7: 4] Reserved
|
||||
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
|
||||
* This field defines the upper address bits of a 40bit address
|
||||
* that defines the start of memory-mapped I/O region i
|
||||
*/
|
||||
ADDRMAP_REG(0x80), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x88), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x90), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x98), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
|
||||
// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
|
||||
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
* F1:0xCC i = 1
|
||||
* F1:0xD4 i = 2
|
||||
* F1:0xDC i = 3
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = reserved
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Limit Address i
|
||||
* This field defines the end of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000,
|
||||
ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000,
|
||||
ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000,
|
||||
ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
|
||||
|
||||
/* PCI I/O Base i Registers
|
||||
* F1:0xC0 i = 0
|
||||
* F1:0xC8 i = 1
|
||||
* F1:0xD0 i = 2
|
||||
* F1:0xD8 i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 3: 2] Reserved
|
||||
* [ 4: 4] VGA Enable
|
||||
* 0 = VGA matches Disabled
|
||||
* 1 = matches all address < 64K and where A[9:0] is in the
|
||||
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
|
||||
* [ 5: 5] ISA Enable
|
||||
* 0 = ISA matches Disabled
|
||||
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
|
||||
* from matching agains this base/limit pair
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Base i
|
||||
* This field defines the start of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003,
|
||||
ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000,
|
||||
ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000,
|
||||
ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
|
||||
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
* F1:0xE8 i = 2
|
||||
* F1:0xEC i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Device Number Compare Enable
|
||||
* 0 = The ranges are based on bus number
|
||||
* 1 = The ranges are ranges of devices on bus 0
|
||||
* [ 3: 3] Reserved
|
||||
* [ 6: 4] Destination Node
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 7] Reserved
|
||||
* [ 9: 8] Destination Link
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 - Reserved
|
||||
* [15:10] Reserved
|
||||
* [23:16] Bus Number Base i
|
||||
* This field defines the lowest bus number in configuration region i
|
||||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration regin i
|
||||
*/
|
||||
// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
|
||||
ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000,
|
||||
ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000,
|
||||
ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
|
||||
};
|
||||
|
||||
int max;
|
||||
max = ARRAY_SIZE(register_values);
|
||||
setup_resource_map(register_values, max);
|
||||
}
|
||||
@@ -1,223 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
//#define SYSTEM_TYPE 0 /* SERVER */
|
||||
#define SYSTEM_TYPE 1 /* DESKTOP */
|
||||
//#define SYSTEM_TYPE 2 /* MOBILE */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <console/console.h>
|
||||
#include <timestamp.h>
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include <superio/ite/common/ite.h>
|
||||
#include <superio/ite/it8718f/it8718f.h>
|
||||
#include <cpu/amd/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <cpu/amd/car.h>
|
||||
#include <southbridge/amd/common/reset.h>
|
||||
#include <southbridge/amd/sb700/sb700.h>
|
||||
#include <southbridge/amd/sb700/smbus.h>
|
||||
#include <northbridge/amd/amdfam10/raminit.h>
|
||||
#include <northbridge/amd/amdht/ht_wrapper.h>
|
||||
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
|
||||
#include <arch/early_variables.h>
|
||||
#include <cbmem.h>
|
||||
#include <southbridge/amd/rs780/rs780.h>
|
||||
#include <spd.h>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
|
||||
|
||||
#include "cpu/amd/quadcore/quadcore.c"
|
||||
|
||||
int spd_read_byte(unsigned int device, unsigned int address);
|
||||
|
||||
|
||||
int spd_read_byte(u32 device, u32 address)
|
||||
{
|
||||
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
|
||||
}
|
||||
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
struct sys_info *sysinfo = get_sysinfo();
|
||||
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
|
||||
u32 bsp_apicid = 0, val;
|
||||
msr_t msr;
|
||||
|
||||
timestamp_init(timestamp_get());
|
||||
timestamp_add_now(TS_START_ROMSTAGE);
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
/* mov bsp to bus 0xff when > 8 nodes */
|
||||
set_bsp_node_CHtExtNodeCfgEn();
|
||||
enumerate_ht_chain();
|
||||
sb7xx_51xx_pci_port80();
|
||||
}
|
||||
|
||||
post_code(0x30);
|
||||
|
||||
if (bist == 0) {
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
|
||||
/* All cores run this but the BSP(node0,core0) is the only core that returns. */
|
||||
}
|
||||
|
||||
post_code(0x32);
|
||||
|
||||
enable_rs780_dev8();
|
||||
sb7xx_51xx_lpc_init();
|
||||
|
||||
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
// Load MPB
|
||||
val = cpuid_eax(1);
|
||||
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
|
||||
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
|
||||
printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
|
||||
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
|
||||
|
||||
/* Setup sysinfo defaults */
|
||||
set_sysinfo_in_ram(0);
|
||||
|
||||
update_microcode(val);
|
||||
|
||||
post_code(0x33);
|
||||
|
||||
cpuSetAMDMSR(0);
|
||||
post_code(0x34);
|
||||
|
||||
amd_ht_init(sysinfo);
|
||||
post_code(0x35);
|
||||
|
||||
/* Setup nodes PCI space and start core 0 AP init. */
|
||||
finalize_node_setup(sysinfo);
|
||||
|
||||
/* Setup any mainboard PCI settings etc. */
|
||||
setup_mb_resource_map();
|
||||
post_code(0x36);
|
||||
|
||||
/* wait for all the APs core0 started by finalize_node_setup. */
|
||||
/* FIXME: A bunch of cores are going to start output to serial at once.
|
||||
It would be nice to fixup prink spinlocks for ROM XIP mode.
|
||||
I think it could be done by putting the spinlock flag in the cache
|
||||
of the BSP located right after sysinfo.
|
||||
*/
|
||||
wait_all_core0_started();
|
||||
|
||||
#if CONFIG(LOGICAL_CPUS)
|
||||
/* Core0 on each node is configured. Now setup any additional cores. */
|
||||
printk(BIOS_DEBUG, "start_other_cores()\n");
|
||||
start_other_cores(bsp_apicid);
|
||||
post_code(0x37);
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
#endif
|
||||
|
||||
post_code(0x38);
|
||||
|
||||
/* run _early_setup before soft-reset. */
|
||||
rs780_early_setup();
|
||||
sb7xx_51xx_early_setup();
|
||||
|
||||
#if CONFIG(SET_FIDVID)
|
||||
msr = rdmsr(MSR_COFVID_STS);
|
||||
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
|
||||
|
||||
/* FIXME: The sb fid change may survive the warm reset and only
|
||||
need to be done once.*/
|
||||
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
|
||||
|
||||
post_code(0x39);
|
||||
|
||||
if (!warm_reset_detect(0)) { // BSP is node 0
|
||||
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
|
||||
} else {
|
||||
init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
|
||||
}
|
||||
|
||||
post_code(0x3A);
|
||||
|
||||
/* show final fid and vid */
|
||||
msr = rdmsr(MSR_COFVID_STS);
|
||||
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
|
||||
#endif
|
||||
|
||||
rs780_htinit();
|
||||
|
||||
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
|
||||
if (!warm_reset_detect(0)) {
|
||||
printk(BIOS_INFO, "...WARM RESET...\n\n\n");
|
||||
soft_reset();
|
||||
die("After soft_reset - shouldn't see this message!!!\n");
|
||||
}
|
||||
|
||||
post_code(0x3B);
|
||||
|
||||
/* It's the time to set ctrl in sysinfo now; */
|
||||
printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
|
||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
||||
|
||||
post_code(0x40);
|
||||
|
||||
raminit_amdmct(sysinfo);
|
||||
|
||||
cbmem_initialize_empty();
|
||||
post_code(0x41);
|
||||
|
||||
amdmct_cbmem_store_info(sysinfo);
|
||||
|
||||
sb7xx_51xx_before_pci_init();
|
||||
|
||||
post_code(0x42);
|
||||
}
|
||||
|
||||
/**
|
||||
* BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
|
||||
* Description:
|
||||
* This routine is called every time a non-coherent chain is processed.
|
||||
* BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
|
||||
* swap list. The first part of the list controls the BUID assignment and the
|
||||
* second part of the list provides the device to device linking. Device orientation
|
||||
* can be detected automatically, or explicitly. See documentation for more details.
|
||||
*
|
||||
* Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
|
||||
* based on each device's unit count.
|
||||
*
|
||||
* Parameters:
|
||||
* @param[in] node = The node on which this chain is located
|
||||
* @param[in] link = The link on the host for this chain
|
||||
* @param[out] List = supply a pointer to a list
|
||||
*/
|
||||
BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
|
||||
{
|
||||
static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF};
|
||||
/* If the BUID was adjusted in early_ht we need to do the manual override */
|
||||
if ((node == 0) && (link == 0)) { /* BSP SB link */
|
||||
*List = swaplist;
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -1,56 +0,0 @@
|
||||
if BOARD_AMD_SERENGETI_CHEETAH_FAM10
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS
|
||||
def_bool y
|
||||
select CPU_AMD_SOCKET_F_1207
|
||||
select DIMM_DDR2
|
||||
select DIMM_REGISTERED
|
||||
select NORTHBRIDGE_AMD_AMDFAM10
|
||||
select SOUTHBRIDGE_AMD_AMD8111
|
||||
select SOUTHBRIDGE_AMD_AMD8132
|
||||
select HT_CHAIN_DISTRIBUTE
|
||||
select SUPERIO_WINBOND_W83627HF
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_1024
|
||||
select ENABLE_APIC_EXT_ID
|
||||
select LIFT_BSP_APIC_ID
|
||||
select DRIVERS_I2C_I2CMUX2
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default amd/serengeti_cheetah_fam10
|
||||
|
||||
config APIC_ID_OFFSET
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "Serengeti Cheetah (Fam10)"
|
||||
|
||||
# 6 * MAX_PHYSICAL_CPUS
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 48
|
||||
|
||||
config MAX_PHYSICAL_CPUS
|
||||
int
|
||||
default 8
|
||||
|
||||
config HT_CHAIN_END_UNITID_BASE
|
||||
hex
|
||||
default 0x6
|
||||
|
||||
config HT_CHAIN_UNITID_BASE
|
||||
hex
|
||||
default 0xa
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 11
|
||||
|
||||
endif # BOARD_AMD_SERENGETI_CHEETAH_FAM10
|
||||
@@ -1,2 +0,0 @@
|
||||
config BOARD_AMD_SERENGETI_CHEETAH_FAM10
|
||||
bool "Serengeti Cheetah (Fam10)"
|
||||
@@ -1,8 +0,0 @@
|
||||
$(eval $(call asl_template,ssdt2))
|
||||
$(eval $(call asl_template,ssdt3))
|
||||
$(eval $(call asl_template,ssdt4))
|
||||
$(eval $(call asl_template,ssdt5))
|
||||
|
||||
romstage-y += resourcemap.c
|
||||
|
||||
ramstage-y += get_bus_conf.c
|
||||
@@ -1,175 +0,0 @@
|
||||
//
|
||||
// This file is part of the coreboot project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
|
||||
//AMD8111
|
||||
Name (APIC, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present
|
||||
Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11},
|
||||
Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12},
|
||||
Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13}
|
||||
})
|
||||
|
||||
Name (PICM, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00},
|
||||
Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00},
|
||||
Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00},
|
||||
Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00}
|
||||
})
|
||||
|
||||
Name (DNCG, Ones)
|
||||
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LEqual (^DNCG, Ones)) {
|
||||
Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0)
|
||||
// Update the Device Number according to SBDN
|
||||
Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0))
|
||||
Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0))
|
||||
Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0))
|
||||
Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0))
|
||||
Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0))
|
||||
Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0))
|
||||
Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0))
|
||||
Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0))
|
||||
Store (0x00, ^DNCG)
|
||||
}
|
||||
If (LNot (PICF)) {Return (PICM)}
|
||||
Else {Return (APIC)}
|
||||
}
|
||||
|
||||
Device (SBC3)
|
||||
{
|
||||
// ACPI smbus it should be 0x00040003 if 8131 present
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
|
||||
}
|
||||
OperationRegion (PIRQ, PCI_Config, 0x56, 0x02)
|
||||
Field (PIRQ, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
PIBA, 8,
|
||||
PIDC, 8
|
||||
}
|
||||
//
|
||||
// OperationRegion (TS3_, PCI_Config, 0xC4, 0x02)
|
||||
// Field (TS3_, DWordAcc, NoLock, Preserve)
|
||||
// {
|
||||
// PTS3, 16
|
||||
// }
|
||||
//
|
||||
}
|
||||
|
||||
Device (HPET)
|
||||
{
|
||||
Name (HPT, 0x00)
|
||||
Name (_HID, EisaId ("PNP0103"))
|
||||
Name (_UID, 0x00)
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0F)
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate ()
|
||||
{
|
||||
Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400)
|
||||
})
|
||||
Return (BUF0)
|
||||
}
|
||||
}
|
||||
|
||||
#include "amd8111_pic.asl"
|
||||
|
||||
#include "amd8111_isa.asl"
|
||||
|
||||
Device (TP2P)
|
||||
{
|
||||
// 8111 P2P and it should 0x00030000 when 8131 present
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(\_SB.PCI0.SBDN, 0x00000000))
|
||||
}
|
||||
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x08, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x08, 0x01 }) }
|
||||
}
|
||||
|
||||
Device (USB0)
|
||||
{
|
||||
Name (_ADR, 0x00000000)
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x0F, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x0F, 0x01 }) }
|
||||
}
|
||||
}
|
||||
|
||||
Device (USB1)
|
||||
{
|
||||
Name (_ADR, 0x00000001)
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x0F, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x0F, 0x01 }) }
|
||||
}
|
||||
}
|
||||
|
||||
Name (APIC, Package (0x0C)
|
||||
{
|
||||
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB
|
||||
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },
|
||||
|
||||
Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 4
|
||||
Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
|
||||
Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
|
||||
Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
|
||||
|
||||
Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 3
|
||||
Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 },
|
||||
Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 },
|
||||
Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 }
|
||||
})
|
||||
|
||||
Name (PICM, Package (0x0C)
|
||||
{
|
||||
Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB
|
||||
Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
|
||||
|
||||
Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 4
|
||||
Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
|
||||
|
||||
Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 3
|
||||
Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
|
||||
Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
|
||||
})
|
||||
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LNot (PICF)) { Return (PICM) }
|
||||
Else { Return (APIC) }
|
||||
}
|
||||
}
|
||||
@@ -1,190 +0,0 @@
|
||||
//
|
||||
// This file is part of the coreboot project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
|
||||
#include <arch/ioapic.h>
|
||||
#include <cpu/x86/lapic_def.h>
|
||||
|
||||
//AMD8111 isa
|
||||
|
||||
Device (ISA)
|
||||
{
|
||||
// lpc 0x00040000
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(\_SB.PCI0.SBDN, 0x00010000))
|
||||
}
|
||||
|
||||
OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers
|
||||
Field (PIRY, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Z000, 2, // Parallel Port Range
|
||||
, 1,
|
||||
ECP, 1, // ECP Enable
|
||||
FDC1, 1, // Floppy Drive Controller 1
|
||||
FDC2, 1, // Floppy Drive Controller 2
|
||||
Offset (0x01),
|
||||
Z001, 3, // Serial Port A Range
|
||||
SAEN, 1, // Serial Post A Enabled
|
||||
Z002, 3, // Serial Port B Range
|
||||
SBEN, 1 // Serial Post B Enabled
|
||||
}
|
||||
|
||||
Device (PIC)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0000"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0020, 0x0020, 0x01, 0x02)
|
||||
IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02)
|
||||
IRQ (Edge, ActiveHigh, Exclusive) {2}
|
||||
})
|
||||
}
|
||||
|
||||
Device (DMA1)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0200"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0000, 0x0000, 0x01, 0x10)
|
||||
IO (Decode16, 0x0080, 0x0080, 0x01, 0x10)
|
||||
IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20)
|
||||
DMA (Compatibility, NotBusMaster, Transfer16) {4}
|
||||
})
|
||||
}
|
||||
|
||||
Device (TMR)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0100"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0040, 0x0040, 0x01, 0x04)
|
||||
IRQ (Edge, ActiveHigh, Exclusive) {0}
|
||||
})
|
||||
}
|
||||
|
||||
Device (RTC)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0B00"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0070, 0x0070, 0x01, 0x06)
|
||||
IRQ (Edge, ActiveHigh, Exclusive) {8}
|
||||
})
|
||||
}
|
||||
|
||||
Device (SPKR)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0800"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0061, 0x0061, 0x01, 0x01)
|
||||
})
|
||||
}
|
||||
|
||||
Device (COPR)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C04"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10)
|
||||
IRQ (Edge, ActiveHigh, Exclusive) {13}
|
||||
})
|
||||
}
|
||||
|
||||
Device (SYSR)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C02"))
|
||||
Name (_UID, 0x00)
|
||||
Name (SYR1, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) //report Thor NVRAM
|
||||
IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //report Thor NVRAM
|
||||
IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80)
|
||||
IO (Decode16, 0x0010, 0x0010, 0x01, 0x10)
|
||||
IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E)
|
||||
IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C)
|
||||
IO (Decode16, 0x0062, 0x0062, 0x01, 0x02)
|
||||
IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B)
|
||||
IO (Decode16, 0x0076, 0x0076, 0x01, 0x0A)
|
||||
IO (Decode16, 0x0090, 0x0090, 0x01, 0x10)
|
||||
IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E)
|
||||
IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10)
|
||||
IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
|
||||
IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
|
||||
})
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Return (SYR1)
|
||||
}
|
||||
}
|
||||
|
||||
Device (MEM)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C02"))
|
||||
Name (_UID, 0x01)
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate ()
|
||||
{
|
||||
Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF
|
||||
Memory32Fixed (ReadWrite, 0x000C0000, 0x00010000) // video BIOS c0000-c8404
|
||||
Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000)
|
||||
Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM
|
||||
Memory32Fixed (ReadWrite, LOCAL_APIC_ADDR, 0x00001000)
|
||||
Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS
|
||||
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
|
||||
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
|
||||
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
|
||||
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
|
||||
})
|
||||
// Read the Video Memory length
|
||||
CreateDWordField (BUF0, 0x14, CLEN)
|
||||
CreateDWordField (BUF0, 0x10, CBAS)
|
||||
|
||||
ShiftLeft (VGA1, 0x09, Local0)
|
||||
Store (Local0, CLEN)
|
||||
|
||||
Return (BUF0)
|
||||
}
|
||||
}
|
||||
|
||||
Device (PS2M)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0F13"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IRQNoFlags () {12}
|
||||
})
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
And (FLG0, 0x04, Local0)
|
||||
If (LEqual (Local0, 0x04)) { Return (0x0F) }
|
||||
Else { Return (0x00) }
|
||||
}
|
||||
}
|
||||
|
||||
Device (PS2K)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0303"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
|
||||
IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
|
||||
IRQNoFlags () {1}
|
||||
})
|
||||
}
|
||||
#include "superio.asl"
|
||||
|
||||
}
|
||||
@@ -1,366 +0,0 @@
|
||||
//
|
||||
// This file is part of the coreboot project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
|
||||
//AMD8111 pic LNKA B C D
|
||||
|
||||
Device (LNKA)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0F"))
|
||||
Name (_UID, 0x01)
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local0)
|
||||
If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled
|
||||
Else { Return (0x0B) } //Enabled
|
||||
}
|
||||
|
||||
Method (_PRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUFA, ResourceTemplate ()
|
||||
{
|
||||
IRQ (Level, ActiveLow, Shared) {3,5,10,11}
|
||||
})
|
||||
Return (BUFA)
|
||||
}
|
||||
|
||||
Method (_DIS, 0, NotSerialized)
|
||||
{
|
||||
Store (0x01, Local3)
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
|
||||
If (LGreater (Local1, 0x07))
|
||||
{
|
||||
Subtract (Local1, 0x08, Local1)
|
||||
}
|
||||
|
||||
ShiftLeft (Local3, Local1, Local3)
|
||||
Not (Local3, Local3)
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUFA, ResourceTemplate ()
|
||||
{
|
||||
IRQ (Level, ActiveLow, Shared) {}
|
||||
})
|
||||
CreateByteField (BUFA, 0x01, IRA1)
|
||||
CreateByteField (BUFA, 0x02, IRA2)
|
||||
Store (0x00, Local3)
|
||||
Store (0x00, Local4)
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
|
||||
If (LNot (LEqual (Local1, 0x00)))
|
||||
{ // Routing enable
|
||||
If (LGreater (Local1, 0x07))
|
||||
{
|
||||
Subtract (Local1, 0x08, Local2)
|
||||
ShiftLeft (One, Local2, Local4)
|
||||
}
|
||||
Else
|
||||
{
|
||||
If (LGreater (Local1, 0x00))
|
||||
{
|
||||
ShiftLeft (One, Local1, Local3)
|
||||
}
|
||||
}
|
||||
|
||||
Store (Local3, IRA1)
|
||||
Store (Local4, IRA2)
|
||||
}
|
||||
|
||||
Return (BUFA)
|
||||
}
|
||||
|
||||
Method (_SRS, 1, NotSerialized)
|
||||
{
|
||||
CreateByteField (Arg0, 0x01, IRA1)
|
||||
CreateByteField (Arg0, 0x02, IRA2)
|
||||
ShiftLeft (IRA2, 0x08, Local0)
|
||||
Or (Local0, IRA1, Local0)
|
||||
Store (0x00, Local1)
|
||||
ShiftRight (Local0, 0x01, Local0)
|
||||
While (LGreater (Local0, 0x00))
|
||||
{
|
||||
Increment (Local1)
|
||||
ShiftRight (Local0, 0x01, Local0)
|
||||
}
|
||||
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
|
||||
Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
|
||||
}
|
||||
}
|
||||
|
||||
Device (LNKB)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0F"))
|
||||
Name (_UID, 0x02)
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local0)
|
||||
If (LEqual (Local0, 0x00)) { Return (0x09) }
|
||||
Else { Return (0x0B) }
|
||||
}
|
||||
|
||||
Method (_PRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUFB, ResourceTemplate ()
|
||||
{
|
||||
IRQ (Level, ActiveLow, Shared) {3,5,10,11}
|
||||
})
|
||||
Return (BUFB)
|
||||
}
|
||||
|
||||
Method (_DIS, 0, NotSerialized)
|
||||
{
|
||||
Store (0x01, Local3)
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
|
||||
ShiftRight (Local1, 0x04, Local1)
|
||||
If (LGreater (Local1, 0x07))
|
||||
{
|
||||
Subtract (Local1, 0x08, Local1)
|
||||
}
|
||||
|
||||
ShiftLeft (Local3, Local1, Local3)
|
||||
Not (Local3, Local3)
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUFB, ResourceTemplate ()
|
||||
{
|
||||
IRQ (Level, ActiveLow, Shared) {}
|
||||
})
|
||||
CreateByteField (BUFB, 0x01, IRB1)
|
||||
CreateByteField (BUFB, 0x02, IRB2)
|
||||
Store (0x00, Local3)
|
||||
Store (0x00, Local4)
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
|
||||
ShiftRight (Local1, 0x04, Local1)
|
||||
If (LNot (LEqual (Local1, 0x00)))
|
||||
{
|
||||
If (LGreater (Local1, 0x07))
|
||||
{
|
||||
Subtract (Local1, 0x08, Local2)
|
||||
ShiftLeft (One, Local2, Local4)
|
||||
}
|
||||
Else
|
||||
{
|
||||
If (LGreater (Local1, 0x00))
|
||||
{
|
||||
ShiftLeft (One, Local1, Local3)
|
||||
}
|
||||
}
|
||||
|
||||
Store (Local3, IRB1)
|
||||
Store (Local4, IRB2)
|
||||
}
|
||||
|
||||
Return (BUFB)
|
||||
}
|
||||
|
||||
Method (_SRS, 1, NotSerialized)
|
||||
{
|
||||
CreateByteField (Arg0, 0x01, IRB1)
|
||||
CreateByteField (Arg0, 0x02, IRB2)
|
||||
ShiftLeft (IRB2, 0x08, Local0)
|
||||
Or (Local0, IRB1, Local0)
|
||||
Store (0x00, Local1)
|
||||
ShiftRight (Local0, 0x01, Local0)
|
||||
While (LGreater (Local0, 0x00))
|
||||
{
|
||||
Increment (Local1)
|
||||
ShiftRight (Local0, 0x01, Local0)
|
||||
}
|
||||
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
|
||||
ShiftLeft (Local1, 0x04, Local1)
|
||||
Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
|
||||
}
|
||||
}
|
||||
|
||||
Device (LNKC)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0F"))
|
||||
Name (_UID, 0x03)
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local0)
|
||||
If (LEqual (Local0, 0x00)) { Return (0x09) }
|
||||
Else { Return (0x0B) }
|
||||
}
|
||||
|
||||
Method (_PRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUFA, ResourceTemplate ()
|
||||
{
|
||||
IRQ (Level, ActiveLow, Shared) {3,5,10,11}
|
||||
})
|
||||
Return (BUFA)
|
||||
}
|
||||
|
||||
Method (_DIS, 0, NotSerialized)
|
||||
{
|
||||
Store (0x01, Local3)
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
|
||||
If (LGreater (Local1, 0x07))
|
||||
{
|
||||
Subtract (Local1, 0x08, Local1)
|
||||
}
|
||||
|
||||
ShiftLeft (Local3, Local1, Local3)
|
||||
Not (Local3, Local3)
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUFA, ResourceTemplate ()
|
||||
{
|
||||
IRQ (Level, ActiveLow, Shared) {}
|
||||
})
|
||||
CreateByteField (BUFA, 0x01, IRA1)
|
||||
CreateByteField (BUFA, 0x02, IRA2)
|
||||
Store (0x00, Local3)
|
||||
Store (0x00, Local4)
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
|
||||
If (LNot (LEqual (Local1, 0x00)))
|
||||
{
|
||||
If (LGreater (Local1, 0x07))
|
||||
{
|
||||
Subtract (Local1, 0x08, Local2)
|
||||
ShiftLeft (One, Local2, Local4)
|
||||
}
|
||||
Else
|
||||
{
|
||||
If (LGreater (Local1, 0x00))
|
||||
{
|
||||
ShiftLeft (One, Local1, Local3)
|
||||
}
|
||||
}
|
||||
|
||||
Store (Local3, IRA1)
|
||||
Store (Local4, IRA2)
|
||||
}
|
||||
|
||||
Return (BUFA)
|
||||
}
|
||||
|
||||
Method (_SRS, 1, NotSerialized)
|
||||
{
|
||||
CreateByteField (Arg0, 0x01, IRA1)
|
||||
CreateByteField (Arg0, 0x02, IRA2)
|
||||
ShiftLeft (IRA2, 0x08, Local0)
|
||||
Or (Local0, IRA1, Local0)
|
||||
Store (0x00, Local1)
|
||||
ShiftRight (Local0, 0x01, Local0)
|
||||
While (LGreater (Local0, 0x00))
|
||||
{
|
||||
Increment (Local1)
|
||||
ShiftRight (Local0, 0x01, Local0)
|
||||
}
|
||||
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
|
||||
Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
|
||||
}
|
||||
}
|
||||
|
||||
Device (LNKD)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0F"))
|
||||
Name (_UID, 0x04)
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local0)
|
||||
If (LEqual (Local0, 0x00)) { Return (0x09) }
|
||||
Else { Return (0x0B) }
|
||||
}
|
||||
|
||||
Method (_PRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUFB, ResourceTemplate ()
|
||||
{
|
||||
IRQ (Level, ActiveLow, Shared) {3,5,10,11}
|
||||
})
|
||||
Return (BUFB)
|
||||
}
|
||||
|
||||
Method (_DIS, 0, NotSerialized)
|
||||
{
|
||||
Store (0x01, Local3)
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
|
||||
ShiftRight (Local1, 0x04, Local1)
|
||||
If (LGreater (Local1, 0x07))
|
||||
{
|
||||
Subtract (Local1, 0x08, Local1)
|
||||
}
|
||||
|
||||
ShiftLeft (Local3, Local1, Local3)
|
||||
Not (Local3, Local3)
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUFB, ResourceTemplate ()
|
||||
{
|
||||
IRQ (Level, ActiveLow, Shared) {}
|
||||
})
|
||||
CreateByteField (BUFB, 0x01, IRB1)
|
||||
CreateByteField (BUFB, 0x02, IRB2)
|
||||
Store (0x00, Local3)
|
||||
Store (0x00, Local4)
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
|
||||
ShiftRight (Local1, 0x04, Local1)
|
||||
If (LNot (LEqual (Local1, 0x00)))
|
||||
{
|
||||
If (LGreater (Local1, 0x07))
|
||||
{
|
||||
Subtract (Local1, 0x08, Local2)
|
||||
ShiftLeft (One, Local2, Local4)
|
||||
}
|
||||
Else
|
||||
{
|
||||
If (LGreater (Local1, 0x00))
|
||||
{
|
||||
ShiftLeft (One, Local1, Local3)
|
||||
}
|
||||
}
|
||||
|
||||
Store (Local3, IRB1)
|
||||
Store (Local4, IRB2)
|
||||
}
|
||||
|
||||
Return (BUFB)
|
||||
}
|
||||
|
||||
Method (_SRS, 1, NotSerialized)
|
||||
{
|
||||
CreateByteField (Arg0, 0x01, IRB1)
|
||||
CreateByteField (Arg0, 0x02, IRB2)
|
||||
ShiftLeft (IRB2, 0x08, Local0)
|
||||
Or (Local0, IRB1, Local0)
|
||||
Store (0x00, Local1)
|
||||
ShiftRight (Local0, 0x01, Local0)
|
||||
While (LGreater (Local0, 0x00))
|
||||
{
|
||||
Increment (Local1)
|
||||
ShiftRight (Local0, 0x01, Local0)
|
||||
}
|
||||
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
|
||||
ShiftLeft (Local1, 0x04, Local1)
|
||||
Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
|
||||
}
|
||||
}
|
||||
@@ -1,122 +0,0 @@
|
||||
//
|
||||
// This file is part of the coreboot project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
Device (PG0A)
|
||||
{
|
||||
// 8132 pcix bridge
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(GHCD(HCIN, 0), 0x00000000))
|
||||
}
|
||||
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x29, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x29, 0x01 }) }
|
||||
}
|
||||
|
||||
Name (APIC, Package (0x04)
|
||||
{
|
||||
// Slot A - PIRQ BCDA
|
||||
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0018 }, //Slot 2
|
||||
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x0019 },
|
||||
Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x001A },
|
||||
Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x001B },
|
||||
})
|
||||
Name (PICM, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2
|
||||
Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
|
||||
})
|
||||
|
||||
Name (DNCG, Ones)
|
||||
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LEqual (^DNCG, Ones))
|
||||
{
|
||||
Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8
|
||||
Store (0x00, Local1)
|
||||
While (LLess (Local1, 0x04))
|
||||
{
|
||||
// Update the GSI according to HCIN
|
||||
Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
|
||||
Add(Local2, Local0, Local0)
|
||||
Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
|
||||
Increment (Local1)
|
||||
}
|
||||
Store (0x00, ^DNCG)
|
||||
}
|
||||
If (LNot (PICF)) { Return (PICM) }
|
||||
Else { Return (APIC) }
|
||||
}
|
||||
}
|
||||
|
||||
Device (PG0B)
|
||||
{
|
||||
// 8132 pcix bridge 2
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(GHCD(HCIN, 0), 0x00010000))
|
||||
}
|
||||
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x22, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x22, 0x01 }) }
|
||||
}
|
||||
|
||||
Name (APIC, Package (0x04)
|
||||
{
|
||||
// Slot A - PIRQ ABCD
|
||||
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x001F },// Slot 1
|
||||
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x0020 },
|
||||
Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x0021 },
|
||||
Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x0022 }
|
||||
})
|
||||
Name (PICM, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
|
||||
Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
|
||||
})
|
||||
|
||||
Name (DNCG, Ones)
|
||||
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LEqual (^DNCG, Ones))
|
||||
{
|
||||
Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8
|
||||
Store (0x00, Local1)
|
||||
While (LLess (Local1, 0x04))
|
||||
{
|
||||
// Update the GSI according to HCIN
|
||||
Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
|
||||
Add(Local2, Local0, Local0)
|
||||
Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
|
||||
Increment (Local1)
|
||||
}
|
||||
|
||||
Store (0x00, ^DNCG)
|
||||
|
||||
}
|
||||
|
||||
If (LNot (PICF)) { Return (PICM) }
|
||||
Else { Return (APIC) }
|
||||
}
|
||||
}
|
||||
@@ -1,130 +0,0 @@
|
||||
//
|
||||
// This file is part of the coreboot project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
|
||||
Device (PG0A)
|
||||
{
|
||||
// 8132 pcix bridge
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(GHCD(HCIN, 0), 0x00000000))
|
||||
}
|
||||
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x29, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x29, 0x01 }) }
|
||||
}
|
||||
|
||||
Name (APIC, Package (0x14)
|
||||
{
|
||||
// Slot A - PIRQ BCDA
|
||||
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 2
|
||||
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A },
|
||||
Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B },
|
||||
Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 },
|
||||
|
||||
//Cypress Slot A - PIRQ BCDA
|
||||
Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x19 }, //?
|
||||
Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1A },
|
||||
Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1B },
|
||||
Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x18 },
|
||||
|
||||
//Cypress Slot B - PIRQ CDAB
|
||||
Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, //?
|
||||
Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B },
|
||||
Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x18 },
|
||||
Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x19 },
|
||||
|
||||
//Cypress Slot C - PIRQ DABC
|
||||
Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x1B }, //?
|
||||
Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x18 },
|
||||
Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x19 },
|
||||
Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x1A },
|
||||
|
||||
//Cypress Slot D - PIRQ ABCD
|
||||
Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x18 }, //?
|
||||
Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x19 },
|
||||
Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1A },
|
||||
Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1B }
|
||||
})
|
||||
Name (PICM, Package (0x14)
|
||||
{
|
||||
Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 2
|
||||
Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
|
||||
Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
|
||||
|
||||
Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
|
||||
Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
|
||||
|
||||
Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
|
||||
Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
|
||||
Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
|
||||
|
||||
Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
|
||||
Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
|
||||
Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
|
||||
|
||||
Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
|
||||
Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
|
||||
})
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LNot (PICF)) { Return (PICM) }
|
||||
Else { Return (APIC) }
|
||||
}
|
||||
}
|
||||
|
||||
Device (PG0B)
|
||||
{
|
||||
// 8132 pcix bridge 2
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(GHCD(HCIN, 0), 0x00010000))
|
||||
}
|
||||
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x22, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x22, 0x01 }) }
|
||||
}
|
||||
|
||||
Name (APIC, Package (0x04)
|
||||
{
|
||||
// Slot A - PIRQ ABCD
|
||||
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1F },// Slot 1
|
||||
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x20 },
|
||||
Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x21 },
|
||||
Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x22 }
|
||||
})
|
||||
Name (PICM, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
|
||||
Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
|
||||
})
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LNot (PICF)) { Return (PICM) }
|
||||
Else { Return (APIC) }
|
||||
}
|
||||
}
|
||||
@@ -1,187 +0,0 @@
|
||||
//
|
||||
// This file is part of the coreboot project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
|
||||
Device (PG0A)
|
||||
{
|
||||
// 8132 pcix bridge
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(GHCD(HCIN, 0), 0x00000000))
|
||||
}
|
||||
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x29, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x29, 0x01 }) }
|
||||
}
|
||||
|
||||
Name (APIC, Package (0x10)
|
||||
{
|
||||
// Slot 1 - PIRQ ABCD
|
||||
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 },
|
||||
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B },
|
||||
// Slot 2 - PIRQ BCDA
|
||||
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0019 },
|
||||
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x001A },
|
||||
Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x001B },
|
||||
Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x0018 },
|
||||
// Slot 3 - PIRQ CDAB
|
||||
Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x001A },
|
||||
Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x001B },
|
||||
Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x0018 },
|
||||
Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x0019 },
|
||||
// Slot 4 - PIRQ DABC
|
||||
Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x001B },
|
||||
Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x0018 },
|
||||
Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x0019 },
|
||||
Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x001A },
|
||||
|
||||
})
|
||||
Name (PICM, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2
|
||||
Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
|
||||
//
|
||||
// Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 2
|
||||
// Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
|
||||
// Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
|
||||
// Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
|
||||
//
|
||||
// Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },//Slot 2
|
||||
// Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
|
||||
// Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
|
||||
// Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
|
||||
//
|
||||
// Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },//Slot 2
|
||||
// Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
|
||||
// Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
|
||||
// Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
|
||||
//
|
||||
})
|
||||
|
||||
Name (DNCG, Ones)
|
||||
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LEqual (^DNCG, Ones)) {
|
||||
Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14
|
||||
Store (0x00, Local1)
|
||||
While (LLess (Local1, 0x10))
|
||||
{
|
||||
// Update the GSI according to HCIN
|
||||
Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
|
||||
Add(Local2, Local0, Local0)
|
||||
Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
|
||||
Increment (Local1)
|
||||
}
|
||||
|
||||
Store (0x00, ^DNCG)
|
||||
|
||||
}
|
||||
|
||||
If (LNot (PICF)) { Return (PICM) }
|
||||
Else { Return (APIC) }
|
||||
}
|
||||
}
|
||||
|
||||
Device (PG0B)
|
||||
{
|
||||
// 8132 pcix bridge 2
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(GHCD(HCIN, 0), 0x00010000))
|
||||
}
|
||||
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x22, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x22, 0x01 }) }
|
||||
}
|
||||
|
||||
Name (APIC, Package (0x10)
|
||||
{
|
||||
// Slot A - PIRQ ABCD
|
||||
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1
|
||||
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 },
|
||||
// Slot A - PIRQ BCDA
|
||||
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0020 },// Slot 1
|
||||
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x0021 },
|
||||
Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x0022 },
|
||||
Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x001F },
|
||||
// Slot A - PIRQ CDAB
|
||||
Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x0021 },// Slot 1
|
||||
Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x0022 },
|
||||
Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x001F },
|
||||
Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x0020 },
|
||||
// Slot A - PIRQ DABC
|
||||
Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x0022 },// Slot 1
|
||||
Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x001F },
|
||||
Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x0020 },
|
||||
Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x0021 },
|
||||
})
|
||||
Name (PICM, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
|
||||
Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
|
||||
|
||||
// Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 1
|
||||
// Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
|
||||
// Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
|
||||
// Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
|
||||
//
|
||||
// Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },//Slot 1
|
||||
// Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
|
||||
// Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
|
||||
// Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
|
||||
//
|
||||
// Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },//Slot 1
|
||||
// Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
|
||||
// Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
|
||||
// Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
|
||||
//
|
||||
})
|
||||
|
||||
Name (DNCG, Ones)
|
||||
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LEqual (^DNCG, Ones)) {
|
||||
Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14
|
||||
Store (0x00, Local1)
|
||||
While (LLess (Local1, 0x10))
|
||||
{
|
||||
// Update the GSI according to HCIN
|
||||
Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
|
||||
Add(Local2, Local0, Local0)
|
||||
Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
|
||||
Increment (Local1)
|
||||
}
|
||||
|
||||
Store (0x00, ^DNCG)
|
||||
|
||||
}
|
||||
|
||||
If (LNot (PICF)) { Return (PICM) }
|
||||
Else { Return (APIC) }
|
||||
}
|
||||
}
|
||||
@@ -1,43 +0,0 @@
|
||||
//
|
||||
// This file is part of the coreboot project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
|
||||
// AMD8151
|
||||
Device (AGPB)
|
||||
{
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(GHCD(HCIN, 0), 0x00010000))
|
||||
}
|
||||
|
||||
Name (APIC, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
|
||||
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }
|
||||
})
|
||||
Name (PICM, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
|
||||
})
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LNot (PICF)) { Return (PICM) }
|
||||
Else { Return (APIC) }
|
||||
}
|
||||
}
|
||||
@@ -1,30 +0,0 @@
|
||||
//
|
||||
// This file is part of the coreboot project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
|
||||
Device (HTXA)
|
||||
{
|
||||
// HTX
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(GHCD(HCIN, 0), 0x00000000))
|
||||
}
|
||||
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x29, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x29, 0x01 }) }
|
||||
}
|
||||
|
||||
}
|
||||
@@ -1,16 +0,0 @@
|
||||
//
|
||||
// This file is part of the coreboot project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
#include "amd8111.asl" //real SB at first
|
||||
#include "amd8132.asl"
|
||||
@@ -1,16 +0,0 @@
|
||||
//
|
||||
// This file is part of the coreboot project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
|
||||
#include "amd8132_2.asl"
|
||||
@@ -1,16 +0,0 @@
|
||||
//
|
||||
// This file is part of the coreboot project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
|
||||
#include "amd8151.asl"
|
||||
@@ -1,16 +0,0 @@
|
||||
//
|
||||
// This file is part of the coreboot project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
|
||||
#include "amd8131_2.asl"
|
||||
@@ -1,16 +0,0 @@
|
||||
//
|
||||
// This file is part of the coreboot project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
|
||||
#include "htx_no_ioapic.asl"
|
||||
@@ -1,16 +0,0 @@
|
||||
//
|
||||
// This file is part of the coreboot project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
|
||||
// #include "w83627hf.asl"
|
||||
@@ -1,179 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <string.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
#include <cbfs.h>
|
||||
|
||||
#include "mb_sysconf.h"
|
||||
#include "mainboard.h"
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
u32 gsi_base = 0x18;
|
||||
|
||||
struct mb_sysconf_t *m;
|
||||
|
||||
m = sysconf.mb;
|
||||
|
||||
/* create all subtables for processors */
|
||||
current = acpi_create_madt_lapics(current);
|
||||
|
||||
/* Write 8111 IOAPIC */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8111,
|
||||
IO_APIC_ADDR, 0);
|
||||
|
||||
/* Write all 8131 IOAPICs */
|
||||
{
|
||||
struct device *dev;
|
||||
struct resource *res;
|
||||
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1,
|
||||
res->base, gsi_base);
|
||||
gsi_base+=7;
|
||||
}
|
||||
}
|
||||
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_2,
|
||||
res->base, gsi_base);
|
||||
gsi_base+=7;
|
||||
}
|
||||
}
|
||||
|
||||
int i;
|
||||
int j = 0;
|
||||
|
||||
for (i = 1; i < sysconf.hc_possible_num; i++) {
|
||||
u32 d = 0;
|
||||
if (!(sysconf.pci1234[i] & 0x1))
|
||||
continue;
|
||||
/* 8131 need to use +4 */
|
||||
switch (sysconf.hcid[i]) {
|
||||
case 1:
|
||||
d = 7;
|
||||
break;
|
||||
case 3:
|
||||
d = 4;
|
||||
break;
|
||||
}
|
||||
switch (sysconf.hcid[i]) {
|
||||
case 1:
|
||||
case 3:
|
||||
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0],
|
||||
res->base, gsi_base);
|
||||
gsi_base+=d;
|
||||
}
|
||||
}
|
||||
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1],
|
||||
res->base, gsi_base);
|
||||
gsi_base+=d;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
j++;
|
||||
}
|
||||
}
|
||||
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 5);
|
||||
/* 0: mean bus 0--->ISA */
|
||||
/* 0: PIC 0 */
|
||||
/* 2: APIC 2 */
|
||||
/* 5 mean: 0101 --> Edge-triggered, Active high*/
|
||||
|
||||
|
||||
/* create all subtables for processors */
|
||||
current = acpi_create_madt_lapic_nmis(current, 5, 1);
|
||||
/* 1: LINT1 connect to NMI */
|
||||
|
||||
return current;
|
||||
}
|
||||
|
||||
unsigned long mainboard_write_acpi_tables(struct device *device,
|
||||
unsigned long current,
|
||||
acpi_rsdp_t *rsdp)
|
||||
{
|
||||
acpi_header_t *ssdtx;
|
||||
const void *p;
|
||||
size_t p_size;
|
||||
|
||||
int i;
|
||||
|
||||
/* same htio, but different possition? We may have to copy,
|
||||
* change HCIN, and recalculate the checknum and add_table
|
||||
*/
|
||||
|
||||
for (i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */
|
||||
const char *file_name;
|
||||
if ((sysconf.pci1234[i] & 1) != 1)
|
||||
continue;
|
||||
u8 c;
|
||||
if (i < 7) {
|
||||
c = (u8) ('4' + i - 1);
|
||||
}
|
||||
else {
|
||||
c = (u8) ('A' + i - 1 - 6);
|
||||
}
|
||||
current = ALIGN(current, 8);
|
||||
printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); /* pci0 and pci1 are in dsdt */
|
||||
ssdtx = (acpi_header_t *)current;
|
||||
switch (sysconf.hcid[i]) {
|
||||
case 1:
|
||||
file_name = CONFIG_CBFS_PREFIX "/ssdt2.aml";
|
||||
break;
|
||||
case 2:
|
||||
file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml";
|
||||
break;
|
||||
case 3: /* 8131 */
|
||||
file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml";
|
||||
break;
|
||||
default:
|
||||
/* HTX no io apic */
|
||||
file_name = CONFIG_CBFS_PREFIX "/ssdt5.aml";
|
||||
}
|
||||
p = cbfs_boot_map_with_leak(
|
||||
file_name,
|
||||
CBFS_TYPE_RAW, &p_size);
|
||||
if (!p || p_size < sizeof(acpi_header_t))
|
||||
continue;
|
||||
memcpy(ssdtx, p, sizeof(acpi_header_t));
|
||||
current += ssdtx->length;
|
||||
memcpy(ssdtx, p, ssdtx->length);
|
||||
update_ssdtx((void *)ssdtx, i);
|
||||
ssdtx->checksum = 0;
|
||||
ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length);
|
||||
acpi_add_table(rsdp, ssdtx);
|
||||
}
|
||||
|
||||
return current;
|
||||
}
|
||||
@@ -1 +0,0 @@
|
||||
Category: server
|
||||
@@ -1,102 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
## Copyright (C) 2007 AMD
|
||||
## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
entries
|
||||
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
393 3 r 0 unused
|
||||
#394 7 unused
|
||||
401 1 e 1 interleave_chip_selects
|
||||
402 1 e 1 interleave_nodes
|
||||
403 1 e 1 interleave_memory_channels
|
||||
404 2 e 8 max_mem_clock
|
||||
406 1 e 2 multi_core
|
||||
412 4 e 6 debug_level
|
||||
416 5 e 10 ecc_scrub_rate
|
||||
440 4 e 9 slow_cpu
|
||||
444 1 e 1 nmi
|
||||
445 1 e 1 gart
|
||||
446 1 e 1 power_on_after_fail
|
||||
456 1 e 1 ECC_memory
|
||||
457 1 e 1 ECC_redirection
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
6 0 Emergency
|
||||
6 1 Alert
|
||||
6 2 Critical
|
||||
6 3 Error
|
||||
6 4 Warning
|
||||
6 5 Notice
|
||||
6 6 Information
|
||||
6 7 Debug
|
||||
6 8 Spew
|
||||
8 0 DDR2-800
|
||||
8 1 DDR2-667
|
||||
8 2 DDR2-533
|
||||
8 3 DDR2-400
|
||||
9 0 off
|
||||
9 1 87.5%
|
||||
9 2 75.0%
|
||||
9 3 62.5%
|
||||
9 4 50.0%
|
||||
9 5 37.5%
|
||||
9 6 25.0%
|
||||
9 7 12.5%
|
||||
10 0 Disabled
|
||||
10 1 40ns
|
||||
10 2 80ns
|
||||
10 3 160ns
|
||||
10 4 320ns
|
||||
10 5 640ns
|
||||
10 6 1.28us
|
||||
10 7 2.56us
|
||||
10 8 5.12us
|
||||
10 9 10.2us
|
||||
10 10 20.5us
|
||||
10 11 41us
|
||||
10 12 81.9us
|
||||
10 13 163.8us
|
||||
10 14 327.7us
|
||||
10 15 655.4us
|
||||
10 16 1.31ms
|
||||
10 17 2.62ms
|
||||
10 18 5.24ms
|
||||
10 19 10.49ms
|
||||
10 20 20.97sms
|
||||
10 21 42ms
|
||||
10 22 84ms
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
@@ -1,137 +0,0 @@
|
||||
chip northbridge/amd/amdfam10/root_complex
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_F_1207 #L1 and DDR2
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device domain 0 on
|
||||
subsystemid 0x1022 0x2b80 inherit
|
||||
chip northbridge/amd/amdfam10
|
||||
device pci 18.0 on # northbridge
|
||||
# devices on link 0, link 0 == LDT 0
|
||||
chip southbridge/amd/amd8132
|
||||
# the on/off keyword is mandatory
|
||||
device pci 0.0 on end
|
||||
device pci 0.1 on end
|
||||
device pci 1.0 on end
|
||||
device pci 1.1 on end
|
||||
end
|
||||
chip southbridge/amd/amd8111
|
||||
# this "device pci 0.0" is the parent the next one
|
||||
# PCI bridge
|
||||
device pci 0.0 on
|
||||
device pci 0.0 on end
|
||||
device pci 0.1 on end
|
||||
device pci 0.2 off end
|
||||
device pci 1.0 off end
|
||||
end
|
||||
device pci 1.0 on
|
||||
chip superio/winbond/w83627hf
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.2 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 off # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.6 off # CIR
|
||||
io 0x60 = 0x100
|
||||
end
|
||||
device pnp 2e.7 off # GAME_MIDI_GIPO1
|
||||
io 0x60 = 0x220
|
||||
io 0x62 = 0x300
|
||||
irq 0x70 = 9
|
||||
end
|
||||
device pnp 2e.8 off end # GPIO2
|
||||
device pnp 2e.9 off end # GPIO3
|
||||
device pnp 2e.a off end # ACPI
|
||||
device pnp 2e.b on # HW Monitor
|
||||
io 0x60 = 0x290
|
||||
irq 0x70 = 5
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 1.1 on end
|
||||
device pci 1.2 on end
|
||||
device pci 1.3 on
|
||||
chip drivers/i2c/i2cmux2 # pca9556 smbus mux
|
||||
chip drivers/i2c/i2cmux2 # pca9556 smbus mux
|
||||
device i2c 18 on #0 pca9516 1
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
end
|
||||
device i2c 18 on #1 pca9516 2
|
||||
chip drivers/generic/generic #dimm 1-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end # acpi
|
||||
device pci 1.5 off end
|
||||
device pci 1.6 off end
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
end
|
||||
end # device pci 18.0
|
||||
|
||||
device pci 18.0 on end
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
device pci 18.4 on end
|
||||
# device pci 00.5 on end
|
||||
end
|
||||
end #domain
|
||||
#for node 32 to node 63
|
||||
# device domain 0 on
|
||||
# chip northbridge/amd/amdfam10
|
||||
# device pci 00.0 on end# northbridge
|
||||
# device pci 00.0 on end
|
||||
# device pci 00.0 on end
|
||||
# device pci 00.0 on end
|
||||
# device pci 00.1 on end
|
||||
# device pci 00.2 on end
|
||||
# device pci 00.3 on end
|
||||
# device pci 00.4 on end
|
||||
# device pci 00.5 on end
|
||||
# end
|
||||
# end #domain
|
||||
|
||||
end
|
||||
@@ -1,244 +0,0 @@
|
||||
//
|
||||
// This file is part of the coreboot project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock ("DSDT.aml", "DSDT", 1, OEM_ID, ACPI_TABLE_CREATOR, 100925440)
|
||||
{
|
||||
|
||||
// Scope (_PR)
|
||||
// {
|
||||
// Device (CPU0) {
|
||||
// Name (_HID, "ACPI0007")
|
||||
// Name (_UID, 0)
|
||||
// }
|
||||
// Device (CPU1) {
|
||||
// Name (_HID, "ACPI0007")
|
||||
// Name (_UID, 1)
|
||||
// }
|
||||
// Device (CPU2) {
|
||||
// Name (_HID, "ACPI0007")
|
||||
// Name (_UID, 2)
|
||||
// }
|
||||
// Device (CPU3) {
|
||||
// Name (_HID, "ACPI0007")
|
||||
// Name (_UID, 3)
|
||||
// }
|
||||
// }
|
||||
|
||||
Method (FWSO, 0, NotSerialized) { }
|
||||
|
||||
|
||||
Scope (_SB)
|
||||
{
|
||||
Device (PCI0)
|
||||
{
|
||||
// BUS0 root bus
|
||||
External (BUSN)
|
||||
External (MMIO)
|
||||
External (PCIO)
|
||||
External (SBLK)
|
||||
External (TOM1)
|
||||
External (HCLK)
|
||||
External (SBDN)
|
||||
External (HCDN)
|
||||
External (CBST)
|
||||
External (CBB)
|
||||
External (CBS2)
|
||||
External (CBB2)
|
||||
|
||||
Name (_HID, EisaId ("PNP0A03"))
|
||||
Name (_UID, 0x01)
|
||||
|
||||
Name (HCIN, 0x00) // HC1
|
||||
|
||||
Method (_BBN, 0, NotSerialized)
|
||||
{
|
||||
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh
|
||||
IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h
|
||||
IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h
|
||||
|
||||
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
0x0000, // Address Space Granularity
|
||||
0x8100, // Address Range Minimum
|
||||
0xFFFF, // Address Range Maximum
|
||||
0x0000, // Address Translation Offset
|
||||
0x7F00,,,
|
||||
, TypeStatic) //8100h-FFFFh
|
||||
|
||||
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
|
||||
0x00000000, // Address Space Granularity
|
||||
0x000C0000, // Address Range Minimum
|
||||
0x000CFFFF, // Address Range Maximum
|
||||
0x00000000, // Address Translation Offset
|
||||
0x00010000,,,
|
||||
, AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh
|
||||
|
||||
Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF
|
||||
|
||||
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
0x0000, // Address Space Granularity
|
||||
0x0000, // Address Range Minimum
|
||||
0x03AF, // Address Range Maximum
|
||||
0x0000, // Address Translation Offset
|
||||
0x03B0,,,
|
||||
, TypeStatic) //0-CF7h
|
||||
|
||||
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
0x0000, // Address Space Granularity
|
||||
0x03E0, // Address Range Minimum
|
||||
0x0CF7, // Address Range Maximum
|
||||
0x0000, // Address Translation Offset
|
||||
0x0918,,,
|
||||
, TypeStatic) //0-CF7h
|
||||
})
|
||||
\_SB.OSVR ()
|
||||
CreateDWordField (BUF0, 0x3E, VLEN)
|
||||
CreateDWordField (BUF0, 0x36, VMAX)
|
||||
CreateDWordField (BUF0, 0x32, VMIN)
|
||||
ShiftLeft (VGA1, 0x09, Local0)
|
||||
Add (VMIN, Local0, VMAX)
|
||||
Decrement (VMAX)
|
||||
Store (Local0, VLEN)
|
||||
Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
|
||||
Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
|
||||
Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
|
||||
Return (Local3)
|
||||
}
|
||||
|
||||
#include "acpi/pci0_hc.asl"
|
||||
|
||||
}
|
||||
Device (PCI1)
|
||||
{
|
||||
Name (_HID, "PNP0A03")
|
||||
Name (_UID, 0x02)
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (\_SB.PCI0.CBST)
|
||||
}
|
||||
Method (_BBN, 0, NotSerialized)
|
||||
{
|
||||
Return (\_SB.PCI0.CBB) // 0 or 0xff
|
||||
}
|
||||
|
||||
}
|
||||
Device (PCI2)
|
||||
{
|
||||
Name (_HID, "PNP0A03")
|
||||
Name (_UID, 0x02)
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (\_SB.PCI0.CBS2)
|
||||
}
|
||||
Method (_BBN, 0, NotSerialized)
|
||||
{
|
||||
Return (\_SB.PCI0.CBB2)// 0xfe
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Scope (_GPE)
|
||||
{
|
||||
Method (_L08, 0, NotSerialized)
|
||||
{
|
||||
Notify (\_SB.PCI0, 0x02) //PME# Wakeup
|
||||
}
|
||||
|
||||
Method (_L0F, 0, NotSerialized)
|
||||
{
|
||||
Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup
|
||||
}
|
||||
|
||||
Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B
|
||||
{
|
||||
Notify (\_SB.PCI0.PG0B, 0x02)
|
||||
}
|
||||
|
||||
Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A
|
||||
{
|
||||
Notify (\_SB.PCI0.PG0A, 0x02)
|
||||
}
|
||||
}
|
||||
|
||||
Method (_PTS, 1, NotSerialized)
|
||||
{
|
||||
Or (Arg0, 0xF0, Local0)
|
||||
Store (Local0, DBG1)
|
||||
}
|
||||
//
|
||||
// Method (_WAK, 1, NotSerialized)
|
||||
// {
|
||||
// Or (Arg0, 0xE0, Local0)
|
||||
// Store (Local0, DBG1)
|
||||
// }
|
||||
|
||||
Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode
|
||||
Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method
|
||||
{
|
||||
Store (Arg0, PICF)
|
||||
}
|
||||
|
||||
OperationRegion (DEBG, SystemIO, 0x80, 0x01)
|
||||
Field (DEBG, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
DBG1, 8
|
||||
}
|
||||
|
||||
OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04)
|
||||
Field (EXTM, WordAcc, Lock, Preserve)
|
||||
{
|
||||
AMEM, 32
|
||||
}
|
||||
|
||||
OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01)
|
||||
Field (VGAM, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
VGA1, 8
|
||||
}
|
||||
|
||||
OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
|
||||
Field (GRAM, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
Offset (0x10),
|
||||
FLG0, 8
|
||||
}
|
||||
|
||||
OperationRegion (GSTS, SystemIO, 0xC028, 0x02)
|
||||
Field (GSTS, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
, 4,
|
||||
IRQR, 1
|
||||
}
|
||||
|
||||
OperationRegion (Z007, SystemIO, 0x21, 0x01)
|
||||
Field (Z007, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Z008, 8
|
||||
}
|
||||
|
||||
OperationRegion (Z009, SystemIO, 0xA1, 0x01)
|
||||
Field (Z009, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Z00A, 8
|
||||
}
|
||||
|
||||
#include <northbridge/amd/amdfam10/amdfam10_util.asl>
|
||||
}
|
||||
@@ -1,159 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2005 Stefan Reinauer <stepan@openbios.org>
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
* ACPI - create the Fixed ACPI Description Tables (FADT)
|
||||
*/
|
||||
|
||||
|
||||
#include <string.h>
|
||||
#include <console/console.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <version.h>
|
||||
|
||||
extern u32 pm_base; /* pm_base should be set in sb ACPI */
|
||||
|
||||
void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
|
||||
|
||||
acpi_header_t *header=&(fadt->header);
|
||||
|
||||
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
|
||||
|
||||
/* Prepare the header */
|
||||
memset((void *)fadt,0,sizeof(acpi_fadt_t));
|
||||
memcpy(header->signature,"FACP",4);
|
||||
header->length = sizeof(acpi_fadt_t);
|
||||
header->revision = get_acpi_table_revision(FADT);
|
||||
memcpy(header->oem_id,OEM_ID,6);
|
||||
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
|
||||
memcpy(header->asl_compiler_id,ASLC,4);
|
||||
header->asl_compiler_revision = asl_revision;
|
||||
|
||||
fadt->firmware_ctrl=(u32)facs;
|
||||
fadt->dsdt= (u32)dsdt;
|
||||
/* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
|
||||
fadt->preferred_pm_profile = 0x03;
|
||||
fadt->sci_int = 9;
|
||||
/* disable system management mode by setting to 0: */
|
||||
fadt->smi_cmd = 0;/* pm_base+0x2f */
|
||||
fadt->acpi_enable = 0xf0;
|
||||
fadt->acpi_disable = 0xf1;
|
||||
fadt->s4bios_req = 0x0;
|
||||
fadt->pstate_cnt = 0x00; /* SMM is not used for p-state control */
|
||||
|
||||
fadt->pm1a_evt_blk = pm_base;
|
||||
fadt->pm1b_evt_blk = 0x0000;
|
||||
fadt->pm1a_cnt_blk = pm_base+0x04;
|
||||
fadt->pm1b_cnt_blk = 0x0000;
|
||||
fadt->pm2_cnt_blk = 0x0000;
|
||||
fadt->pm_tmr_blk = pm_base+0x08;
|
||||
fadt->gpe0_blk = pm_base+0x20;
|
||||
fadt->gpe1_blk = pm_base+0xb0;
|
||||
|
||||
fadt->pm1_evt_len = 4;
|
||||
fadt->pm1_cnt_len = 2;
|
||||
fadt->pm2_cnt_len = 0;
|
||||
fadt->pm_tmr_len = 4;
|
||||
fadt->gpe0_blk_len = 4;
|
||||
fadt->gpe1_blk_len = 8;
|
||||
fadt->gpe1_base = 16;
|
||||
|
||||
fadt->cst_cnt = 0x00;/* SMM is not used for p-state control */
|
||||
fadt->p_lvl2_lat = 101;
|
||||
fadt->p_lvl3_lat = 1001;
|
||||
fadt->flush_size = 0;
|
||||
fadt->flush_stride = 0;
|
||||
fadt->duty_offset = 1;
|
||||
fadt->duty_width = 3;
|
||||
fadt->day_alrm = 0; /* 0x7d these have to be */
|
||||
fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
|
||||
fadt->century = 0; /* 0x7f to make rtc alrm work */
|
||||
fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
|
||||
fadt->flags = 0x25;
|
||||
|
||||
fadt->res2 = 0;
|
||||
|
||||
fadt->reset_reg.space_id = 1;
|
||||
fadt->reset_reg.bit_width = 8;
|
||||
fadt->reset_reg.bit_offset = 0;
|
||||
fadt->reset_reg.access_size = 0;
|
||||
fadt->reset_reg.addrl = 0xcf9;
|
||||
fadt->reset_reg.addrh = 0x0;
|
||||
|
||||
fadt->reset_value = 6;
|
||||
fadt->x_firmware_ctl_l = (u32)facs;
|
||||
fadt->x_firmware_ctl_h = 0;
|
||||
fadt->x_dsdt_l = (u32)dsdt;
|
||||
fadt->x_dsdt_h = 0;
|
||||
|
||||
fadt->x_pm1a_evt_blk.space_id = 1;
|
||||
fadt->x_pm1a_evt_blk.bit_width = 32;
|
||||
fadt->x_pm1a_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_evt_blk.access_size = 0;
|
||||
fadt->x_pm1a_evt_blk.addrl = pm_base;
|
||||
fadt->x_pm1a_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_evt_blk.space_id = 1;
|
||||
fadt->x_pm1b_evt_blk.bit_width = 4;
|
||||
fadt->x_pm1b_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_evt_blk.access_size = 0;
|
||||
fadt->x_pm1b_evt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1a_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1a_cnt_blk.bit_width = 16;
|
||||
fadt->x_pm1a_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_cnt_blk.access_size = 0;
|
||||
fadt->x_pm1a_cnt_blk.addrl = pm_base+4;
|
||||
fadt->x_pm1a_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1b_cnt_blk.bit_width = 2;
|
||||
fadt->x_pm1b_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_cnt_blk.access_size = 0;
|
||||
fadt->x_pm1b_cnt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm2_cnt_blk.space_id = 1;
|
||||
fadt->x_pm2_cnt_blk.bit_width = 0;
|
||||
fadt->x_pm2_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm2_cnt_blk.access_size = 0;
|
||||
fadt->x_pm2_cnt_blk.addrl = 0x0;
|
||||
fadt->x_pm2_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm_tmr_blk.space_id = 1;
|
||||
fadt->x_pm_tmr_blk.bit_width = 32;
|
||||
fadt->x_pm_tmr_blk.bit_offset = 0;
|
||||
fadt->x_pm_tmr_blk.access_size = 0;
|
||||
fadt->x_pm_tmr_blk.addrl = pm_base+0x08;
|
||||
fadt->x_pm_tmr_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_gpe0_blk.space_id = 1;
|
||||
fadt->x_gpe0_blk.bit_width = 32;
|
||||
fadt->x_gpe0_blk.bit_offset = 0;
|
||||
fadt->x_gpe0_blk.access_size = 0;
|
||||
fadt->x_gpe0_blk.addrl = pm_base+0x20;
|
||||
fadt->x_gpe0_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_gpe1_blk.space_id = 1;
|
||||
fadt->x_gpe1_blk.bit_width = 64;
|
||||
fadt->x_gpe1_blk.bit_offset = 16;
|
||||
fadt->x_gpe1_blk.access_size = 0;
|
||||
fadt->x_gpe1_blk.addrl = pm_base+0xb0;
|
||||
fadt->x_gpe1_blk.addrh = 0x0;
|
||||
|
||||
header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
|
||||
}
|
||||
@@ -1,167 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <stdint.h>
|
||||
#include <cpu/amd/multicore.h>
|
||||
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
#include <stdlib.h>
|
||||
#include "mb_sysconf.h"
|
||||
|
||||
/* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */
|
||||
struct mb_sysconf_t mb_sysconf;
|
||||
|
||||
|
||||
static u32 get_hcid(u32 i)
|
||||
{
|
||||
u32 id = 0;
|
||||
u32 busn = (sysconf.pci1234[i] >> 12) & 0xff;
|
||||
u32 devn = sysconf.hcdn[i] & 0xff;
|
||||
struct device *dev;
|
||||
|
||||
dev = dev_find_slot(busn, PCI_DEVFN(devn,0));
|
||||
|
||||
if (dev == NULL)
|
||||
die("ERROR - could not find PCI %02x:%02x.0\n", busn, PCI_DEVFN(devn, 0));
|
||||
|
||||
switch (dev->device) {
|
||||
case 0x7458: /* 8132 */
|
||||
id = 1;
|
||||
break;
|
||||
case 0x7454: /* 8151 */
|
||||
id = 2;
|
||||
break;
|
||||
case 0x7450: /* 8131 */
|
||||
id = 3;
|
||||
break;
|
||||
}
|
||||
/* we may need more way to find out hcid: subsystem id? GPIO read ? */
|
||||
/* we need use id for 1. bus num, 2. mptable, 3. ACPI table */
|
||||
return id;
|
||||
}
|
||||
|
||||
void get_bus_conf(void)
|
||||
{
|
||||
u32 apicid_base;
|
||||
|
||||
struct device *dev;
|
||||
int i, j;
|
||||
struct mb_sysconf_t *m;
|
||||
|
||||
sysconf.mb = &mb_sysconf;
|
||||
|
||||
m = sysconf.mb;
|
||||
|
||||
get_default_pci1234(32);
|
||||
|
||||
sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
|
||||
m->sbdn3 = sysconf.hcdn[0] & 0xff;
|
||||
|
||||
m->bus_8132_0 = (sysconf.pci1234[0] >> 12) & 0xff;
|
||||
m->bus_8111_0 = m->bus_8132_0;
|
||||
|
||||
/* 8111 */
|
||||
dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
|
||||
if (dev) {
|
||||
m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8111_0, sysconf.sbdn);
|
||||
}
|
||||
|
||||
/* 8132-1 */
|
||||
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3,0));
|
||||
if (dev) {
|
||||
m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3);
|
||||
}
|
||||
|
||||
/* 8132-2 */
|
||||
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1,0));
|
||||
if (dev) {
|
||||
m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3+1);
|
||||
}
|
||||
|
||||
/* HT chain 1 */
|
||||
j = 0;
|
||||
for (i = 1; i < sysconf.hc_possible_num; i++) {
|
||||
if (!(sysconf.pci1234[i] & 0x1))
|
||||
continue;
|
||||
|
||||
/* check hcid type here */
|
||||
sysconf.hcid[i] = get_hcid(i);
|
||||
|
||||
switch (sysconf.hcid[i]) {
|
||||
|
||||
case 1: /* 8132 */
|
||||
case 3: /* 8131 */
|
||||
|
||||
m->bus_8132a[j][0] = (sysconf.pci1234[i] >> 12) & 0xff;
|
||||
|
||||
m->sbdn3a[j] = sysconf.hcdn[i] & 0xff;
|
||||
|
||||
/* 8132-1 */
|
||||
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j],0));
|
||||
if (dev) {
|
||||
m->bus_8132a[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]);
|
||||
}
|
||||
|
||||
/* 8132-2 */
|
||||
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1,0));
|
||||
if (dev) {
|
||||
m->bus_8132a[j][2] = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]+1);
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case 2: /* 8151 */
|
||||
|
||||
m->bus_8151[j][0] = (sysconf.pci1234[i] >> 12) & 0xff;
|
||||
m->sbdn5[j] = sysconf.hcdn[i] & 0xff;
|
||||
/* 8151 */
|
||||
dev = dev_find_slot(m->bus_8151[j][0], PCI_DEVFN(m->sbdn5[j]+1, 0));
|
||||
|
||||
if (dev) {
|
||||
m->bus_8151[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8151[j][0], m->sbdn5[j]+1);
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
j++;
|
||||
}
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
apicid_base = 0;
|
||||
m->apicid_8111 = apicid_base + 0;
|
||||
m->apicid_8132_1 = apicid_base + 1;
|
||||
m->apicid_8132_2 = apicid_base + 2;
|
||||
for (i = 0; i < j; i++) {
|
||||
m->apicid_8132a[i][0] = apicid_base + 3 + i * 2;
|
||||
m->apicid_8132a[i][1] = apicid_base + 3 + i * 2 + 1;
|
||||
}
|
||||
}
|
||||
@@ -1,141 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
#include "mb_sysconf.h"
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
|
||||
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
|
||||
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
|
||||
u8 slot, u8 rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
u32 slot_num;
|
||||
u8 *v;
|
||||
|
||||
u8 sum = 0;
|
||||
int i;
|
||||
|
||||
struct mb_sysconf_t *m;
|
||||
|
||||
m = sysconf.mb;
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be between 0xf0000 & 0x100000 */
|
||||
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (u8 *) (addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
pirq->rtr_bus = m->bus_8111_0;
|
||||
pirq->rtr_devfn = ((sysconf.sbdn + 1) << 3) | 0;
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
pirq->rtr_vendor = 0x1022;
|
||||
pirq->rtr_device = 0x746b;
|
||||
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *)(&pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
|
||||
/* pci bridge */
|
||||
write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn + 1) << 3) | 0,
|
||||
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
|
||||
0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
|
||||
/* pcix bridge */
|
||||
|
||||
int j = 0;
|
||||
|
||||
for (i = 1; i < sysconf.hc_possible_num; i++) {
|
||||
if (!(sysconf.pci1234[i] & 0x1))
|
||||
continue;
|
||||
u32 busn = (sysconf.pci1234[i] >> 12) & 0xff;
|
||||
u32 devn = sysconf.hcdn[i] & 0xff;
|
||||
|
||||
write_pirq_info(pirq_info, busn, PCI_DEVFN(devn, 0), 0x1, 0xdef8,
|
||||
0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
j++;
|
||||
|
||||
}
|
||||
|
||||
#if CONFIG_CBB
|
||||
write_pirq_info(pirq_info, CONFIG_CBB, PCI_DEVFN(0, 0), 0x1, 0xdef8, 0x2,
|
||||
0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
if (sysconf.nodes > 32) {
|
||||
write_pirq_info(pirq_info, CONFIG_CBB - 1, PCI_DEVFN(0, 0), 0x1,
|
||||
0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8,
|
||||
0, 0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
}
|
||||
#endif
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++) {
|
||||
sum += v[i];
|
||||
}
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "done.\n");
|
||||
|
||||
return (unsigned long)pirq_info;
|
||||
}
|
||||
@@ -1,25 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/device.h>
|
||||
#include <arch/acpi.h>
|
||||
#include "mainboard.h"
|
||||
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
@@ -1,14 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
unsigned long mainboard_write_acpi_tables(struct device *device, unsigned long start, acpi_rsdp_t *rsdp);
|
||||
@@ -1,38 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MB_SYSCONF_H
|
||||
|
||||
#define MB_SYSCONF_H
|
||||
|
||||
struct mb_sysconf_t {
|
||||
u8 bus_8132_0;
|
||||
u8 bus_8132_1;
|
||||
u8 bus_8132_2;
|
||||
u8 bus_8111_0;
|
||||
u8 bus_8111_1;
|
||||
u8 bus_8132a[31][3];
|
||||
u8 bus_8151[31][2];
|
||||
|
||||
u32 apicid_8111;
|
||||
u32 apicid_8132_1;
|
||||
u32 apicid_8132_2;
|
||||
u32 apicid_8132a[31][2];
|
||||
u32 sbdn3;
|
||||
u32 sbdn3a[31];
|
||||
u32 sbdn5[31];
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -1,192 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <stdint.h>
|
||||
#if CONFIG(LOGICAL_CPUS)
|
||||
#include <cpu/amd/multicore.h>
|
||||
#endif
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
#include "mb_sysconf.h"
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
int i, j, bus_isa;
|
||||
struct mp_config_table *mc;
|
||||
struct mb_sysconf_t *m;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
m = sysconf.mb;
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address*/
|
||||
smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); /* 8111 */
|
||||
{
|
||||
struct device *dev;
|
||||
struct resource *res;
|
||||
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, m->apicid_8132_1, 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, m->apicid_8132_2, 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
|
||||
j = 0;
|
||||
|
||||
for (i = 1; i < sysconf.hc_possible_num; i++) {
|
||||
if (!(sysconf.pci1234[i] & 0x1))
|
||||
continue;
|
||||
|
||||
switch (sysconf.hcid[i]) {
|
||||
case 1:
|
||||
case 3:
|
||||
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
j++;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0);
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
/* ??? What */
|
||||
smp_write_pci_intsrc(mc, mp_INT, m->bus_8111_0, sysconf.sbdn+1, 3, m->apicid_8111, 0x13);
|
||||
|
||||
/* Onboard AMD USB */
|
||||
smp_write_pci_intsrc(mc, mp_INT, m->bus_8111_1, 0, 3, m->apicid_8111, 0x13);
|
||||
|
||||
/* Slot 3 PCI 32 */
|
||||
for (i = 0; i < 4; i++) {
|
||||
smp_write_pci_intsrc(mc, mp_INT, m->bus_8111_1, 5, i, m->apicid_8111, 0x10 + (1+i)%4); /* 16 */
|
||||
}
|
||||
|
||||
|
||||
/* Slot 4 PCI 32 */
|
||||
for (i = 0; i < 4; i++) {
|
||||
smp_write_pci_intsrc(mc, mp_INT, m->bus_8111_1, 4, i, m->apicid_8111, 0x10 + (0+i)%4); /* 16 */
|
||||
}
|
||||
|
||||
|
||||
/* Slot 1 PCI-X 133/100/66 */
|
||||
for (i = 0; i < 4; i++) {
|
||||
smp_write_pci_intsrc(mc, mp_INT, m->bus_8132_2, 1, i, m->apicid_8132_2, (0+i)%4);
|
||||
}
|
||||
|
||||
|
||||
/* Slot 2 PCI-X 133/100/66 */
|
||||
for (i = 0; i < 4; i++) {
|
||||
smp_write_pci_intsrc(mc, mp_INT, m->bus_8132_1, 1, i, m->apicid_8132_1, (1+i)%4); /* 25 */
|
||||
}
|
||||
|
||||
j = 0;
|
||||
|
||||
for (i = 1; i < sysconf.hc_possible_num; i++) {
|
||||
if (!(sysconf.pci1234[i] & 0x1))
|
||||
continue;
|
||||
int ii;
|
||||
int jj;
|
||||
struct device *dev;
|
||||
struct resource *res;
|
||||
switch (sysconf.hcid[i]) {
|
||||
case 1:
|
||||
case 3:
|
||||
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
for (jj = 0; jj < 4; jj++) {
|
||||
/* Slot 1 PCI-X 133/100/66 */
|
||||
for (ii = 0; ii < 4; ii++) {
|
||||
smp_write_pci_intsrc(mc, mp_INT, m->bus_8132a[j][1], jj, ii, m->apicid_8132a[j][0], (jj+ii)%4);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
for (jj = 0; jj < 4; jj++) {
|
||||
/* Slot 2 PCI-X 133/100/66 */
|
||||
for (ii = 0; ii < 4; ii++) {
|
||||
smp_write_pci_intsrc(mc, mp_INT, m->bus_8132a[j][2], jj, ii, m->apicid_8132a[j][1], (jj+ii)%4); /* 25 */
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
break;
|
||||
case 2:
|
||||
|
||||
/* Slot AGP */
|
||||
smp_write_pci_intsrc(mc, mp_INT, m->bus_8151[j][1], 0x0, 0, m->apicid_8111, 0x11);
|
||||
break;
|
||||
}
|
||||
|
||||
j++;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
mptable_lintsrc(mc, bus_isa);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
@@ -1,273 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <commonlib/helpers.h>
|
||||
#include <northbridge/amd/amdfam10/amdfam10.h>
|
||||
|
||||
void setup_mb_resource_map(void)
|
||||
{
|
||||
static const unsigned int register_values[] = {
|
||||
/* Careful set limit registers before base registers which contain the enables */
|
||||
/* DRAM Limit i Registers
|
||||
* F1:0x44 i = 0
|
||||
* F1:0x4C i = 1
|
||||
* F1:0x54 i = 2
|
||||
* F1:0x5C i = 3
|
||||
* F1:0x64 i = 4
|
||||
* F1:0x6C i = 5
|
||||
* F1:0x74 i = 6
|
||||
* F1:0x7C i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 3] Reserved
|
||||
* [10: 8] Interleave select
|
||||
* specifies the values of A[14:12] to use with interleave enable.
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Limit Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40 bit address
|
||||
* that define the end of the DRAM region.
|
||||
*/
|
||||
/* Don't touch it, we need it for CAR with FAM10 */
|
||||
ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001,
|
||||
ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002,
|
||||
ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003,
|
||||
ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004,
|
||||
ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005,
|
||||
ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006,
|
||||
ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
|
||||
/* DRAM Base i Registers
|
||||
* F1:0x40 i = 0
|
||||
* F1:0x48 i = 1
|
||||
* F1:0x50 i = 2
|
||||
* F1:0x58 i = 3
|
||||
* F1:0x60 i = 4
|
||||
* F1:0x68 i = 5
|
||||
* F1:0x70 i = 6
|
||||
* F1:0x78 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 7: 2] Reserved
|
||||
* [10: 8] Interleave Enable
|
||||
* 000 = No interleave
|
||||
* 001 = Interleave on A[12] (2 nodes)
|
||||
* 010 = reserved
|
||||
* 011 = Interleave on A[12] and A[14] (4 nodes)
|
||||
* 100 = reserved
|
||||
* 101 = reserved
|
||||
* 110 = reserved
|
||||
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
|
||||
* [15:11] Reserved
|
||||
* [13:16] DRAM Base Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40-bit address
|
||||
* that define the start of the DRAM region.
|
||||
*/
|
||||
/* don't touch it, we need it for CAR with FAM10 */
|
||||
ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000,
|
||||
ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
* F1:0x8C i = 1
|
||||
* F1:0x94 i = 2
|
||||
* F1:0x9C i = 3
|
||||
* F1:0xA4 i = 4
|
||||
* F1:0xAC i = 5
|
||||
* F1:0xB4 i = 6
|
||||
* F1:0xBC i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Reserved
|
||||
* [ 6: 6] Reserved
|
||||
* [ 7: 7] Non-Posted
|
||||
* 0 = CPU writes may be posted
|
||||
* 1 = CPU writes must be non-posted
|
||||
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
|
||||
* This field defines the upp address bits of a 40-bit address that
|
||||
* defines the end of a memory-mapped I/O region n
|
||||
*/
|
||||
ADDRMAP_REG(0x84), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x8C), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x94), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0x9C), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xA4), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xAC), 0x00000048, 0x00000000,
|
||||
ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Base i Registers
|
||||
* F1:0x80 i = 0
|
||||
* F1:0x88 i = 1
|
||||
* F1:0x90 i = 2
|
||||
* F1:0x98 i = 3
|
||||
* F1:0xA0 i = 4
|
||||
* F1:0xA8 i = 5
|
||||
* F1:0xB0 i = 6
|
||||
* F1:0xB8 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Cpu Disable
|
||||
* 0 = Cpu can use this I/O range
|
||||
* 1 = Cpu requests do not use this I/O range
|
||||
* [ 3: 3] Lock
|
||||
* 0 = base/limit registers i are read/write
|
||||
* 1 = base/limit registers i are read-only
|
||||
* [ 7: 4] Reserved
|
||||
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
|
||||
* This field defines the upper address bits of a 40bit address
|
||||
* that defines the start of memory-mapped I/O region i
|
||||
*/
|
||||
ADDRMAP_REG(0x80), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x88), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x90), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0x98), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000,
|
||||
ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
|
||||
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
* F1:0xCC i = 1
|
||||
* F1:0xD4 i = 2
|
||||
* F1:0xDC i = 3
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = reserved
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Limit Address i
|
||||
* This field defines the end of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000,
|
||||
ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000,
|
||||
ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
|
||||
|
||||
/* PCI I/O Base i Registers
|
||||
* F1:0xC0 i = 0
|
||||
* F1:0xC8 i = 1
|
||||
* F1:0xD0 i = 2
|
||||
* F1:0xD8 i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 3: 2] Reserved
|
||||
* [ 4: 4] VGA Enable
|
||||
* 0 = VGA matches Disabled
|
||||
* 1 = matches all address < 64K and where A[9:0] is in the
|
||||
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
|
||||
* [ 5: 5] ISA Enable
|
||||
* 0 = ISA matches Disabled
|
||||
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
|
||||
* from matching agains this base/limit pair
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Base i
|
||||
* This field defines the start of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000,
|
||||
ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000,
|
||||
ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
|
||||
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
* F1:0xE8 i = 2
|
||||
* F1:0xEC i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Device Number Compare Enable
|
||||
* 0 = The ranges are based on bus number
|
||||
* 1 = The ranges are ranges of devices on bus 0
|
||||
* [ 3: 3] Reserved
|
||||
* [ 6: 4] Destination Node
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 7] Reserved
|
||||
* [ 9: 8] Destination Link
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 - Reserved
|
||||
* [15:10] Reserved
|
||||
* [23:16] Bus Number Base i
|
||||
* This field defines the lowest bus number in configuration region i
|
||||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration regin i
|
||||
*/
|
||||
/* AMD 8111 on link0 of CPU 0 */
|
||||
ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000,
|
||||
ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000,
|
||||
ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
|
||||
};
|
||||
|
||||
int max;
|
||||
max = ARRAY_SIZE(register_values);
|
||||
setup_resource_map(register_values, max);
|
||||
}
|
||||
@@ -1,334 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#define SYSTEM_TYPE 0 /* SERVER */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <console/console.h>
|
||||
#include <timestamp.h>
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
#include <spd.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include <cpu/amd/car.h>
|
||||
#include <cpu/amd/msr.h>
|
||||
#include <superio/winbond/common/winbond.h>
|
||||
#include <superio/winbond/w83627hf/w83627hf.h>
|
||||
#include <northbridge/amd/amdfam10/raminit.h>
|
||||
#include <northbridge/amd/amdht/ht_wrapper.h>
|
||||
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
|
||||
#include <arch/early_variables.h>
|
||||
#include <cbmem.h>
|
||||
#include "southbridge/amd/amd8111/early_smbus.c"
|
||||
#include "southbridge/amd/amd8111/early_ctrl.c"
|
||||
|
||||
#include "cpu/amd/quadcore/quadcore.c"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
|
||||
|
||||
int spd_read_byte(unsigned int device, unsigned int address);
|
||||
|
||||
static void memreset_setup(void)
|
||||
{
|
||||
/* GPIO on amd8111 to enable MEMRST ???? */
|
||||
outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); /* REVC_MEMRST_EN = 1 */
|
||||
outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17);
|
||||
}
|
||||
|
||||
void activate_spd_rom(const struct mem_controller *ctrl)
|
||||
{
|
||||
#define SMBUS_HUB 0x18
|
||||
int ret,i;
|
||||
u8 device = ctrl->spd_switch_addr;
|
||||
|
||||
printk(BIOS_DEBUG, "switch i2c to : %02x for node %02x\n", device, ctrl->node_id);
|
||||
|
||||
/* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/
|
||||
i = 2;
|
||||
do {
|
||||
ret = smbus_write_byte(SMBUS_HUB, 0x01, (1<<(device & 0x7)));
|
||||
} while ((ret != 0) && (i-->0));
|
||||
smbus_write_byte(SMBUS_HUB, 0x03, 0);
|
||||
}
|
||||
|
||||
int spd_read_byte(u32 device, u32 address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
static const u8 spd_addr[] = {
|
||||
/* first node */
|
||||
RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 1
|
||||
/* second node */
|
||||
RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 2
|
||||
/* third node */
|
||||
RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
/* forth node */
|
||||
RC03, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 4
|
||||
RC04, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC05, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 6
|
||||
RC06, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC07, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 8
|
||||
RC08, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC09, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC10, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC11, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 12
|
||||
RC12, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC13, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC14, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC15, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 16
|
||||
RC16, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC17, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC18, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC19, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 20
|
||||
RC20, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC21, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC22, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC23, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 24
|
||||
RC24, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC25, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC26, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC27, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC28, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC29, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC30, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC31, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 32
|
||||
RC32, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC33, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC34, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC35, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC36, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC37, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC38, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC39, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC40, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC41, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC42, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC43, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC44, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC45, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC46, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC47, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 48
|
||||
RC48, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC49, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC50, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC51, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC52, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC53, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC54, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC55, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC56, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC57, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC58, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC59, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC60, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC61, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC62, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC63, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
};
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
struct sys_info *sysinfo = get_sysinfo();
|
||||
u32 bsp_apicid = 0, val;
|
||||
msr_t msr;
|
||||
|
||||
timestamp_init(timestamp_get());
|
||||
timestamp_add_now(TS_START_ROMSTAGE);
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
/* mov bsp to bus 0xff when > 8 nodes */
|
||||
set_bsp_node_CHtExtNodeCfgEn();
|
||||
enumerate_ht_chain();
|
||||
}
|
||||
|
||||
post_code(0x30);
|
||||
|
||||
if (bist == 0) {
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
|
||||
/* All cores run this but the BSP(node0,core0) is the only core that returns. */
|
||||
}
|
||||
|
||||
post_code(0x32);
|
||||
|
||||
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
/* Load MPB */
|
||||
val = cpuid_eax(1);
|
||||
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
|
||||
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
|
||||
printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
|
||||
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
|
||||
|
||||
/* Setup sysinfo defaults */
|
||||
set_sysinfo_in_ram(0);
|
||||
|
||||
update_microcode(val);
|
||||
|
||||
post_code(0x33);
|
||||
|
||||
cpuSetAMDMSR(0);
|
||||
post_code(0x34);
|
||||
|
||||
amd_ht_init(sysinfo);
|
||||
post_code(0x35);
|
||||
|
||||
/* Setup nodes PCI space and start core 0 AP init. */
|
||||
finalize_node_setup(sysinfo);
|
||||
|
||||
/* Setup any mainboard PCI settings etc. */
|
||||
setup_mb_resource_map();
|
||||
post_code(0x36);
|
||||
|
||||
/* wait for all the APs core0 started by finalize_node_setup. */
|
||||
/* FIXME: A bunch of cores are going to start output to serial at once.
|
||||
It would be nice to fixup prink spinlocks for ROM XIP mode.
|
||||
I think it could be done by putting the spinlock flag in the cache
|
||||
of the BSP located right after sysinfo.
|
||||
*/
|
||||
wait_all_core0_started();
|
||||
|
||||
#if CONFIG(LOGICAL_CPUS)
|
||||
/* Core0 on each node is configured. Now setup any additional cores. */
|
||||
printk(BIOS_DEBUG, "start_other_cores()\n");
|
||||
start_other_cores(bsp_apicid);
|
||||
post_code(0x37);
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
#endif
|
||||
|
||||
post_code(0x38);
|
||||
|
||||
#if CONFIG(SET_FIDVID)
|
||||
msr = rdmsr(MSR_COFVID_STS);
|
||||
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
|
||||
|
||||
/* FIXME: The sb fid change may survive the warm reset and only
|
||||
need to be done once.*/
|
||||
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
|
||||
|
||||
post_code(0x39);
|
||||
|
||||
if (!warm_reset_detect(0)) { /* BSP is node 0 */
|
||||
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
|
||||
} else {
|
||||
init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */
|
||||
}
|
||||
|
||||
post_code(0x3A);
|
||||
|
||||
/* show final fid and vid */
|
||||
msr = rdmsr(MSR_COFVID_STS);
|
||||
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
|
||||
#endif
|
||||
|
||||
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
|
||||
if (!warm_reset_detect(0)) {
|
||||
printk(BIOS_INFO, "...WARM RESET...\n\n\n");
|
||||
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
|
||||
die("After soft_reset_x - shouldn't see this message!!!\n");
|
||||
}
|
||||
|
||||
post_code(0x3B);
|
||||
|
||||
/* FIXME: Move this to chipset init.
|
||||
enable cf9 for hard reset */
|
||||
printk(BIOS_DEBUG, "enable_cf9_x()\n");
|
||||
enable_cf9_x(sysinfo->sbbusn, sysinfo->sbdn);
|
||||
post_code(0x3C);
|
||||
|
||||
/* It's the time to set ctrl in sysinfo now; */
|
||||
printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
|
||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
||||
post_code(0x3D);
|
||||
|
||||
printk(BIOS_DEBUG, "enable_smbus()\n");
|
||||
enable_smbus();
|
||||
post_code(0x3E);
|
||||
|
||||
memreset_setup();
|
||||
post_code(0x40);
|
||||
|
||||
raminit_amdmct(sysinfo);
|
||||
|
||||
cbmem_initialize_empty();
|
||||
post_code(0x41);
|
||||
|
||||
amdmct_cbmem_store_info(sysinfo);
|
||||
|
||||
post_code(0x42);
|
||||
}
|
||||
|
||||
/**
|
||||
* BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
|
||||
* Description:
|
||||
* This routine is called every time a non-coherent chain is processed.
|
||||
* BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
|
||||
* swap list. The first part of the list controls the BUID assignment and the
|
||||
* second part of the list provides the device to device linking. Device orientation
|
||||
* can be detected automatically, or explicitly. See documentation for more details.
|
||||
*
|
||||
* Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
|
||||
* based on each device's unit count.
|
||||
*
|
||||
* Parameters:
|
||||
* @param[in] node = The node on which this chain is located
|
||||
* @param[in] link = The link on the host for this chain
|
||||
* @param[out] List = supply a pointer to a list
|
||||
*/
|
||||
BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
|
||||
{
|
||||
static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
|
||||
/* If the BUID was adjusted in early_ht we need to do the manual override */
|
||||
if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
|
||||
printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
|
||||
if ((node == 0) && (link == 0)) { /* BSP SB link */
|
||||
*List = swaplist;
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -1,79 +0,0 @@
|
||||
//
|
||||
// This file is part of the coreboot project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock ("SSDT2.aml", "SSDT", 1, OEM_ID, ACPI_TABLE_CREATOR, 100925440)
|
||||
{
|
||||
Scope (_SB)
|
||||
{
|
||||
External (DADD, MethodObj)
|
||||
External (GHCE, MethodObj)
|
||||
External (GHCN, MethodObj)
|
||||
External (GHCL, MethodObj)
|
||||
External (GHCD, MethodObj)
|
||||
External (GNUS, MethodObj)
|
||||
External (GIOR, MethodObj)
|
||||
External (GMEM, MethodObj)
|
||||
External (GWBN, MethodObj)
|
||||
External (GBUS, MethodObj)
|
||||
|
||||
External (PICF)
|
||||
|
||||
External (\_SB.PCI0.LNKA, DeviceObj)
|
||||
External (\_SB.PCI0.LNKB, DeviceObj)
|
||||
External (\_SB.PCI0.LNKC, DeviceObj)
|
||||
External (\_SB.PCI0.LNKD, DeviceObj)
|
||||
|
||||
Device (PCIX)
|
||||
{
|
||||
|
||||
// BUS ? Second HT Chain
|
||||
Name (HCIN, 0xcc) // HC2 0x01
|
||||
|
||||
Name (_UID, 0xdd) // HC 0x03
|
||||
|
||||
Name (_HID, "PNP0A03")
|
||||
|
||||
Method (_ADR, 0, NotSerialized) //Fake bus should be 0
|
||||
{
|
||||
Return (DADD(GHCN(HCIN), 0x00000000))
|
||||
}
|
||||
|
||||
Method (_BBN, 0, NotSerialized)
|
||||
{
|
||||
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
|
||||
}
|
||||
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (\_SB.GHCE(HCIN))
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate () { })
|
||||
Store( GHCN(HCIN), Local4)
|
||||
Store( GHCL(HCIN), Local5)
|
||||
|
||||
Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
|
||||
Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
|
||||
Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
|
||||
Return (Local3)
|
||||
}
|
||||
|
||||
#include "acpi/pci2_hc.asl"
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
@@ -1,79 +0,0 @@
|
||||
//
|
||||
// This file is part of the coreboot project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock ("SSDT3.aml", "SSDT", 1, OEM_ID, ACPI_TABLE_CREATOR, 100925440)
|
||||
{
|
||||
Scope (_SB)
|
||||
{
|
||||
External (DADD, MethodObj)
|
||||
External (GHCE, MethodObj)
|
||||
External (GHCN, MethodObj)
|
||||
External (GHCL, MethodObj)
|
||||
External (GHCD, MethodObj)
|
||||
External (GNUS, MethodObj)
|
||||
External (GIOR, MethodObj)
|
||||
External (GMEM, MethodObj)
|
||||
External (GWBN, MethodObj)
|
||||
External (GBUS, MethodObj)
|
||||
|
||||
External (PICF)
|
||||
|
||||
External (\_SB.PCI0.LNKA, DeviceObj)
|
||||
External (\_SB.PCI0.LNKB, DeviceObj)
|
||||
External (\_SB.PCI0.LNKC, DeviceObj)
|
||||
External (\_SB.PCI0.LNKD, DeviceObj)
|
||||
|
||||
Device (PCIX)
|
||||
{
|
||||
|
||||
// BUS ? Second HT Chain
|
||||
Name (HCIN, 0xcc) // HC2 0x01
|
||||
|
||||
Name (_UID, 0xdd) // HC 0x03
|
||||
|
||||
Name (_HID, "PNP0A03")
|
||||
|
||||
Method (_ADR, 0, NotSerialized) //Fake bus should be 0
|
||||
{
|
||||
Return (DADD(GHCN(HCIN), 0x00000000))
|
||||
}
|
||||
|
||||
Method (_BBN, 0, NotSerialized)
|
||||
{
|
||||
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
|
||||
}
|
||||
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (\_SB.GHCE(HCIN))
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate () { })
|
||||
Store( GHCN(HCIN), Local4)
|
||||
Store( GHCL(HCIN), Local5)
|
||||
|
||||
Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
|
||||
Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
|
||||
Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
|
||||
Return (Local3)
|
||||
}
|
||||
|
||||
#include "acpi/pci3_hc.asl"
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
@@ -1,79 +0,0 @@
|
||||
//
|
||||
// This file is part of the coreboot project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock ("SSDT4.aml", "SSDT", 1, OEM_ID, ACPI_TABLE_CREATOR, 100925440)
|
||||
{
|
||||
Scope (_SB)
|
||||
{
|
||||
External (DADD, MethodObj)
|
||||
External (GHCE, MethodObj)
|
||||
External (GHCN, MethodObj)
|
||||
External (GHCL, MethodObj)
|
||||
External (GHCD, MethodObj)
|
||||
External (GNUS, MethodObj)
|
||||
External (GIOR, MethodObj)
|
||||
External (GMEM, MethodObj)
|
||||
External (GWBN, MethodObj)
|
||||
External (GBUS, MethodObj)
|
||||
|
||||
External (PICF)
|
||||
|
||||
External (\_SB.PCI0.LNKA, DeviceObj)
|
||||
External (\_SB.PCI0.LNKB, DeviceObj)
|
||||
External (\_SB.PCI0.LNKC, DeviceObj)
|
||||
External (\_SB.PCI0.LNKD, DeviceObj)
|
||||
|
||||
Device (PCIX)
|
||||
{
|
||||
|
||||
// BUS ? Second HT Chain
|
||||
Name (HCIN, 0xcc) // HC2 0x01
|
||||
|
||||
Name (_UID, 0xdd) // HC 0x03
|
||||
|
||||
Name (_HID, "PNP0A03")
|
||||
|
||||
Method (_ADR, 0, NotSerialized) //Fake bus should be 0
|
||||
{
|
||||
Return (DADD(GHCN(HCIN), 0x00000000))
|
||||
}
|
||||
|
||||
Method (_BBN, 0, NotSerialized)
|
||||
{
|
||||
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
|
||||
}
|
||||
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (\_SB.GHCE(HCIN))
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate () { })
|
||||
Store( GHCN(HCIN), Local4)
|
||||
Store( GHCL(HCIN), Local5)
|
||||
|
||||
Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
|
||||
Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
|
||||
Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
|
||||
Return (Local3)
|
||||
}
|
||||
|
||||
#include "acpi/pci4_hc.asl"
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
@@ -1,80 +0,0 @@
|
||||
//
|
||||
// This file is part of the coreboot project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock ("SSDT5.aml", "SSDT", 1, OEM_ID, ACPI_TABLE_CREATOR, 100925440)
|
||||
{
|
||||
Scope (_SB)
|
||||
{
|
||||
External (DADD, MethodObj)
|
||||
External (GHCE, MethodObj)
|
||||
External (GHCN, MethodObj)
|
||||
External (GHCL, MethodObj)
|
||||
External (GHCD, MethodObj)
|
||||
External (GNUS, MethodObj)
|
||||
External (GIOR, MethodObj)
|
||||
External (GMEM, MethodObj)
|
||||
External (GWBN, MethodObj)
|
||||
External (GBUS, MethodObj)
|
||||
|
||||
External (PICF)
|
||||
|
||||
External (\_SB.PCI0.LNKA, DeviceObj)
|
||||
External (\_SB.PCI0.LNKB, DeviceObj)
|
||||
External (\_SB.PCI0.LNKC, DeviceObj)
|
||||
External (\_SB.PCI0.LNKD, DeviceObj)
|
||||
|
||||
Device (PCIX)
|
||||
{
|
||||
|
||||
// BUS ? Second HT Chain
|
||||
Name (HCIN, 0xcc) // HC2 0x01
|
||||
|
||||
Name (_UID, 0xdd) // HC 0x03
|
||||
|
||||
Name (_HID, "PNP0A03")
|
||||
|
||||
Method (_ADR, 0, NotSerialized) //Fake bus should be 0
|
||||
{
|
||||
Return (DADD(GHCN(HCIN), 0x00000000))
|
||||
}
|
||||
|
||||
Method (_BBN, 0, NotSerialized)
|
||||
{
|
||||
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
|
||||
}
|
||||
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (\_SB.GHCE(HCIN))
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate () { })
|
||||
Store( GHCN(HCIN), Local4)
|
||||
Store( GHCL(HCIN), Local5)
|
||||
|
||||
Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
|
||||
Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
|
||||
Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
|
||||
Return (Local3)
|
||||
}
|
||||
|
||||
#include "acpi/pci5_hc.asl"
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
@@ -1,63 +0,0 @@
|
||||
if BOARD_AMD_TILAPIA_FAM10
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS
|
||||
def_bool y
|
||||
select CPU_AMD_SOCKET_AM3
|
||||
select DIMM_DDR3
|
||||
select DIMM_REGISTERED
|
||||
select NORTHBRIDGE_AMD_AMDFAM10
|
||||
select SOUTHBRIDGE_AMD_RS780
|
||||
select SOUTHBRIDGE_AMD_SB700
|
||||
select SUPERIO_ITE_IT8718F
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
select LIFT_BSP_APIC_ID
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_1024
|
||||
select ENABLE_APIC_EXT_ID
|
||||
select GFXUMA
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default amd/tilapia_fam10
|
||||
|
||||
config APIC_ID_OFFSET
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "Tilapia (Fam10)"
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 8
|
||||
|
||||
config MAX_PHYSICAL_CPUS
|
||||
int
|
||||
default 2
|
||||
|
||||
config HT_CHAIN_END_UNITID_BASE
|
||||
hex
|
||||
default 0x1
|
||||
|
||||
config HT_CHAIN_UNITID_BASE
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 11
|
||||
|
||||
config VGA_BIOS
|
||||
bool
|
||||
default n
|
||||
|
||||
config VGA_BIOS_ID
|
||||
string
|
||||
depends on VGA_BIOS
|
||||
default "1002,9615"
|
||||
|
||||
endif # BOARD_AMD_TILAPIA_FAM10
|
||||
@@ -1,2 +0,0 @@
|
||||
config BOARD_AMD_TILAPIA_FAM10
|
||||
bool "Tilapia (Fam10)"
|
||||
@@ -1,16 +0,0 @@
|
||||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
|
||||
romstage-y += resourcemap.c
|
||||
|
||||
ramstage-y += get_bus_conf.c
|
||||
@@ -1,80 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* This file defines the processor and performance state capability
|
||||
* for each core in the system. It is included into the DSDT for each
|
||||
* core. It assumes that each core of the system has the same performance
|
||||
* characteristics.
|
||||
*/
|
||||
/*
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001)
|
||||
{
|
||||
Scope (\_PR) {
|
||||
Device (CPU0) {
|
||||
Name (_HID, "ACPI0007")
|
||||
Name (_UID, 0)
|
||||
#include "cpstate.asl"
|
||||
}
|
||||
Device (CPU1) {
|
||||
Name (_HID, "ACPI0007")
|
||||
Name (_UID, 1)
|
||||
#include "cpstate.asl"
|
||||
}
|
||||
Device (CPU2) {
|
||||
Name (_HID, "ACPI0007")
|
||||
Name (_UID, 2)
|
||||
#include "cpstate.asl"
|
||||
}
|
||||
Device (CPU3) {
|
||||
Name (_HID, "ACPI0007")
|
||||
Name (_UID, 3)
|
||||
#include "cpstate.asl"
|
||||
}
|
||||
}
|
||||
*/
|
||||
/* P-state support: The maximum number of P-states supported by the */
|
||||
/* CPUs we'll use is 6. */
|
||||
/* Get from AMI BIOS. */
|
||||
Name(_PSS, Package(){
|
||||
Package ()
|
||||
{
|
||||
0x00000AF0,
|
||||
0x0000BF81,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000000,
|
||||
0x00000000
|
||||
},
|
||||
|
||||
Package ()
|
||||
{
|
||||
0x00000578,
|
||||
0x000076F2,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000001,
|
||||
0x00000001
|
||||
}
|
||||
})
|
||||
|
||||
Name(_PCT, Package(){
|
||||
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
|
||||
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
|
||||
})
|
||||
|
||||
Method(_PPC, 0){
|
||||
Return(0)
|
||||
}
|
||||
@@ -1,240 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
Scope (_SB) {
|
||||
Device(PCI0) {
|
||||
Device(IDEC) {
|
||||
Name(_ADR, 0x00140001)
|
||||
#include "ide.asl"
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
/* Some timing tables */
|
||||
Name(UDTT, Package(){ /* Udma timing table */
|
||||
120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
|
||||
})
|
||||
|
||||
Name(MDTT, Package(){ /* MWDma timing table */
|
||||
480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
|
||||
})
|
||||
|
||||
Name(POTT, Package(){ /* Pio timing table */
|
||||
600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
|
||||
})
|
||||
|
||||
/* Some timing register value tables */
|
||||
Name(MDRT, Package(){ /* MWDma timing register table */
|
||||
0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
|
||||
})
|
||||
|
||||
Name(PORT, Package(){
|
||||
0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
|
||||
})
|
||||
|
||||
OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
|
||||
Field(ICRG, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
PPTS, 8, /* Primary PIO Slave Timing */
|
||||
PPTM, 8, /* Primary PIO Master Timing */
|
||||
OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
|
||||
PMTM, 8, /* Primary MWDMA Master Timing */
|
||||
OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
|
||||
OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
|
||||
PPSM, 4, /* Primary PIO slave Mode */
|
||||
OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
|
||||
OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
|
||||
PDSM, 4, /* Primary UltraDMA Mode */
|
||||
}
|
||||
|
||||
Method(GTTM, 1) /* get total time*/
|
||||
{
|
||||
Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
|
||||
Increment(Local0)
|
||||
Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
|
||||
Increment(Local1)
|
||||
Return(Multiply(30, Add(Local0, Local1)))
|
||||
}
|
||||
|
||||
Device(PRID)
|
||||
{
|
||||
Name (_ADR, Zero)
|
||||
Method(_GTM, 0)
|
||||
{
|
||||
NAME(OTBF, Buffer(20) { /* out buffer */
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
|
||||
CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
|
||||
CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
|
||||
CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
|
||||
CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
|
||||
|
||||
/* Just return if the channel is disabled */
|
||||
If(And(PPCR, 0x01)) { /* primary PIO control */
|
||||
Return(OTBF)
|
||||
}
|
||||
|
||||
/* Always tell them independent timing available and IOChannelReady used on both drives */
|
||||
Or(BFFG, 0x1A, BFFG)
|
||||
|
||||
Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
|
||||
Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
|
||||
|
||||
If(And(PDCR, 0x01)) { /* It's under UDMA mode */
|
||||
Or(BFFG, 0x01, BFFG)
|
||||
Store(DerefOf(Index(UDTT, PDMM)), DSD0)
|
||||
}
|
||||
Else {
|
||||
Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
|
||||
}
|
||||
|
||||
If(And(PDCR, 0x02)) { /* It's under UDMA mode */
|
||||
Or(BFFG, 0x04, BFFG)
|
||||
Store(DerefOf(Index(UDTT, PDSM)), DSD1)
|
||||
}
|
||||
Else {
|
||||
Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
|
||||
}
|
||||
|
||||
Return(OTBF) /* out buffer */
|
||||
} /* End Method(_GTM) */
|
||||
|
||||
Method(_STM, 3, NotSerialized)
|
||||
{
|
||||
NAME(INBF, Buffer(20) { /* in buffer */
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
|
||||
CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
|
||||
CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
|
||||
CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
|
||||
CreateDwordField(INBF, 16, BFFG) /*buffer flag */
|
||||
|
||||
Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
|
||||
Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
|
||||
Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
|
||||
|
||||
Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
|
||||
Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
|
||||
|
||||
If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
|
||||
Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 7, PDMM,)
|
||||
Or(PDCR, 0x01, PDCR)
|
||||
}
|
||||
Else {
|
||||
If(LNotEqual(DSD0, 0xFFFFFFFF)) {
|
||||
Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
|
||||
Store(DerefOf(Index(MDRT, Local0)), PMTM)
|
||||
}
|
||||
}
|
||||
|
||||
If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
|
||||
Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 7, PDSM,)
|
||||
Or(PDCR, 0x02, PDCR)
|
||||
}
|
||||
Else {
|
||||
If(LNotEqual(DSD1, 0xFFFFFFFF)) {
|
||||
Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
|
||||
Store(DerefOf(Index(MDRT, Local0)), PMTS)
|
||||
}
|
||||
}
|
||||
/* Return(INBF) */
|
||||
} /*End Method(_STM) */
|
||||
Device(MST)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_GTF) {
|
||||
Name(CMBF, Buffer(21) {
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
|
||||
})
|
||||
CreateByteField(CMBF, 1, POMD)
|
||||
CreateByteField(CMBF, 8, DMMD)
|
||||
CreateByteField(CMBF, 5, CMDA)
|
||||
CreateByteField(CMBF, 12, CMDB)
|
||||
CreateByteField(CMBF, 19, CMDC)
|
||||
|
||||
Store(0xA0, CMDA)
|
||||
Store(0xA0, CMDB)
|
||||
Store(0xA0, CMDC)
|
||||
|
||||
Or(PPMM, 0x08, POMD)
|
||||
|
||||
If(And(PDCR, 0x01)) {
|
||||
Or(PDMM, 0x40, DMMD)
|
||||
}
|
||||
Else {
|
||||
Store(Match
|
||||
(MDTT, MLE, GTTM(PMTM),
|
||||
MTR, 0, 0), Local0)
|
||||
If(LLess(Local0, 3)) {
|
||||
Or(0x20, Local0, DMMD)
|
||||
}
|
||||
}
|
||||
Return(CMBF)
|
||||
}
|
||||
} /* End Device(MST) */
|
||||
|
||||
Device(SLAV)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_GTF) {
|
||||
Name(CMBF, Buffer(21) {
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
|
||||
})
|
||||
CreateByteField(CMBF, 1, POMD)
|
||||
CreateByteField(CMBF, 8, DMMD)
|
||||
CreateByteField(CMBF, 5, CMDA)
|
||||
CreateByteField(CMBF, 12, CMDB)
|
||||
CreateByteField(CMBF, 19, CMDC)
|
||||
|
||||
Store(0xB0, CMDA)
|
||||
Store(0xB0, CMDB)
|
||||
Store(0xB0, CMDC)
|
||||
|
||||
Or(PPSM, 0x08, POMD)
|
||||
|
||||
If(And(PDCR, 0x02)) {
|
||||
Or(PDSM, 0x40, DMMD)
|
||||
}
|
||||
Else {
|
||||
Store(Match
|
||||
(MDTT, MLE, GTTM(PMTS),
|
||||
MTR, 0, 0), Local0)
|
||||
If(LLess(Local0, 3)) {
|
||||
Or(0x20, Local0, DMMD)
|
||||
}
|
||||
}
|
||||
Return(CMBF)
|
||||
}
|
||||
} /* End Device(SLAV) */
|
||||
}
|
||||
@@ -1,297 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
|
||||
)
|
||||
{
|
||||
#include "routing.asl"
|
||||
}
|
||||
*/
|
||||
|
||||
/* Routing is in System Bus scope */
|
||||
Scope(\_SB) {
|
||||
Name(PR0, Package(){
|
||||
/* NB devices */
|
||||
/* Bus 0, Dev 0 - RS780 Host Controller */
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
|
||||
Package(){0x0002FFFF, 0, INTC, 0 },
|
||||
Package(){0x0002FFFF, 1, INTD, 0 },
|
||||
Package(){0x0002FFFF, 2, INTA, 0 },
|
||||
Package(){0x0002FFFF, 3, INTB, 0 },
|
||||
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
|
||||
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||
Package(){0x0004FFFF, 0, INTA, 0 },
|
||||
Package(){0x0004FFFF, 1, INTB, 0 },
|
||||
Package(){0x0004FFFF, 2, INTC, 0 },
|
||||
Package(){0x0004FFFF, 3, INTD, 0 },
|
||||
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||
/* Package(){0x0005FFFF, 0, INTB, 0 }, */
|
||||
/* Package(){0x0005FFFF, 1, INTC, 0 }, */
|
||||
/* Package(){0x0005FFFF, 2, INTD, 0 }, */
|
||||
/* Package(){0x0005FFFF, 3, INTA, 0 }, */
|
||||
/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
|
||||
Package(){0x0006FFFF, 0, INTC, 0 },
|
||||
Package(){0x0006FFFF, 1, INTD, 0 },
|
||||
Package(){0x0006FFFF, 2, INTA, 0 },
|
||||
Package(){0x0006FFFF, 3, INTB, 0 },
|
||||
/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
|
||||
Package(){0x0007FFFF, 0, INTD, 0 },
|
||||
Package(){0x0007FFFF, 1, INTA, 0 },
|
||||
Package(){0x0007FFFF, 2, INTB, 0 },
|
||||
Package(){0x0007FFFF, 3, INTC, 0 },
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
/* SB devices */
|
||||
/* Bus 0, Dev 17 - SATA controller #2 */
|
||||
/* Bus 0, Dev 18 - SATA controller #1 */
|
||||
Package(){0x0011FFFF, 1, INTA, 0 },
|
||||
|
||||
/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
|
||||
Package(){0x0012FFFF, 0, INTA, 0 },
|
||||
Package(){0x0012FFFF, 1, INTB, 0 },
|
||||
Package(){0x0013FFFF, 0, INTA, 0 },
|
||||
Package(){0x0013FFFF, 1, INTB, 0 },
|
||||
Package(){0x0014FFFF, 2, INTA, 0 },
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */
|
||||
Package(){0x0014FFFF, 0, INTA, 0 },
|
||||
Package(){0x0014FFFF, 1, INTB, 0 },
|
||||
Package(){0x0014FFFF, 2, INTC, 0 },
|
||||
Package(){0x0014FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APR0, Package(){
|
||||
/* NB devices in APIC mode */
|
||||
/* Bus 0, Dev 0 - RS780 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
/* Package(){0x0001FFFF, 0, 0, 18 }, */
|
||||
/* Package(){0x0001FFFF, 1, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
|
||||
Package(){0x0002FFFF, 0, 0, 18 },
|
||||
/* Package(){0x0002FFFF, 1, 0, 19 }, */
|
||||
/* Package(){0x0002FFFF, 2, 0, 16 }, */
|
||||
/* Package(){0x0002FFFF, 3, 0, 17 }, */
|
||||
|
||||
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
|
||||
Package(){0x0003FFFF, 0, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||
Package(){0x0004FFFF, 0, 0, 16 },
|
||||
/* Package(){0x0004FFFF, 1, 0, 17 }, */
|
||||
/* Package(){0x0004FFFF, 2, 0, 18 }, */
|
||||
/* Package(){0x0004FFFF, 3, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||
/* Package(){0x0005FFFF, 0, 0, 17 }, */
|
||||
/* Package(){0x0005FFFF, 1, 0, 18 }, */
|
||||
/* Package(){0x0005FFFF, 2, 0, 19 }, */
|
||||
/* Package(){0x0005FFFF, 3, 0, 16 }, */
|
||||
|
||||
/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
|
||||
/* Package(){0x0006FFFF, 0, 0, 18 }, */
|
||||
/* Package(){0x0006FFFF, 1, 0, 19 }, */
|
||||
/* Package(){0x0006FFFF, 2, 0, 16 }, */
|
||||
/* Package(){0x0006FFFF, 3, 0, 17 }, */
|
||||
|
||||
/* Bus 0, Dev 7 - PCIe Bridge for network card */
|
||||
/* Package(){0x0007FFFF, 0, 0, 19 }, */
|
||||
/* Package(){0x0007FFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x0007FFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x0007FFFF, 3, 0, 18 }, */
|
||||
|
||||
/* Bus 0, Dev 9 - PCIe Bridge for network card */
|
||||
Package(){0x0009FFFF, 0, 0, 17 },
|
||||
/* Package(){0x0009FFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x0009FFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x0009FFFF, 3, 0, 18 }, */
|
||||
/* Bus 0, Dev A - PCIe Bridge for network card */
|
||||
Package(){0x000AFFFF, 0, 0, 18 },
|
||||
/* Package(){0x000AFFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x000AFFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x000AFFFF, 3, 0, 18 }, */
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
/* SB devices in APIC mode */
|
||||
/* Bus 0, Dev 17 - SATA controller #2 */
|
||||
/* Bus 0, Dev 18 - SATA controller #1 */
|
||||
Package(){0x0011FFFF, 0, 0, 22 },
|
||||
|
||||
/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
|
||||
Package(){0x0012FFFF, 0, 0, 16 },
|
||||
Package(){0x0012FFFF, 1, 0, 17 },
|
||||
Package(){0x0013FFFF, 0, 0, 18 },
|
||||
Package(){0x0013FFFF, 1, 0, 19 },
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
/* Package(){0x00130004, 2, 0, 18 }, */
|
||||
/* Package(){0x00130005, 3, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
Package(){0x0014FFFF, 1, 0, 17 },
|
||||
Package(){0x0014FFFF, 2, 0, 18 },
|
||||
Package(){0x0014FFFF, 3, 0, 19 },
|
||||
/* Package(){0x00140004, 2, 0, 18 }, */
|
||||
/* Package(){0x00140004, 3, 0, 19 }, */
|
||||
/* Package(){0x00140005, 1, 0, 17 }, */
|
||||
/* Package(){0x00140006, 1, 0, 17 }, */
|
||||
})
|
||||
|
||||
Name(PR1, Package(){
|
||||
/* Internal graphics - RS780 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, INTA, 0 },
|
||||
Package(){0x0005FFFF, 1, INTB, 0 },
|
||||
Package(){0x0005FFFF, 2, INTC, 0 },
|
||||
Package(){0x0005FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APR1, Package(){
|
||||
/* Internal graphics - RS780 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, 0, 18 },
|
||||
Package(){0x0005FFFF, 1, 0, 19 },
|
||||
/* Package(){0x0005FFFF, 2, 0, 20 }, */
|
||||
/* Package(){0x0005FFFF, 3, 0, 17 }, */
|
||||
})
|
||||
|
||||
Name(PS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
|
||||
Name(APS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, 0, 16 },
|
||||
Package(){0x0000FFFF, 1, 0, 17 },
|
||||
Package(){0x0000FFFF, 2, 0, 18 },
|
||||
Package(){0x0000FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PS5, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 5 */
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
|
||||
Name(APS5, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 5 */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
|
||||
Name(PS6, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 6 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
|
||||
Name(APS6, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 6 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS7, Package(){
|
||||
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
|
||||
Name(APS7, Package(){
|
||||
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
|
||||
Package(){0x0000FFFF, 0, 0, 19 },
|
||||
Package(){0x0000FFFF, 1, 0, 16 },
|
||||
Package(){0x0000FFFF, 2, 0, 17 },
|
||||
Package(){0x0000FFFF, 3, 0, 18 },
|
||||
})
|
||||
Name(PS9, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 9 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
|
||||
Name(APS9, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 9 */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
Name(PSa, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
|
||||
Name(APSa, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PCIB, Package(){
|
||||
/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
|
||||
Package(){0x0005FFFF, 0, 0, 0x14 },
|
||||
Package(){0x0005FFFF, 1, 0, 0x15 },
|
||||
Package(){0x0005FFFF, 2, 0, 0x16 },
|
||||
Package(){0x0005FFFF, 3, 0, 0x17 },
|
||||
Package(){0x0006FFFF, 0, 0, 0x15 },
|
||||
Package(){0x0006FFFF, 1, 0, 0x16 },
|
||||
Package(){0x0006FFFF, 2, 0, 0x17 },
|
||||
Package(){0x0006FFFF, 3, 0, 0x14 },
|
||||
Package(){0x0007FFFF, 0, 0, 0x16 },
|
||||
Package(){0x0007FFFF, 1, 0, 0x17 },
|
||||
Package(){0x0007FFFF, 2, 0, 0x14 },
|
||||
Package(){0x0007FFFF, 3, 0, 0x15 },
|
||||
})
|
||||
}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user