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Route device IRQ through PCI bridge instead in mptable.

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Don't enable pin0 for ioapic of io-4.

1. apic error in kernel for MB with mcp55+io55
2. some pcie-cards could have pci bridge there, so need to put entries
   for device under them in mptable.

Signed-off-by: Yinghai Lu <yinghailu@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Yinghai Lu
2008-02-20 17:41:38 +00:00
committed by Stefan Reinauer
parent 8eff1e3d04
commit f327d9f954
7 changed files with 177 additions and 144 deletions
Download Patch File Download Diff File Expand all files Collapse all files

83
src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
View File

@@ -35,7 +35,7 @@
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
struct mb_sysconf_t mb_sysconf;
unsigned pci1234x[] =
unsigned pci1234x[] =
{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
0x0000ff0,
@@ -47,7 +47,7 @@ unsigned pci1234x[] =
// 0x0000ff0,
// 0x0000ff0
};
unsigned hcdnx[] =
unsigned hcdnx[] =
{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
0x20202020,
0x20202020,
@@ -98,18 +98,19 @@ void get_bus_conf(void)
device_t dev;
int i, j;
if(get_bus_conf_done==1) return; //do it only once
if (get_bus_conf_done)
return; //do it only once
get_bus_conf_done = 1;
sysconf.mb = &mb_sysconf;
m = sysconf.mb;
memset(m, 0, sizeof(struct mb_sysconf_t));
sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
for(i=0;i<sysconf.hc_possible_num; i++) {
for (i = 0; i < sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
}
@@ -121,77 +122,41 @@ void get_bus_conf(void)
m->sbdnb = (sysconf.hcdn[1] & 0xff); // first byte of second chain
m->bus_type[0] = 1; //pci
m->bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
/* MCP55 */
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0));
if (dev) {
m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
}
m->bus_mcp55 = (sysconf.pci1234[0] >> 16) & 0xff;
for(i=2; i<8;i++) {
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
if (dev) {
m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
}
}
for (i = 0; i < sysconf.hc_possible_num; i++) {
unsigned busn_min, busn_max;
if(m->bus_mcp55[2]) {
for(i=0;i<2; i++) {
dev = dev_find_slot(m->bus_mcp55[2], PCI_DEVFN(0, i));
if(dev) {
m->bus_pcix[0] = m->bus_mcp55[2];
m->bus_pcix[i+1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
}
}
for(i=0; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue;
if (!(sysconf.pci1234[i] & 0x1))
continue;
unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
unsigned busn_max = (sysconf.pci1234[i] >> 24) & 0xff;
for (j = busn; j <= busn_max; j++)
busn_min = (sysconf.pci1234[i] >> 16) & 0xff;
busn_max = (sysconf.pci1234[i] >> 24) & 0xff;
for (j = busn_min; j <= busn_max; j++)
m->bus_type[j] = 1;
if(m->bus_isa <= busn_max)
if(m->bus_isa <= busn_max)
m->bus_isa = busn_max + 1;
printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn_min, busn_max, m->bus_isa);
}
/* MCP55b */
for(i=1; i< sysconf.hc_possible_num; i++) {
if (!(sysconf.pci1234[i] & 0x0f) ) continue;
for (i = 1; i < sysconf.hc_possible_num; i++) {
if (!(sysconf.pci1234[i] & 0x0f))
continue;
// check hcid type here
sysconf.hcid[i] = get_hcid(i);
if (!sysconf.hcid[i]) continue; //unknown co processor
if (!sysconf.hcid[i])
continue; //unknown co processor
m->bus_mcp55b[0] = (sysconf.pci1234[1]>>16) & 0xff;
m->bus_mcp55b[1] = m->bus_mcp55b[0]+1; //fake pci
for(i=2; i<8;i++) {
dev = dev_find_slot(m->bus_mcp55b[0], PCI_DEVFN(m->sbdnb + 0x0a + i - 2 , 0));
if (dev) {
m->bus_mcp55b[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55b[0], m->sbdnb + 0x0a + i - 2 );
}
}
m->bus_mcp55b = (sysconf.pci1234[1]>>16) & 0xff;
}
/*I/O APICs: APIC ID Version State Address*/
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(2);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
#endif
m->apicid_mcp55 = apicid_base+0;
m->apicid_mcp55b = apicid_base+1;

18
src/mainboard/nvidia/l1_2pvv/irq_tables.c
View File

@@ -78,15 +78,15 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq = (void *)(addr);
v = (uint8_t *)(addr);
pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION;
pirq->rtr_bus = m->bus_mcp55[0];
pirq->rtr_bus = m->bus_mcp55;
pirq->rtr_devfn = ((sbdn+6)<<3)|0;
pirq->exclusive_irqs = 0;
pirq->rtr_vendor = 0x10de;
pirq->rtr_device = 0x0370;
@@ -97,10 +97,10 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq_info = (void *) ( &pirq->checksum + 1);
slot_num = 0;
//pci bridge
write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
write_pirq_info(pirq_info, m->bus_mcp55, ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
for(i=1; i< sysconf.hc_possible_num; i++) {
for (i = 1; i < sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue;
unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
unsigned devn = sysconf.hcdn[i] & 0xff;
@@ -109,10 +109,10 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq_info++; slot_num++;
}
pirq->size = 32 + 16 * slot_num;
pirq->size = 32 + 16 * slot_num;
for (i = 0; i < pirq->size; i++)
sum += v[i];
sum += v[i];
sum = pirq->checksum - sum;

5
src/mainboard/nvidia/l1_2pvv/mb_sysconf.h
View File

@@ -24,12 +24,11 @@
struct mb_sysconf_t {
unsigned char bus_isa;
unsigned char bus_mcp55[8]; //1
unsigned char bus_mcp55b[8];//a
unsigned char bus_mcp55;
unsigned char bus_mcp55b;
unsigned apicid_mcp55;
unsigned apicid_mcp55b;
unsigned bus_type[256];
unsigned char bus_pcix[3]; // under bus_mcp55_2
unsigned sbdnb;

122
src/mainboard/nvidia/l1_2pvv/mptable.c
View File

@@ -39,6 +39,7 @@ void *smp_write_config_table(void *v)
unsigned sbdn;
int i,j;
unsigned char apicpin[4];
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc));
@@ -65,8 +66,8 @@ void *smp_write_config_table(void *v)
/*Bus: Bus ID Type*/
/* define bus and isa numbers */
for(j= 0; j < 256 ; j++) {
if(m->bus_type[j])
for (j = 0; j < 256 ; j++) {
if (m->bus_type[j])
smp_write_bus(mc, j, "PCI ");
}
smp_write_bus(mc, m->bus_isa, "ISA ");
@@ -77,38 +78,43 @@ void *smp_write_config_table(void *v)
struct resource *res;
uint32_t dword;
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn+ 0x1,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
if (res)
smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
}
/* Initialize interrupt mapping*/
dword = pci_read_config32(dev, 0x74);
dword &= ~(1<<15);
dword |= 1<<2;
pci_write_config32(dev, 0x74, dword);
dword = 0x43c6c643;
pci_write_config32(dev, 0x7c, dword);
pci_write_config32(dev, 0x7c, dword);
dword = 0x81001a00;
pci_write_config32(dev, 0x80, dword);
dword = 0xd00012d2;
dword = 0xd00012d2;
pci_write_config32(dev, 0x84, dword);
}
if(m->bus_mcp55b[0]) {
dev = dev_find_slot(m->bus_mcp55b[0], PCI_DEVFN(m->sbdnb + 0x1,0));
if (m->bus_mcp55b) {
dev = dev_find_slot(m->bus_mcp55b, PCI_DEVFN(m->sbdnb + 0x1,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
if (res)
smp_write_ioapic(mc, m->apicid_mcp55b, 0x11, res->base);
}
dword = 0x43c60000;
pci_write_config32(dev, 0x7c, dword);
pci_write_config32(dev, 0x7c, dword);
dword = 0x81000000;
pci_write_config32(dev, 0x80, dword);
dword = 0xd00002d0;
dword = 0xd00002d0;
pci_write_config32(dev, 0x84, dword);
}
@@ -116,8 +122,8 @@ void *smp_write_config_table(void *v)
}
}
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_mcp55, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x2);
@@ -131,63 +137,65 @@ void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_mcp55, 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_mcp55, 0xf);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa); // 10
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
for(j=7; j>=2; j--) {
if(!m->bus_mcp55[j]) continue;
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
}
//Slot PCIE
for (j = 2; j < 8; j++) {
device_t dev;
dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 0x0a + j - 2 , 0));
if (!dev || !dev->enabled)
continue;
for (i = 0; i < 4; i++)
apicpin[i] = 0x10 + (2+j+i+4-sbdn%4)%4;
smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55, apicpin);
}
for(j=0; j<2; j++)
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x06+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
}
//Slot PCI 32
{
device_t dev;
dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 6 , 0));
if (dev && dev->enabled) {
for (i = 0; i < 4; i++)
apicpin[i] = 0x10 + (2+i)%4;
smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55, apicpin);
}
}
if(m->bus_mcp55b[0]) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b[0], ((m->sbdnb+5)<<2)|0, m->apicid_mcp55b, 0x14); // 20
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b[0], ((m->sbdnb+5)<<2)|1, m->apicid_mcp55b, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b[0], ((m->sbdnb+5)<<2)|2, m->apicid_mcp55b, 0x15); // 21
if (m->bus_mcp55b) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+5)<<2)|0, m->apicid_mcp55b, 0x14); // 20
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+5)<<2)|1, m->apicid_mcp55b, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+5)<<2)|2, m->apicid_mcp55b, 0x15); // 21
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b[0], ((m->sbdnb+8)<<2)|0, m->apicid_mcp55b, 0x16); // 22
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b[0], ((m->sbdnb+9)<<2)|0, m->apicid_mcp55b, 0x15); // 21
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+8)<<2)|0, m->apicid_mcp55b, 0x16); // 22
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+9)<<2)|0, m->apicid_mcp55b, 0x15); // 21
for(j=7; j>=2; j--) {
if(!m->bus_mcp55b[j]) continue;
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b[j], (0x00<<2)|i, m->apicid_mcp55b, 0x10 + (2+j+i+4-m->sbdnb%4)%4);
//Slot PCIE
for (j = 2; j < 8; j++) {
device_t dev;
dev = dev_find_slot(m->bus_mcp55b, PCI_DEVFN(m->sbdnb + 0x0a + j - 2 , 0));
if (!dev || !dev->enabled)
continue;
for (i = 0; i < 4; i++) {
apicpin[i] = 0x10 + (2+j+i+4-m->sbdnb%4)%4;
}
smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55b, apicpin);
}
}
#if 1
if(m->bus_pcix[0]) {
for(i=0;i<2;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_pcix[2], (4<<2)|i, m->apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17
}
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_pcix[1], (4<<2)|i, m->apicid_mcp55, 0x10 + (2+i+4-sbdn%4)%4); // 18, 19, 16, 17
}
}
#endif
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);