mb/google/guybrush: Switch eSPI ALERT# to in-band

Using the push-pull alert was causing leakages when in S0i3. This is
because the EC drives ALERT#, so when the AP enters S0i3, the extra
current leaks into the SoC and ends up turning on the power regulators.
By using in-band ALERT#, the EC no longer drives this pin high, thus
fixing the leak. We could also have used an open drain alert, but the
rise time is less than ideal.

BUG=b:187122344, b:186135022
TEST=Measure S0i3 power on guybrush and validate it's no longer high.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6de771aeda8feca062652f0ea9eb57d31cb68562
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
This commit is contained in:
Raul E Rangel
2021-05-05 13:41:24 -06:00
committed by Felix Held
parent 8317e727ce
commit f33f857fbe

View File

@ -35,7 +35,7 @@ chip soc/amd/cezanne
.io_mode = ESPI_IO_MODE_QUAD,
.op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
.crc_check_enable = 1,
.alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
.alert_pin = ESPI_ALERT_PIN_IN_BAND,
.periph_ch_en = 1,
.vw_ch_en = 1,
.oob_ch_en = 0,