commonlib,console,nb,sb,security: Add SPDX licenses to Makefiles

To help identify the licenses of the various files contained in the
coreboot source, we've added SPDX headers to the top of all of the
.c and .h files. This extends that practice to Makefiles.

Any file in the coreboot project without a specific license is bound
to the license of the overall coreboot project, GPL Version 2.

This patch adds the GPL V2 license identifier to the top of all
makefiles in the commonlib, console, northbridge, security, and
southbridge directories that don't already have an SPDX license line
at the top.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I02804a10d0b0355e41271a035613d9f3dfb122f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>

src/commonlib/Makefile.inc

@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 subdirs-y += storage
 
 bootblock-y += mem_pool.c

src/console/Makefile.inc

@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 ramstage-y += vtxprintf.c printk.c vsprintf.c
 ramstage-y += init.c console.c
 ramstage-y += post.c

src/device/dram/Makefile.inc

@@ -1,3 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
 
 romstage-y += ddr_common.c
 ramstage-y += ddr_common.c spd.c

src/northbridge/intel/e7505/Makefile.inc

@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 ifeq ($(CONFIG_NORTHBRIDGE_INTEL_E7505),y)
 
 ramstage-y += northbridge.c

src/security/Makefile.inc

@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 subdirs-y += vboot
 subdirs-y += tpm
 subdirs-y += memory

src/security/intel/Makefile.inc

@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 subdirs-y += txt
 subdirs-y += stm
 subdirs-y += cbnt

src/security/intel/cbnt/Makefile.inc

@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 ifeq ($(CONFIG_INTEL_CBNT_SUPPORT),y)
 
 all-y += logging.c

src/security/intel/stm/Makefile.inc

@@ -1,3 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
 
 # put the stm where it can be found
 

src/security/intel/txt/Makefile.inc

@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 romstage-$(CONFIG_INTEL_TXT_LIB) += txtlib.c
 
 ifeq ($(CONFIG_INTEL_TXT),y)

src/security/memory/Makefile.inc

@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 romstage-$(CONFIG_PLATFORM_HAS_DRAM_CLEAR) += memory.c
 postcar-$(CONFIG_PLATFORM_HAS_DRAM_CLEAR) += memory.c
 ramstage-$(CONFIG_PLATFORM_HAS_DRAM_CLEAR) += memory.c

src/security/tpm/Makefile.inc

@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 subdirs-$(CONFIG_TPM_GOOGLE) += tss/vendor/cr50
 
 ## TSS

src/security/tpm/tss/vendor/cr50/Makefile.inc

@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 ramstage-y += cr50.c
 romstage-y += cr50.c
 postcar-y += cr50.c

src/southbridge/amd/common/Makefile.inc

@@ -1 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c

src/southbridge/intel/i82870/Makefile.inc

@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82870),y)
 
 ramstage-y += ioapic.c

src/southbridge/ricoh/rl5c476/Makefile.inc

@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 ifeq ($(CONFIG_SOUTHBRIDGE_RICOH_RL5C476),y)
 
 ramstage-y += rl5c476.c

src/southbridge/ti/pci1x2x/Makefile.inc

@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 ifeq ($(CONFIG_SOUTHBRIDGE_TI_PCI1X2X),y)
 
 ramstage-y += pci1x2x.c