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Add support for the Intel NM10 (a variant of ICH7) and ICH8 southbridges.

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Both are tested and appear to be working, however I'm not 100% clear
on if the NM10 has any other PCI IDs.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Corey Osgood
2010-08-17 08:33:44 +00:00
committed by Stefan Reinauer
parent e7b7ae23e6
commit f366ce05ef
5 changed files with 10 additions and 0 deletions
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2
util/inteltool/gpio.c
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@@ -171,6 +171,7 @@ int print_gpios(struct pci_dev *sb)
gpio_registers = ich9_gpio_registers;
size = ARRAY_SIZE(ich9_gpio_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH8:
case PCI_DEVICE_ID_INTEL_ICH8M:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
gpio_registers = ich8_gpio_registers;
@@ -180,6 +181,7 @@ int print_gpios(struct pci_dev *sb)
case PCI_DEVICE_ID_INTEL_ICH7M:
case PCI_DEVICE_ID_INTEL_ICH7DH:
case PCI_DEVICE_ID_INTEL_ICH7MDH:
case PCI_DEVICE_ID_INTEL_NM10:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
gpio_registers = ich7_gpio_registers;
size = ARRAY_SIZE(ich7_gpio_registers);