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acpi: Rename acpi_create_dmar_drhd

Browse Source 
For most of SoCs, DRHD is by default with the size of 4KB. However,
larger sizes are allowed as well. Rename acpi_create_dmar_drhd to
acpi_create_dmar_drhd_4k to support the default case while a later
patch will re-add acpi_create_dmar_drhd with a size parameter.

TEST=intel/archercity CRB

Change-Id: Ic0a0618aa8e46d3fec2ceac7a91742122993df91
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Shuo Liu 2024-06-25 18:50:06 +08:00 committed by Felix Held
parent 79d7f3a13e
commit f3aaa0e153
16 changed files with 37 additions and 37 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/acpi/acpi_dmar.c
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@ -36,7 +36,7 @@ void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags,
header->checksum = acpi_checksum((void *)dmar, header->length); header->checksum = acpi_checksum((void *)dmar, header->length);
} }
unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, unsigned long acpi_create_dmar_drhd_4k(unsigned long current, u8 flags,
u16 segment, u64 bar) u16 segment, u64 bar)
{ {
dmar_entry_t *drhd = (dmar_entry_t *)current; dmar_entry_t *drhd = (dmar_entry_t *)current;

2
src/include/acpi/acpi.h
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@ -1849,7 +1849,7 @@ unsigned long acpi_16550_mmio32_write_dbg2_uart(acpi_rsdp_t *rsdp, unsigned long
void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags, void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags,
unsigned long (*acpi_fill_dmar)(unsigned long)); unsigned long (*acpi_fill_dmar)(unsigned long));
unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, unsigned long acpi_create_dmar_drhd_4k(unsigned long current, u8 flags,
u16 segment, u64 bar); u16 segment, u64 bar);
unsigned long acpi_create_dmar_rmrr(unsigned long current, u16 segment, unsigned long acpi_create_dmar_rmrr(unsigned long current, u16 segment,
u64 bar, u64 limit); u64 bar, u64 limit);

8
src/northbridge/intel/gm45/acpi.c
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@ -25,13 +25,13 @@ static unsigned long acpi_fill_dmar(unsigned long current)
PCI_CLASS_REVISION); PCI_CLASS_REVISION);
unsigned long tmp = current; unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE1); current += acpi_create_dmar_drhd_4k(current, 0, 0, IOMMU_BASE1);
current += acpi_create_dmar_ds_pci(current, 0, 0x1b, 0); current += acpi_create_dmar_ds_pci(current, 0, 0x1b, 0);
acpi_dmar_drhd_fixup(tmp, current); acpi_dmar_drhd_fixup(tmp, current);
if (stepping != STEPPING_B2 && igd_active) { if (stepping != STEPPING_B2 && igd_active) {
tmp = current; tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE2); current += acpi_create_dmar_drhd_4k(current, 0, 0, IOMMU_BASE2);
current += acpi_create_dmar_ds_pci(current, 0, 0x2, 0); current += acpi_create_dmar_ds_pci(current, 0, 0x2, 0);
current += acpi_create_dmar_ds_pci(current, 0, 0x2, 1); current += acpi_create_dmar_ds_pci(current, 0, 0x2, 1);
acpi_dmar_drhd_fixup(tmp, current); acpi_dmar_drhd_fixup(tmp, current);
@ -39,7 +39,7 @@ static unsigned long acpi_fill_dmar(unsigned long current)
if (me_active) { if (me_active) {
tmp = current; tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE3); current += acpi_create_dmar_drhd_4k(current, 0, 0, IOMMU_BASE3);
current += acpi_create_dmar_ds_pci(current, 0, 0x3, 0); current += acpi_create_dmar_ds_pci(current, 0, 0x3, 0);
current += acpi_create_dmar_ds_pci(current, 0, 0x3, 1); current += acpi_create_dmar_ds_pci(current, 0, 0x3, 1);
current += acpi_create_dmar_ds_pci(current, 0, 0x3, 2); current += acpi_create_dmar_ds_pci(current, 0, 0x3, 2);
@ -47,7 +47,7 @@ static unsigned long acpi_fill_dmar(unsigned long current)
acpi_dmar_drhd_fixup(tmp, current); acpi_dmar_drhd_fixup(tmp, current);
} }
current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, IOMMU_BASE4); current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, IOMMU_BASE4);
/* TODO: reserve GTT for 0.2.0 and 0.2.1? */ /* TODO: reserve GTT for 0.2.0 and 0.2.1? */
return current; return current;

4
src/northbridge/intel/haswell/acpi.c
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@ -28,7 +28,7 @@ static unsigned long acpi_fill_dmar(unsigned long current)
if (emit_igd) { if (emit_igd) {
const unsigned long tmp = current; const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar);
current += acpi_create_dmar_ds_pci(current, 0, 2, 0); current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
acpi_dmar_drhd_fixup(tmp, current); acpi_dmar_drhd_fixup(tmp, current);
@ -37,7 +37,7 @@ static unsigned long acpi_fill_dmar(unsigned long current)
/* VTVC0BAR has to be set, enabled, and in 32-bit space */ /* VTVC0BAR has to be set, enabled, and in 32-bit space */
if (vtvc0bar && vtvc0en && !mchbar_read32(VTVC0BAR + 4)) { if (vtvc0bar && vtvc0en && !mchbar_read32(VTVC0BAR + 4)) {
const unsigned long tmp = current; const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR,
PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_BUS,
PCH_IOAPIC_PCI_SLOT, 0); PCH_IOAPIC_PCI_SLOT, 0);

4
src/northbridge/intel/sandybridge/acpi.c
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@ -34,14 +34,14 @@ static unsigned long acpi_fill_dmar(unsigned long current)
if (igfx && igfx->enabled) { if (igfx && igfx->enabled) {
const unsigned long tmp = current; const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, GFXVT_BASE); current += acpi_create_dmar_drhd_4k(current, 0, 0, GFXVT_BASE);
current += acpi_create_dmar_ds_pci(current, 0, 2, 0); current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
acpi_dmar_drhd_fixup(tmp, current); acpi_dmar_drhd_fixup(tmp, current);
} }
{ {
const unsigned long tmp = current; const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE); current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE);
current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR,
PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_BUS,

8
src/soc/intel/alderlake/acpi.c
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@ -239,7 +239,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
if (is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten) { if (is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten) {
const unsigned long tmp = current; const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar);
current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IGD, 0); current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IGD, 0);
acpi_dmar_drhd_fixup(tmp, current); acpi_dmar_drhd_fixup(tmp, current);
@ -251,7 +251,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) { if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) {
const unsigned long tmp = current; const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); current += acpi_create_dmar_drhd_4k(current, 0, 0, ipuvtbar);
current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IPU, 0); current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IPU, 0);
acpi_dmar_drhd_fixup(tmp, current); acpi_dmar_drhd_fixup(tmp, current);
@ -265,7 +265,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
if (tbtbar && tbten) { if (tbtbar && tbten) {
const unsigned long tmp = current; const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, tbtbar); current += acpi_create_dmar_drhd_4k(current, 0, 0, tbtbar);
current += acpi_create_dmar_ds_pci_br(current, 0, current += acpi_create_dmar_ds_pci_br(current, 0,
SA_DEV_SLOT_TBT, i); SA_DEV_SLOT_TBT, i);
@ -280,7 +280,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
if (vtvc0bar && vtvc0en) { if (vtvc0bar && vtvc0en) {
const unsigned long tmp = current; const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, current += acpi_create_dmar_drhd_4k(current,
DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
current += acpi_create_dmar_ds_ioapic_from_hw(current, current += acpi_create_dmar_ds_ioapic_from_hw(current,
IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV,

4
src/soc/intel/apollolake/acpi.c
View File

@ -126,7 +126,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
if (emit_igd) { if (emit_igd) {
tmp = current; tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar);
current += acpi_create_dmar_ds_pci(current, 0, 2, 0); current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
acpi_dmar_drhd_fixup(tmp, current); acpi_dmar_drhd_fixup(tmp, current);
} }
@ -138,7 +138,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
union p2sb_bdf hbdf = p2sb_get_hpet_bdf(); union p2sb_bdf hbdf = p2sb_get_hpet_bdf();
p2sb_hide(); p2sb_hide();
current += acpi_create_dmar_drhd(current, current += acpi_create_dmar_drhd_4k(current,
DRHD_INCLUDE_PCI_ALL, 0, defvtbar); DRHD_INCLUDE_PCI_ALL, 0, defvtbar);
current += acpi_create_dmar_ds_ioapic_from_hw(current, current += acpi_create_dmar_ds_ioapic_from_hw(current,
IO_APIC_ADDR, ibdf.bus, ibdf.dev, ibdf.fn); IO_APIC_ADDR, ibdf.bus, ibdf.dev, ibdf.fn);

4
src/soc/intel/broadwell/acpi.c
View File

@ -38,7 +38,7 @@ static unsigned long acpi_fill_dmar(unsigned long current)
if (emit_igd) { if (emit_igd) {
const unsigned long tmp = current; const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar);
current += acpi_create_dmar_ds_pci(current, 0, 2, 0); current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
acpi_dmar_drhd_fixup(tmp, current); acpi_dmar_drhd_fixup(tmp, current);
@ -47,7 +47,7 @@ static unsigned long acpi_fill_dmar(unsigned long current)
/* VTVC0BAR has to be set, enabled, and in 32-bit space */ /* VTVC0BAR has to be set, enabled, and in 32-bit space */
if (vtvc0bar && vtvc0en && !mchbar_read32(VTVC0BAR + 4)) { if (vtvc0bar && vtvc0en && !mchbar_read32(VTVC0BAR + 4)) {
const unsigned long tmp = current; const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, current += acpi_create_dmar_drhd_4k(current,
DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
current += acpi_create_dmar_ds_ioapic_from_hw(current, current += acpi_create_dmar_ds_ioapic_from_hw(current,
IO_APIC_ADDR, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); IO_APIC_ADDR, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0);

6
src/soc/intel/cannonlake/acpi.c
View File

@ -261,7 +261,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
if (emit_igd) { if (emit_igd) {
unsigned long tmp = current; unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar);
current += acpi_create_dmar_ds_pci(current, 0, 2, 0); current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
acpi_dmar_drhd_fixup(tmp, current); acpi_dmar_drhd_fixup(tmp, current);
@ -273,7 +273,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) { if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) {
unsigned long tmp = current; unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); current += acpi_create_dmar_drhd_4k(current, 0, 0, ipuvtbar);
current += acpi_create_dmar_ds_pci(current, 0, 5, 0); current += acpi_create_dmar_ds_pci(current, 0, 5, 0);
acpi_dmar_drhd_fixup(tmp, current); acpi_dmar_drhd_fixup(tmp, current);
@ -285,7 +285,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
if (vtvc0bar && vtvc0en) { if (vtvc0bar && vtvc0en) {
const unsigned long tmp = current; const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, current += acpi_create_dmar_drhd_4k(current,
DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
current += acpi_create_dmar_ds_ioapic_from_hw(current, current += acpi_create_dmar_ds_ioapic_from_hw(current,
IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV,

2
src/soc/intel/denverton_ns/acpi.c
View File

@ -173,7 +173,7 @@ static unsigned long acpi_fill_dmar(unsigned long current)
if (!vtbar) if (!vtbar)
return current; return current;
current += acpi_create_dmar_drhd(current, current += acpi_create_dmar_drhd_4k(current,
DRHD_INCLUDE_PCI_ALL, 0, vtbar); DRHD_INCLUDE_PCI_ALL, 0, vtbar);
current += acpi_create_dmar_ds_ioapic_from_hw(current, current += acpi_create_dmar_ds_ioapic_from_hw(current,

4
src/soc/intel/elkhartlake/acpi.c
View File

@ -175,7 +175,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
if (is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten) { if (is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten) {
unsigned long tmp = current; unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar);
current += acpi_create_dmar_ds_pci(current, 0, 2, 0); current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
acpi_dmar_drhd_fixup(tmp, current); acpi_dmar_drhd_fixup(tmp, current);
@ -187,7 +187,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
if (vtvc0bar && vtvc0en) { if (vtvc0bar && vtvc0en) {
const unsigned long tmp = current; const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, current += acpi_create_dmar_drhd_4k(current,
DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
current += acpi_create_dmar_ds_ioapic_from_hw(current, current += acpi_create_dmar_ds_ioapic_from_hw(current,
IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV,

6
src/soc/intel/jasperlake/acpi.c
View File

@ -173,7 +173,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
if (is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten) { if (is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten) {
unsigned long tmp = current; unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar);
current += acpi_create_dmar_ds_pci(current, 0, 2, 0); current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
acpi_dmar_drhd_fixup(tmp, current); acpi_dmar_drhd_fixup(tmp, current);
@ -185,7 +185,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) { if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) {
unsigned long tmp = current; unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); current += acpi_create_dmar_drhd_4k(current, 0, 0, ipuvtbar);
current += acpi_create_dmar_ds_pci(current, 0, 5, 0); current += acpi_create_dmar_ds_pci(current, 0, 5, 0);
acpi_dmar_drhd_fixup(tmp, current); acpi_dmar_drhd_fixup(tmp, current);
@ -197,7 +197,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
if (vtvc0bar && vtvc0en) { if (vtvc0bar && vtvc0en) {
const unsigned long tmp = current; const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, current += acpi_create_dmar_drhd_4k(current,
DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
current += acpi_create_dmar_ds_ioapic_from_hw(current, current += acpi_create_dmar_ds_ioapic_from_hw(current,
IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV,

4
src/soc/intel/meteorlake/acpi.c
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@ -235,14 +235,14 @@ static unsigned long soc_fill_dmar(unsigned long current)
__func__, gfxvtbar, MCHBAR32(GFXVTBAR)); __func__, gfxvtbar, MCHBAR32(GFXVTBAR));
if (is_devfn_enabled(PCI_DEVFN_IGD) && gfxvtbar && gfxvten) { if (is_devfn_enabled(PCI_DEVFN_IGD) && gfxvtbar && gfxvten) {
tmp = current; tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar);
current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IGD, 0); current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IGD, 0);
acpi_dmar_drhd_fixup(tmp, current); acpi_dmar_drhd_fixup(tmp, current);
} }
tmp = current; tmp = current;
current += acpi_create_dmar_drhd(current, current += acpi_create_dmar_drhd_4k(current,
DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE_ADDRESS); DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE_ADDRESS);
current += acpi_create_dmar_ds_ioapic_from_hw(current, current += acpi_create_dmar_ds_ioapic_from_hw(current,
IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV,

4
src/soc/intel/skylake/acpi.c
View File

@ -193,7 +193,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
if (emit_igd) { if (emit_igd) {
const unsigned long tmp = current; const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, gfx_vtbar); current += acpi_create_dmar_drhd_4k(current, 0, 0, gfx_vtbar);
current += acpi_create_dmar_ds_pci(current, 0, 2, 0); current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
acpi_dmar_drhd_fixup(tmp, current); acpi_dmar_drhd_fixup(tmp, current);
@ -206,7 +206,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) {
const unsigned long tmp = current; const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, V_P2SB_IBDF_BUS, current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, V_P2SB_IBDF_BUS,
V_P2SB_IBDF_DEV, V_P2SB_IBDF_FUN); V_P2SB_IBDF_DEV, V_P2SB_IBDF_FUN);

8
src/soc/intel/tigerlake/acpi.c
View File

@ -232,7 +232,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
if (is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten) { if (is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten) {
unsigned long tmp = current; unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar);
current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IGD, 0); current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IGD, 0);
acpi_dmar_drhd_fixup(tmp, current); acpi_dmar_drhd_fixup(tmp, current);
@ -244,7 +244,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) { if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) {
unsigned long tmp = current; unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); current += acpi_create_dmar_drhd_4k(current, 0, 0, ipuvtbar);
current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IPU, 0); current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IPU, 0);
acpi_dmar_drhd_fixup(tmp, current); acpi_dmar_drhd_fixup(tmp, current);
@ -257,7 +257,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
if (tbtbar && tbten) { if (tbtbar && tbten) {
unsigned long tmp = current; unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, tbtbar); current += acpi_create_dmar_drhd_4k(current, 0, 0, tbtbar);
current += acpi_create_dmar_ds_pci_br(current, 0, current += acpi_create_dmar_ds_pci_br(current, 0,
SA_DEV_SLOT_TBT, i); SA_DEV_SLOT_TBT, i);
@ -271,7 +271,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
if (vtvc0bar && vtvc0en) { if (vtvc0bar && vtvc0en) {
const unsigned long tmp = current; const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, current += acpi_create_dmar_drhd_4k(current,
DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
current += acpi_create_dmar_ds_ioapic_from_hw(current, current += acpi_create_dmar_ds_ioapic_from_hw(current,
IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV,

4
src/soc/intel/xeon_sp/uncore_acpi.c
View File

@ -272,12 +272,12 @@ static unsigned long acpi_create_drhd(unsigned long current, struct device *iomm
printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, "
"Register Base Address: 0x%x\n", "Register Base Address: 0x%x\n",
DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base);
current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL,
pcie_seg, reg_base); pcie_seg, reg_base);
} else { } else {
printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, "
"Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base);
current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base); current += acpi_create_dmar_drhd_4k(current, 0, pcie_seg, reg_base);
} }
// Add PCH IOAPIC // Add PCH IOAPIC