From f3c107eb01cae5347b487d75462e36a455f9ec48 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Thu, 15 Dec 2022 06:43:56 +0100
Subject: [PATCH] soc/intel/apollolake/acpi/northbridge.asl: Fix comment

This fixes the following error:
In file included from src/mainboard/siemens/mc_apl1/dsdt.asl:21:
src/soc/intel/apollolake/acpi/northbridge.asl:15:12: warning: '/*' within block comment [-Wcomment]
                PXEN,   1,      /* Enable */
                                ^

Change-Id: I1173eed69847f4c3b307ce96d76fb7185dc2f85c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70767
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
---
 src/soc/intel/apollolake/acpi/northbridge.asl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl
index 373d6b8ea4..2230433686 100644
--- a/src/soc/intel/apollolake/acpi/northbridge.asl
+++ b/src/soc/intel/apollolake/acpi/northbridge.asl
@@ -11,7 +11,7 @@ Device (MCHC)
 	OperationRegion (MCHP, PCI_Config, 0x00, 0x100)
 	Field (MCHP, DWordAcc, NoLock, Preserve)
 	{
-		Offset (0x60),	/* PCIEXBAR (0:0:0:60)
+		Offset (0x60),	/* PCIEXBAR (0:0:0:60) */
 		PXEN,	1,	/* Enable */
 		PXSZ,	2,	/* PCI Express Size */
 		    ,	25,