mb/foxconn/g41s-k: Add g41m variant

Was tested with the following:
- 2 DIMM slots
- USB
- Ethernet NIC
- automatic fan control
- Libgfxinit with VGA, DVI (HDMI slot unpopulated)
- PS2 Keyboard
- SATA
- PEG
- S3 resume

What does not work:
- Using the second DIMM slot on a channel
  G41 can only handle 2 ranks per channel and on this mainboard 1 rank
  per DIMM slot. Supporting this would require too much raminit rework
  and is not worth it (at least for me)

Change-Id: I67784038ef929f561b82365f00db70a69c024321
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/mainboard/foxconn/g41s-k/Kconfig

@@ -14,7 +14,7 @@
 ## GNU General Public License for more details.
 ##
 
-if BOARD_FOXCONN_G41S_K
+if BOARD_FOXCONN_G41S_K || BOARD_FOXCONN_G41M
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
@@ -39,9 +39,18 @@ config MAINBOARD_DIR
 	string
 	default "foxconn/g41s-k"
 
+config VARIANT_DIR
+	default "g41s-k" if BOARD_FOXCONN_G41S_K
+	default "g41m" if BOARD_FOXCONN_G41M
+
 config MAINBOARD_PART_NUMBER
 	string
-	default "G41S-K"
+	default "G41S-K" if BOARD_FOXCONN_G41S_K
+	default "G41M/G41M-S/G41M-V" if BOARD_FOXCONN_G41M
+
+config OVERRIDE_DEVICETREE
+	string
+	default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
 
 config MAX_CPUS
 	int

src/mainboard/foxconn/g41s-k/Kconfig.name

@@ -1,2 +1,4 @@
 config BOARD_FOXCONN_G41S_K
 	bool "G41S-K"
+config BOARD_FOXCONN_G41M
+	bool "G41M/G41M-S/G41M-V"

src/mainboard/foxconn/g41s-k/Makefile.inc

@@ -1,4 +1,6 @@
 ramstage-y += cstates.c
 romstage-y += gpio.c
 
-ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/

src/mainboard/foxconn/g41s-k/acpi/superio.asl

@@ -26,10 +26,14 @@
 #define SUPERIO_DEV		SIO0
 #define SUPERIO_PNP_BASE	0x2e
 #define IT8720F_SHOW_SP1	1
+#if IS_ENABLED(CONFIG_BOARD_FOXCONN_G41S_K)
 #define IT8720F_SHOW_SP2	1
+#endif
 #define IT8720F_SHOW_EC		1
 #define IT8720F_SHOW_KBCK	1
 #define IT8720F_SHOW_KBCM	1
 #define IT8720F_SHOW_GPIO	1
+#if IS_ENABLED(CONFIG_BOARD_FOXCONN_G41S_K)
 #define IT8720F_SHOW_CIR	1
+#endif
 #include <superio/ite/it8720f/acpi/superio.asl>

src/mainboard/foxconn/g41s-k/devicetree.cb

@@ -26,7 +26,6 @@ chip northbridge/intel/x4x		# Northbridge
 		end
 	end
 	device domain 0 on		# PCI domain
-		subsystemid 0x105b 0x0dda inherit
 		device pci 0.0 on end			# Host Bridge
 		device pci 1.0 on end			# PEG
 		device pci 2.0 on end			# Integrated graphics controller

src/mainboard/foxconn/g41s-k/hda_verb.c

@@ -17,6 +17,7 @@
 
 #include <device/azalia_device.h>
 
+#if IS_ENABLED(CONFIG_BOARD_FOXCONN_G41S_K)
 const u32 cim_verb_data[] = {
 	/* coreboot specific header */
 	0x10ec0888, /* Vendor ID */
@@ -40,6 +41,31 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x1e, 0x01441130),
 	AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
 };
+#else /* CONFIG_BOARD_FOXCONN_G41M */
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0888, /* Vendor ID */
+	0x105b0dc0, /* Subsystem ID */
+	0x0000000e, /* Number of entries */
+
+	/* Pin Widget Verb Table */
+
+	AZALIA_PIN_CFG(2, 0x11, 0x01441140),
+	AZALIA_PIN_CFG(2, 0x12, 0x411111f0),
+	AZALIA_PIN_CFG(2, 0x14, 0x01014410),
+	AZALIA_PIN_CFG(2, 0x15, 0x01011412),
+	AZALIA_PIN_CFG(2, 0x16, 0x01016411),
+	AZALIA_PIN_CFG(2, 0x17, 0x01012414),
+	AZALIA_PIN_CFG(2, 0x18, 0x01a19c50),
+	AZALIA_PIN_CFG(2, 0x19, 0x02a19c60),
+	AZALIA_PIN_CFG(2, 0x1a, 0x0181345f),
+	AZALIA_PIN_CFG(2, 0x1b, 0x02014c20),
+	AZALIA_PIN_CFG(2, 0x1c, 0x593301f0),
+	AZALIA_PIN_CFG(2, 0x1d, 0x4007f603),
+	AZALIA_PIN_CFG(2, 0x1e, 0x99430130),
+	AZALIA_PIN_CFG(2, 0x1f, 0x411111f0),
+};
+#endif
 
 const u32 pc_beep_verbs[0] = {};
 

src/mainboard/foxconn/g41s-k/romstage.c

@@ -72,7 +72,7 @@ static void ich7_enable_lpc(void)
 {
 	pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010);
 	pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |
-		COMB_LPC_EN | COMA_LPC_EN);
+			FDD_LPC_EN | COMB_LPC_EN | COMA_LPC_EN);
 
 	/* Decode 64 bytes at 0x0a00 to LPC for Super I/O EC and GPIO. */
 	pci_write_config32(LPC_DEV, GEN1_DEC, 0x003c0a01);
@@ -81,7 +81,13 @@ static void ich7_enable_lpc(void)
 void mainboard_romstage_entry(unsigned long bist)
 {
 	//                          ch0      ch1
+#if IS_ENABLED(CONFIG_BOARD_FOXCONN_G41S_K)
 	const u8 spd_addrmap[4] = { 0x50, 0, 0, 0 };
+#else
+	/* TODO adapt raminit such that other slots can be used
+	 * for single rank dimms */
+	const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
+#endif
 	u8 boot_path = 0;
 	u8 s3_resume;
 

src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl

@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+ * Copyright (C) 2017 Samuel Holland <samuel@sholland.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+m *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This is board specific information:
+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH7
+ */
+
+If (PICM) {
+	Return (Package() {
+		Package() { 0x0001ffff, 0, 0, 0x12},
+		Package() { 0x0001ffff, 1, 0, 0x13},
+		Package() { 0x0001ffff, 2, 0, 0x10},
+		Package() { 0x0001ffff, 3, 0, 0x11},
+
+		Package() { 0x0002ffff, 0, 0, 0x11},
+		Package() { 0x0002ffff, 1, 0, 0x12},
+		Package() { 0x0002ffff, 2, 0, 0x13},
+		Package() { 0x0002ffff, 3, 0, 0x10},
+	})
+} Else {
+	Return (Package() {
+		Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKD, 0},
+		Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+
+		Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0},
+		Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKA, 0},
+		Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKB, 0},
+	})
+}

src/mainboard/foxconn/g41s-k/variants/g41m/gma-mainboard.ads

@@ -0,0 +1,29 @@
+--
+-- This file is part of the coreboot project.
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (Analog,
+      HDMI1,
+      HDMI2,
+      others => Disabled);
+
+end GMA.Mainboard;

src/mainboard/foxconn/g41s-k/variants/g41m/overridetree.cb

@@ -0,0 +1,17 @@
+chip northbridge/intel/x4x		# Northbridge
+	device domain 0 on		# PCI domain
+		subsystemid 0x105b 0x0dc0 inherit
+		chip southbridge/intel/i82801gx		# Southbridge
+			device pci 1f.0 on		# ISA bridge
+				device pnp 2e.0 on	# Floppy
+					io 0x60 = 0x3f0
+					irq 0x70 = 6
+					drq 0x74 = 2
+				end
+				device pnp 2e.2 off end	# COM2 (IR)
+				device pnp 2e.a off end	# CIR
+			end
+			device pci 1f.1 on end		# PATA/IDE
+		end
+	end
+end

src/mainboard/foxconn/g41s-k/variants/g41s-k/overridetree.cb

@@ -0,0 +1,5 @@
+chip northbridge/intel/x4x		# Northbridge
+	device domain 0 on		# PCI domain
+		subsystemid 0x105b 0x0dda inherit
+	end
+end