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sb/intel: Don't set ACPI_EN twice

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It is already done once when enabling PMBASE in early init.

Change-Id: I14289c9164ee1488c192fce721d86c89fa5cc736
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons
2020-11-04 00:38:28 +01:00
parent 4b519f7c62
commit f47117134d
7 changed files with 3 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/southbridge/intel/bd82x6x/early_pch.c
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@@ -222,7 +222,7 @@ static void pch_enable_bars(void)
pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1);
pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN);
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);

3
src/southbridge/intel/bd82x6x/lpc.c
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@@ -44,9 +44,6 @@ static void pch_enable_ioapic(struct device *dev)
pci_write_config16(dev, LPC_IBDF, pci_write_config16(dev, LPC_IBDF,
PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3); PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
/* Enable ACPI I/O range decode */
pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
set_ioapic_id(VIO_APIC_VADDR, 0x02); set_ioapic_id(VIO_APIC_VADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */ /* affirm full set of redirection table entries ("write once") */

3
src/southbridge/intel/i82801gx/lpc.c
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@@ -35,9 +35,6 @@
*/ */
static void i82801gx_enable_ioapic(struct device *dev) static void i82801gx_enable_ioapic(struct device *dev)
{ {
/* Enable ACPI I/O range decode */
pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
set_ioapic_id(VIO_APIC_VADDR, 0x02); set_ioapic_id(VIO_APIC_VADDR, 0x02);
/* /*

2
src/southbridge/intel/ibexpeak/early_pch.c
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@@ -33,7 +33,7 @@ void ibexpeak_setup_bars(void)
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
/* Enable ACPI BAR */ /* Enable ACPI BAR */
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN);
printk(BIOS_DEBUG, " done.\n"); printk(BIOS_DEBUG, " done.\n");

3
src/southbridge/intel/ibexpeak/lpc.c
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@@ -39,9 +39,6 @@ static void pch_enable_ioapic(struct device *dev)
{ {
u32 reg32; u32 reg32;
/* Enable ACPI I/O range decode */
pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
set_ioapic_id(VIO_APIC_VADDR, 0x01); set_ioapic_id(VIO_APIC_VADDR, 0x01);
/* affirm full set of redirection table entries ("write once") */ /* affirm full set of redirection table entries ("write once") */
reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); reg32 = io_apic_read(VIO_APIC_VADDR, 0x01);

2
src/southbridge/intel/lynxpoint/early_pch.c
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@@ -40,7 +40,7 @@ static void pch_enable_bars(void)
pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1);
/* Enable ACPI BAR */ /* Enable ACPI BAR */
pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN);
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);

3
src/southbridge/intel/lynxpoint/lpc.c
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@@ -41,9 +41,6 @@ static void pch_enable_ioapic(struct device *dev)
pci_write_config16(dev, LPC_IBDF, pci_write_config16(dev, LPC_IBDF,
PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3); PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
/* Enable ACPI I/O range decode */
pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
set_ioapic_id(VIO_APIC_VADDR, 0x02); set_ioapic_id(VIO_APIC_VADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */ /* affirm full set of redirection table entries ("write once") */