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sb/intel: Use boolean for pcie_hotplug_map attribute

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Change-Id: Ia5e1ee683fa3d8d216ece26426e9870981ede2ba
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79932
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer
2024-01-12 21:21:06 +01:00
committed by Felix Singer
parent d04378118d
commit f4842bbc14
5 changed files with 10 additions and 5 deletions
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2
src/southbridge/intel/bd82x6x/chip.h
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@@ -65,7 +65,7 @@ struct southbridge_intel_bd82x6x_config {
int docking_supported; int docking_supported;
uint8_t pcie_hotplug_map[8]; bool pcie_hotplug_map[8];
/* Ports which can be routed to either EHCI or xHCI. */ /* Ports which can be routed to either EHCI or xHCI. */
uint32_t xhci_switchable_ports; uint32_t xhci_switchable_ports;

3
src/southbridge/intel/common/pciehp.c
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@@ -4,10 +4,11 @@
#include <acpi/acpigen.h> #include <acpi/acpigen.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <stdbool.h>
#include "pciehp.h" #include "pciehp.h"
void intel_acpi_pcie_hotplug_generator(u8 *hotplug_map, int port_number) void intel_acpi_pcie_hotplug_generator(bool *hotplug_map, int port_number)
{ {
int port; int port;
int have_hotplug = 0; int have_hotplug = 0;

4
src/southbridge/intel/common/pciehp.h
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@@ -1,9 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <stdbool.h>
#ifndef SOUTHBRIDGE_INTEL_COMMON_PCIEHP_H #ifndef SOUTHBRIDGE_INTEL_COMMON_PCIEHP_H
#define SOUTHBRIDGE_INTEL_COMMON_PCIEHP_H #define SOUTHBRIDGE_INTEL_COMMON_PCIEHP_H
void intel_acpi_pcie_hotplug_generator(u8 *hotplug_map, int port_number); void intel_acpi_pcie_hotplug_generator(bool *hotplug_map, int port_number);
void intel_acpi_pcie_hotplug_scan_slot(struct bus *bus); void intel_acpi_pcie_hotplug_scan_slot(struct bus *bus);
#endif #endif

3
src/southbridge/intel/i82801ix/chip.h
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@@ -3,6 +3,7 @@
#ifndef SOUTHBRIDGE_INTEL_I82801IX_CHIP_H #ifndef SOUTHBRIDGE_INTEL_I82801IX_CHIP_H
#define SOUTHBRIDGE_INTEL_I82801IX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801IX_CHIP_H
#include <stdbool.h>
#include <stdint.h> #include <stdint.h>
enum { enum {
@@ -73,7 +74,7 @@ struct southbridge_intel_i82801ix_config {
uint8_t scale : 2; uint8_t scale : 2;
} pcie_power_limits[6]; } pcie_power_limits[6];
uint8_t pcie_hotplug_map[8]; bool pcie_hotplug_map[8];
/* Additional LPC IO decode ranges */ /* Additional LPC IO decode ranges */
uint32_t gen1_dec; uint32_t gen1_dec;

3
src/southbridge/intel/i82801jx/chip.h
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@@ -3,6 +3,7 @@
#ifndef SOUTHBRIDGE_INTEL_I82801JX_CHIP_H #ifndef SOUTHBRIDGE_INTEL_I82801JX_CHIP_H
#define SOUTHBRIDGE_INTEL_I82801JX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801JX_CHIP_H
#include <stdbool.h>
#include <stdint.h> #include <stdint.h>
enum { enum {
@@ -59,7 +60,7 @@ struct southbridge_intel_i82801jx_config {
uint8_t scale : 2; uint8_t scale : 2;
} pcie_power_limits[6]; } pcie_power_limits[6];
uint8_t pcie_hotplug_map[8]; bool pcie_hotplug_map[8];
/* Additional LPC IO decode ranges */ /* Additional LPC IO decode ranges */
uint32_t gen1_dec; uint32_t gen1_dec;