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Geode LX: this patch adds configuration/status/self-test MSR definitions

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for L2 cache and fixes wrong  P2D defines.
This also patch adds L2 cache initialization for Geode LX CPU.

Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Indrek Kruusa
2006-08-02 11:30:32 +00:00
committed by Stefan Reinauer
parent 4278e99383
commit f4c0b596a2
2 changed files with 49 additions and 3 deletions
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30
src/cpu/amd/model_lx/model_lx_init.c
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@ -5,7 +5,7 @@
#include <cpu/cpu.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/cache.h>
#include <cpu/amd/lxdef.h>
static void vsm_end_post_smi(void)
{
@ -19,9 +19,37 @@ static void vsm_end_post_smi(void)
static void model_lx_init(device_t dev)
{
msr_t msr;
printk_debug("model_lx_init\n");
/* Turn on caching if we haven't already */
/* Instruction Memory Configuration register
* set EBE bit, required when L2 cache is enabled
*/
msr = rdmsr(CPU_IM_CONFIG);
msr.lo |= 0x400;
wrmsr(CPU_IM_CONFIG, msr);
/* Data Memory Subsystem Configuration register
* set EVCTONRPL bit, required when L2 cache is enabled in victim mode
*/
msr = rdmsr(CPU_DM_CONFIG0);
msr.lo |= 0x4000;
wrmsr(CPU_DM_CONFIG0, msr);
/* invalidate L2 cache */
msr.hi = 0x00;
msr.lo = 0x10;
wrmsr(L2_CONFIG_MSR, msr);
/* Enable L2 cache */
msr.hi = 0x00;
msr.lo = 0x0f;
wrmsr(L2_CONFIG_MSR, msr);
x86_enable_cache();
/* Enable the local cpu apics */