3rdparty: Move to blobs

To move 3rdparty to 3rdparty/blobs (ie. below itself
from git's broken perspective), we need to work around
it - since some git implementations don't like the direct
approach.

Change-Id: I1fc84bbb37e7c8c91ab14703d609a739b5ca073c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10108
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/cpu/amd/geode_gx2/Makefile.inc

@@ -11,4 +11,4 @@ cpu_incs += $(src)/cpu/amd/geode_gx2/cache_as_ram.inc
 cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa
 vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa
 vsa-type = stage
-vsa-required = VSA binary (binary and MASM source code available in coreboot/3rdparty repository)
+vsa-required = VSA binary (binary and MASM source code available in coreboot/blobs repository)

src/cpu/amd/geode_lx/Kconfig

@@ -37,7 +37,7 @@ config GEODE_VSA_FILE
 config VSA_FILENAME
 	string "AMD Geode LX VSA path and filename"
 	depends on GEODE_VSA_FILE
-	default "3rdparty/cpu/amd/geode_lx/gpl_vsa_lx_102.bin"
+	default "blobs/cpu/amd/geode_lx/gpl_vsa_lx_102.bin"
 	help
 	  The path and filename of the file to use as VSA.
 

src/cpu/amd/geode_lx/Makefile.inc

@@ -11,4 +11,4 @@ cpu_incs += $(src)/cpu/amd/geode_lx/cache_as_ram.inc
 cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa
 vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa
 vsa-type = stage
-vsa-required = VSA binary (binary and MASM source code available in coreboot/3rdparty repository)
+vsa-required = VSA binary (binary and MASM source code available in coreboot/blobs repository)

src/cpu/intel/haswell/microcode_blob.c

@@ -23,8 +23,8 @@ unsigned microcode[] = {
 	 * a very good reason why we only use one at a time?
 	 */
 	#if CONFIG_INTEL_LYNXPOINT_LP
-	#include "../../../../3rdparty/cpu/intel/model_4065x/microcode.h"
+	#include "../../../../blobs/cpu/intel/model_4065x/microcode.h"
 	#else
-	#include "../../../../3rdparty/cpu/intel/model_306cx/microcode.h"
+	#include "../../../../blobs/cpu/intel/model_306cx/microcode.h"
 	#endif
 };

src/cpu/intel/model_1067x/microcode_blob.c

@@ -1,3 +1,3 @@
 unsigned microcode_updates_1067ax[] = {
-	#include "../../../../3rdparty/cpu/intel/model_1067x/microcode.h"
+	#include "../../../../blobs/cpu/intel/model_1067x/microcode.h"
 };

src/cpu/intel/model_106cx/microcode_blob.c

@@ -1,3 +1,3 @@
 unsigned microcode_updates_106cx[] = {
-	#include "../../../../3rdparty/cpu/intel/model_106cx/microcode.h"
+	#include "../../../../blobs/cpu/intel/model_106cx/microcode.h"
 };

src/cpu/intel/model_2065x/microcode_blob.c

@@ -18,5 +18,5 @@
  */
 
 unsigned microcode[] = {
-	#include "../../../../3rdparty/cpu/intel/model_2065x/microcode.h"
+	#include "../../../../blobs/cpu/intel/model_2065x/microcode.h"
 };

src/cpu/intel/model_206ax/microcode_blob.c

@@ -18,5 +18,5 @@
  */
 
 unsigned microcode[] = {
-	#include "../../../../3rdparty/cpu/intel/model_206ax/microcode.h"
+	#include "../../../../blobs/cpu/intel/model_206ax/microcode.h"
 };

src/cpu/intel/model_65x/microcode_blob.c

@@ -1,3 +1,3 @@
 unsigned microcode_updates_65x[] = {
-	#include "../../../../3rdparty/cpu/intel/model_65x/microcode.h"
+	#include "../../../../blobs/cpu/intel/model_65x/microcode.h"
 };

src/cpu/intel/model_67x/microcode_blob.c

@@ -1,3 +1,3 @@
 unsigned microcode_updates_67x[] = {
-	#include "../../../../3rdparty/cpu/intel/model_67x/microcode.h"
+	#include "../../../../blobs/cpu/intel/model_67x/microcode.h"
 };

src/cpu/intel/model_68x/microcode_blob.c

@@ -1,3 +1,3 @@
 unsigned microcode_updates_68x[] = {
-	#include "../../../../3rdparty/cpu/intel/model_68x/microcode.h"
+	#include "../../../../blobs/cpu/intel/model_68x/microcode.h"
 };

src/cpu/intel/model_69x/microcode_blob.c

@@ -1,3 +1,3 @@
 unsigned microcode_updates_69x[] = {
-	#include "../../../../3rdparty/cpu/intel/model_69x/microcode.h"
+	#include "../../../../blobs/cpu/intel/model_69x/microcode.h"
 };

src/cpu/intel/model_6bx/microcode_blob.c

@@ -1,3 +1,3 @@
 unsigned microcode_updates_6bx[] = {
-	#include "../../../../3rdparty/cpu/intel/model_6bx/microcode.h"
+	#include "../../../../blobs/cpu/intel/model_6bx/microcode.h"
 };

src/cpu/intel/model_6dx/microcode_blob.c

@@ -1,3 +1,3 @@
 unsigned microcode_updates_6dx[] = {
-	#include "../../../../3rdparty/cpu/intel/model_6dx/microcode.h"
+	#include "../../../../blobs/cpu/intel/model_6dx/microcode.h"
 };

src/cpu/intel/model_6ex/microcode_blob.c

@@ -1,3 +1,3 @@
 unsigned microcode_updates_6ex[] = {
-	#include "../../../../3rdparty/cpu/intel/model_6ex/microcode.h"
+	#include "../../../../blobs/cpu/intel/model_6ex/microcode.h"
 };

src/cpu/intel/model_6fx/microcode_blob.c

@@ -1,3 +1,3 @@
 unsigned microcode_updates_6fx[] = {
-	#include "../../../../3rdparty/cpu/intel/model_6fx/microcode.h"
+	#include "../../../../blobs/cpu/intel/model_6fx/microcode.h"
 };

src/cpu/intel/model_6xx/microcode_blob.c

@@ -1,3 +1,3 @@
 unsigned microcode_updates_6xx[] = {
-	#include "../../../../3rdparty/cpu/intel/model_6xx/microcode.h"
+	#include "../../../../blobs/cpu/intel/model_6xx/microcode.h"
 };

src/cpu/intel/model_f0x/microcode_blob.c

@@ -1,4 +1,4 @@
 /* 256KB cache */
 unsigned microcode_updates_f0x[] = {
-	#include "../../../../3rdparty/cpu/intel/model_f0x/microcode.h"
+	#include "../../../../blobs/cpu/intel/model_f0x/microcode.h"
 };

src/cpu/intel/model_f1x/microcode_blob.c

@@ -1,4 +1,4 @@
 /* 256KB cache */
 unsigned microcode_updates_f1x[] = {
-	#include "../../../../3rdparty/cpu/intel/model_f1x/microcode.h"
+	#include "../../../../blobs/cpu/intel/model_f1x/microcode.h"
 };

src/cpu/intel/model_f2x/microcode_blob.c

@@ -1,4 +1,4 @@
 /* 512KB cache */
 unsigned microcode_updates_f2x[] = {
-	#include "../../../../3rdparty/cpu/intel/model_f2x/microcode.h"
+	#include "../../../../blobs/cpu/intel/model_f2x/microcode.h"
 };

src/cpu/intel/model_f3x/microcode_blob.c

@@ -1,3 +1,3 @@
 unsigned microcode_updates_f3x[] = {
-	#include "../../../../3rdparty/cpu/intel/model_f3x/microcode.h"
+	#include "../../../../blobs/cpu/intel/model_f3x/microcode.h"
 };

src/cpu/intel/model_f4x/microcode_blob.c

@@ -1,3 +1,3 @@
 unsigned microcode_updates_f4x[] = {
-	#include "../../../../3rdparty/cpu/intel/model_f4x/microcode.h"
+	#include "../../../../blobs/cpu/intel/model_f4x/microcode.h"
 };

src/cpu/samsung/exynos5250/update-bl1.sh

@@ -1,7 +1,7 @@
 #!/bin/sh
 
 BL1_NAME="E5250.nbl1.bin"
-BL1_PATH="3rdparty/cpu/samsung/exynos5250/"
+BL1_PATH="blobs/cpu/samsung/exynos5250/"
 BL1_URL="http://commondatastorage.googleapis.com/chromeos-localmirror/distfiles/exynos-pre-boot-0.0.2-r8.tbz2"
 
 get_bl1() {